JP2007179602A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory cell of a high speed/low voltage DRAM running under a voltage of 1 V or lower and array peripheral circuits thereof. <P>SOLUTION: A DRAM cell is composed of a memory cell transistor in a FD-SOI MOST structure and a planer capacitor. Since it has no junction leakage current, it does not lose the accumulated charge and can operate under a low voltage. Further, the gate and well are connected in a cross coupled sense amplifier using a FD-SOI MOST. Thus, the threshold dynamically changes to achieve high-speed sensing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit in which a CMOS circuit is integrated on a semiconductor chip. More specifically, the present invention relates to a circuit system and a device system for realizing a low voltage and high speed operation of a MOS dynamic random access memory (DRAM).

In MOS transistors (MOST), the variation in threshold voltage V _T of MOST increases with miniaturization, so that the operating speed of MOST in a chip becomes more and more varied. This speed variation becomes more prominent as the operating voltage V _DD decreases. Therefore, the low-voltage operation has come to a small variation MOST of V _T are desired. FIG. 9 (b), is a diagram published in non-patent document 1, as shown, the standard deviation σ of the variations in V _T increases with miniaturization of bulk MOST. Figure sigma _int is the standard deviation of the so-called intrinsic V _T determined by the variation in the number of variations and its position of the impurity atoms in the channel of the MOST, sigma _ext is the so-called extrinsic V _T determined by the variation of such dimensions of the channel Is the standard deviation. Overall V _T variation σ is determined by the variation of both. Even if the microfabrication technology is about 90 nm, σ can be about 30 mV. Since it is necessary to design in consideration of a V _T variation (ΔV _T ) of about 5σ in one chip, this value is 150 mV. Therefore, the effective gate voltage of each MOST in the chip represented by V _DD − (V _T0 + ΔV _T ) varies greatly. Here, V _T0 is an average V _T. Since this gate voltage is substantially proportional to the load drive current of MOST, for example, when V _T0 = 0.3 V and ΔV _T = 150 mV, the drive current of MOST decreases rapidly when V _DD becomes 1 V or less. At 45V, the drive current becomes zero and the circuit delay time becomes infinite. Such V _T variation, (the difference in V _T pairs MOST) offset voltage of the sense amplifier to be used such as dynamic random access memory (DRAM) is also increased, to destabilize the sensing operation.

  In order to suppress such speed variation and instability of operation due to such miniaturization and voltage reduction, a fully depleted SOI (Silicon On Insulator (SOI) with a fully depleted double gate structure (hereinafter referred to as FD-SOI). The detailed structure and characteristics of the SOIMOST are described in Non-Patent Document 2.

The outline of the structure shown in Non-Patent Document 2 is shown below. FIG. 9A is a cross-sectional view and an equivalent circuit of an N-channel MOST (NMOST) and a P-channel MOST (PMOST), respectively. The gate G is a metal silicide film gate electrode such as NiSi, the channel forming part immediately below the gate is a single crystal semiconductor thin film (SOI layer), D or S is a P-type or N-type highly concentrated ultrathin drain or source diffusion layer, and BOX is A buried oxide layer (BOX layer: Buried OXide), an n + well layer is formed immediately below the BOX in the case of PMOST, a p + well layer in the case of NMOST, and a deeper n well layer (n-well) is formed directly below the n + well layer. Integrated on the substrate. Features of this MOST is as shown in FIG. 9 (c), the type and concentration of the well under the BOX layer of gate material, it is to be controlled V _T The voltage applied to the well layer. In an actual MOST, the channel length (Lg) is 100 nm or less, the thickness of the SOI layer in which the MOST is formed is 20 nm or less, the thickness of the BOX layer is 10 nm or less, and the concentration of the well layer below it is 10 ¹⁶ cm ^−. It is about ³ to 10 ¹⁸ cm ⁻³ . As described above, by a thin BOX layer, the σ of the variations in V _T of MOST, 20 percent of the conventional bulk structure below is reduced (FIG. 9 (b)). Since random variation is reached to the V _T variation intrinsic to determine the offset of the sense amplifier becomes negligibly small as 1/10 or less. The double gate MOST structure can be regarded as a single MOST in which an upper MOST and a lower MOST are connected in parallel. Here, in the lower MOST, the well is the gate and the BOX layer is the gate insulating film. Therefore, as shown in the example of the NMOST in FIG. 9C, the threshold voltage V _{T of the} entire double gate MOST can be greatly changed by changing the lower well voltage. This is because the well layer is insulated from others, so that the well voltage can be greatly changed without generating a pn junction leakage current.

M. Yamaoka et al., "Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology," Symp. VLSI Circuits Dig., Pp.288-291, June 2004

R. Tsuchiya et al., "Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control," IEDM Dig. Tech. Papers, pp. 631-634 , Dec. 2004

On the other hand, in the DRAM, after the data pair line is precharged to V _DD / 2 in a floating state, the minute signal voltage of the memory cell read to the data line by driving the word line is set to the level of V _DD / 2. And discriminate with a differential amplifier (sense amplifier). This sensing method is also called mid-point sensing, and it is well known that it does not generate noise in the memory cell array and is suitable for low power consumption because it has a small data line charging current. ing. However, since the sense amplifier operates based on a low voltage of V _DD / 2, it is inherently difficult to operate at high speed. Therefore, if a circuit / device system capable of high-speed amplification under such conditions is found, V _DD can be lowered accordingly.

  Among the inventions described in this specification, typical ones are as follows.

  A plurality of word lines for driving the memory cells, a plurality of data pairs orthogonal to the word lines and for exchanging information with the memory cells, one MOS transistor and one connected to the intersection of the word lines and the data lines A voltage coupled to the data line by precharging the data line is coupled to the data line by driving the word line. The voltage is approximately equal to or smaller than the voltage, and the two combined voltages have opposite polarities.

  More preferably, the voltage coupled to the data line by precharging the data line is coupled toward the minimum value of the voltage that the data line can take, and is coupled to the data line by driving the word line. The voltage to be coupled is to be coupled toward the maximum value side of the voltage that can be taken by the data line.

  From another point of view, it is connected to a plurality of word lines that drive the memory cells, a plurality of data pairs that are orthogonal to the word lines and exchange information with the memory cells, and intersections of the word lines and the data lines. A plurality of memory cells each composed of one MOS transistor and one capacitor and a MOS transistor for precharging the data line, and the voltage coupled to the data line by precharging the data line is It is coupled to the maximum value side of the voltage that can be taken.

  More preferably, the precharge voltage of the data line is set to be approximately halfway between the maximum value and the minimum value of the voltage that can be taken by the data line.

  From another point of view, a circuit including a fully-depleted SOI structure MOS transistor having a double gate having a first gate and a well layer existing below the buried oxide film as a second gate, It includes a memory cell composed of a MOS transistor and a capacitor having a structure.

  More preferably, the capacitor uses the first gate of the MOS transistor having the structure as the first electrode and the drain or source of the MOS transistor as the second electrode.

  According to the present invention, it is possible to reduce the voltage, increase the speed and reduce the size of the CMOS DRAM.

  The present invention provides a peripheral circuit such as a memory cell, a memory cell array, or a sense amplifier for a high-speed DRAM suitable for a low-voltage DRAM of 1 V or less, utilizing the FD-SOI MOST structure or its characteristics. .

That is, if the above-described FD-SOIMOST characteristics are used, a low-voltage DRAM having excellent stable operation can be realized. FD-SOI MOST, as described above, the variation of _{V T} is small, hence the smaller the ignorable offset voltage of the sense amplifier. For example, since 3 sigma (standard deviation) can be reduced to 5 mV or less, noise is effectively reduced by that amount, and variation in amplification speed is also reduced. Therefore, SOIMOST is a suitable device for DRAM.

  Hereinafter, a DRAM using SOIMOST will be described in detail according to an embodiment.

FIG. 1 is a cross-sectional view of a DRAM using SOIMOST according to an embodiment of the present invention. With such a structure, the leakage current is negligibly small because no extra impurity is diffused in the charge storage node of the memory cell, and therefore the data retention characteristics such as a sufficiently long refresh time are improved. since the collection area within even cell alpha and cosmic rays are incident is extremely small soft error is negligible, or its sensitivity offset voltage becomes smaller in the sense amplifier because the variation of V _T is significantly reduced improves. Furthermore, it is necessary to boost the word voltage to write high voltage from the data line in the DRAM (V _DD) to the full cell node than V _{DD +} V _T, the variation of the boosted voltage V _T less min Since it can be made as small as possible and there is no substrate effect, a low voltage design of the word circuit becomes possible. There is also an advantage that a highly integrated memory cell and sense amplifier can be configured using almost the same structure as the peripheral logic circuit. The memory cell (MC) is composed of an NMOST for switching and an NMOS capacitor for storing information charges (planar structure in the figure). In the memory cell, the gate of the NMOST is connected to the word line (WL _{0 in} FIG. 1), the source or drain is connected to the data line DL, and the drain or source is connected to the capacitor electrode. Data line DL formed of metal wire from the contact within the cell, as shown in FIG. 2, it is wired orthogonally top of the word lines WL ₀ to the word line WL _0. The capacitor shares with the MOST an SOI layer, a BOX, and a p-type well layer (p +) to which a DC voltage (for example, 0.5 V) is applied, and they are on the top of a common n-well (n-Well). Is formed. As is well known, half of the maximum voltage V _DD of the data line, that is, V _DD / 2, is applied to the electrode PL. This is because the voltage between the electrodes of the capacitor is minimized with respect to both the binary information storage voltage V _DD and 0 V, and the capacitor insulating film can be made thinner with respect to a certain stress voltage, and the capacitance value can be increased accordingly. . Here, even when V _DD is written in the cell, in order to form a large capacitance between the source of the MOST in the cell and the electrode PL, V _DD / 2 is applied to the electrode PL of the capacitor. It is necessary to deepen a MOS structure capacitor into a depletion layer. Since _{V T} of the normal switch MOST of enhancement type, after all, the MOS capacitor gate (electrode PL) material must be a material different work function with the MOST. Usually, the electrode PL material has a work function smaller than that of the word line material, for example, ErSi _x if the word line material is NiSi, or NiSi if the word line material is PtSi. Here, in order to ensure the refresh time of the memory cell, the subthreshold current must be suppressed. Therefore, a constant value V _T is in the said MOST, for example, must be chosen above 0.7 V, if not choose a much larger the V _T, as is well known, the non-selection time of the word line voltage it can be increased effectively V _T to the negative. For example, as will be described later, if V _T0 = 0.2V, the word voltage may be selected to be −0.5V (described later) when not selected, and 1.2V when V _DD is 0.5V when selected. Further, in this embodiment, for the purpose of miniaturization, the p-well (p +) of the sense amplifier and the p-well (p +) of the array are formed of the same layer, and the NMOST in the sense amplifier and the switch NMOST in the cell are It is separated by shallow trench isolation (STI), and NMOST and PMOST in the sense amplifier or the peripheral circuit are separated by other trench isolation (STI).

FIG. 2 shows two types of cells laid out with a reference dimension F, and FIG. 3 shows data line circuits corresponding to them. Even if the SOIMOST is not used, the cell layout is low noise and highly integrated. However, the SOI structure has the above-described significant advantages, and therefore the description will be made on the assumption that the cross section is the SOI structure. In addition, the cell cross section shown by FIG. 1 is an AA 'cross section of these cells. As shown in FIG. 3A, the cell (a) is a cell (hereinafter abbreviated as 1-T cell) connected to one of two intersections of a word line WL and a data pair line (DL and / DL). 1-bit information is handled in one cell. Consider the case where a cell connected to the DL is read out. If the storage voltage _{V DD,} the _{V DD} and the data line precharge voltage _{V DD} / 2 of the difference and the cell node capacitance _{C S} and the data line capacitance _C signal voltage determined by the magnitude of _{D v S}
v _S = (V _DD / 2) · C _S / (C _S + C _D )
Is superimposed on the floating voltage V _DD / 2 of the precharged data line (DL) and output. Its polarity is positive with respect to V _DD / 2. If the accumulated voltage is 0V, the signal is negative in the same manner. 1-T in cell, remains one of the data lines (/ DL) voltage V _{DD / 2,} based on the V _{DD / 2,} the positive polarity or negative polarity of the signal of the sense amplifier (figure SA ). The sense amplifier shown in FIG. 4 has a configuration in which cross-coupled NMOS amplifiers (M ₁ and M ₂ ) and PMOS amplifiers (M ₃ and M ₄ ) are vertically stacked. Since the PMOS amplifier is operated after amplification, it is necessary to amplify as fast as possible with the NMOS amplifier in order to increase the speed. On the other hand, as shown in FIG. 3B, the 2-T cell is a cell connected to each of two intersections (hereinafter abbreviated as 2-T cell), and one of the two cells has V _DD , on the other hand the handle 0V, or 0V to one vice versa, one bit of information by reading and other accumulated V _DD to. Therefore, although the combination differs depending on the accumulated information, a positive / negative signal is always output to each data pair line, and this combination is discriminated by the sense amplifier (SA). In FIG. 2, when compared with 1 bit, both cell areas are the same cell area (37.5 F ² ). Therefore, the capacitance value C _S of the capacitor in one cell is smaller 2-T cells. For example, if the capacitor oxide film thickness of 2.2nm in 65 nanometer process technology, the use of the high dielectric film having a relative dielectric constant 6-7 such as silicon oxynitride film (SiON), C _S is 1-T A cell can achieve 2.0 fF and a 2-T cell can achieve 0.75 fF. The 2-T cells, since the positive and negative cell signal is read out by the differential, the effective _{C S} is twice the 1.5fF of 0.75FF. Still 1-T cell C _S is larger amount corresponding signal voltage is large, also, only a large amount area of C _S, C _S has the advantage of not easily influenced by the processing variations. On the other hand, the 2-T cell has an advantage that there are few noises. For example, when the layout of FIG. 2B and the operation method of FIG. 3B are combined, an array configuration that is not easily affected by adjacent data lines can be obtained. That is, as shown in the figure, if signals are read out to every other data pair line, for example, DL ₀ and / DL ₀ and DL ₂ and / DL ₂ , and the sense amplifiers SA ₀ and SA ₂ are selectively operated, Since the paired wires are shielded by the paired wires that are not operated, it is difficult to receive noise from other data lines. On the other hand, in the 1-T cell, after signals are read out to all the data pair lines, they are amplified by operating all the sense amplifiers at the same time. Susceptible to voltage changes. This type of noise can be canceled out by crossing pairs, but the area increases. In addition 1-T cell, when operating the sense amplifier in a state of driving the word line, an amount corresponding data line pair of the cell capacitance C _S is electrically unbalanced. This unbalance acts as noise during amplification in the sense amplifier. On the other hand, in the 2-T cell, since _CS is added to each of the paired lines, the data paired lines are always balanced and no noise is generated.

Since the voltage coupled from the other conductor to the data pair line also affects the cell operation and the operation of the sense amplifier, the 1-T cell and the 2-T cell will be compared from this viewpoint. Here, _{V T} (i.e. _{V TM)} memory cells MOST, _V T _{(V TP)} of the precharge MOST, and _V T _{(V TS)} to 0.2V respective sense amplifier MOST amplification start time, 0.1 V , 0.1V. As described above, the _VTM of the cell MOST needs to be increased to about 0.7 V in order to suppress the subthreshold current of the MOST flowing in the data line when not selected and to ensure a sufficient cell refresh time. In this embodiment, from the viewpoint of easy selection of the electrode material of the capacitor and the word line, the actual _{VTM is set} to 0.2 V, and it is effective with the help of the negative word voltage −0.5 V when not selected. _{VTM is set} to the required 0.7V. _{V TP} of the precharge MOST may to the same extent as _{V T} of the peripheral logic circuit. Here, at the time of precharging, since it is necessary to precharge them to V _DD / 2 after the data pair lines become V _DD and 0 V, the amplitude of the precharge signal must be V _DD + V _TP or more. . It is desired that the _VTS of the sense amplifier is low. This is because the effective gate voltage of the sense amplifier MOST at the start of amplification is made as high as possible. However, this value has a lower limit. This is because if this _VT is too low, the MOST is turned on instantaneously and the signal disappears even if an attempt is made to amplify the read signal. At about 10ns even sense time is long, since it is sufficient hold signal by that much time, and can actually even smaller, V _TS can be in the order of -0.05 V.

Let's examine the coupling voltage to the data pair under these conditions. As described above, since the coupling noise from the adjacent data line can be reduced, it is ignored here. The timing at which the voltages are combined before the signal voltage is sensed is when the precharge ends and when the word line is driven. In the example shown in FIG. 4, the memory cell MC connected to the data line DL is read. When the precharge signal amplitude V _P precharge circuit PC, which is an NMOS is driven low will be turned off from the high level, capacitor C _P between the driving lines and the data _lines, precharge and more specifically Due to the total gate capacitance of the three MOSTs constituting the circuit, a negative voltage Δ (C _P ) is equally coupled to the data pair. Since the gate capacitance is formed only during the period when the precharge signal drops from _VP to approximately V _DD / 2 + V _TP , this coupling voltage is
Δ (C _P ) = (V _P− V _DD / 2−V _TP ) · C _P / (C _P + C _D )
It becomes. When the word line is driven, a voltage is coupled to each data line due to the capacitance between the word line and the data line, and this is superimposed on the signal voltage. In the 1-T cell, the signal voltage is always read only to the data line DL to which the cell is connected, and is not read to the other data line. Also the line capacitance C _WD towards the cell are connected whereas a large gate capacitance via the MOST, a small cross-wiring capacitance as it is negligible capacitance C _'WD between the lines that are not connected. Thus, the data line DL, but the positive direction of the voltage corresponding to the substantially C _WD Δ (C _WD) are attached, do not bind to the other data line / DL. Since the gate capacitance is formed only during the period when the word voltage drops from V _W to approximately V _DD / 2 + V _TM ,
Δ (C _WD ) = (V _W −V _DD / 2−V _TM ) C _WD / (C _WD + C _S + C _D )
It becomes. The coupling voltage is similarly determined for the 2-T cell. However, in the 2-T cell, although the positive / negative combination differs depending on the stored information of the cell, the positive / negative signal is always read to the data pair line. The above Δ (C _WD ) is also coupled equally to the data pair.

FIG. 5 compares the voltage of each data pair line immediately before the sense amplifier operation, the differential voltage (voltage difference between the pair lines), and the gate voltage of the MOST to be turned on in the sense amplifier. Apparently, in the 1-T cell, the effective signal voltage taking the coupling voltage into consideration is smaller by Δ (C _WD ) in the negative polarity signal (“L” reading in the figure), and on the contrary, the positive polarity signal ( In the figure, “H” reading) increases by Δ (C _WD ). On the other hand, in the 2-T cell, it is always equal to the sum of signals of constant positive and negative polarity. Further, the gate voltage of the MOST to be turned on by the sense amplifier is smaller in the 1-T cell by the sum of Δ (C _WD ) and the signal voltage (v _S1 ) in the “L” reading than in the “H” reading. Become. Therefore, the high speed operation of the sense amplifier is determined by 'L' reading. On the other hand, in the 2-T cell, the sum of Δ (C _WD ) and the signal voltage (v _S2 ) is larger than that in the case of the above “L” reading. That is, the sense amplifier operates at a higher speed in the 2-T cell. Regardless of whether it is a 1-T cell or a 2-T cell, in order to sense a cell signal at high speed, the higher the gate voltage of the MOST to be turned on first, the better. For this purpose, it is to make Δ (C _P ) as small as possible or Δ (C _WD ) −Δ (C _P ) as large as possible from FIG. 5 when the signal voltage and V _DD are constant. . Therefore, the coupling voltage at the time of precharging must be made as small as possible than that at the time of driving the word line, or the coupling voltage at the time of precharging must be made as small as possible. For this purpose, for example, the size of the MOST in the precharge circuit may be reduced, or the voltage amplitude of the precharge signal may be reduced. This is also apparent from the data pair voltage waveform before activation of the sense amplifier in FIG. Figure by the coupling voltage at the word line driving constant, the waveform in which the channel width W _P per one of the three MOST constituting a precharge circuit parameters, apparently, 'L' read ' H 'to read both the reference voltage during the precharge As you decrease the W _P rises. Alternatively, if the precharge circuit is configured with PMOS more actively and the precharge signal is raised from low level to high level during precharge, the effective voltage on the gate increases further because the data line coupling voltage becomes positive. Sense speed can be increased.

In the 1-T cell using the bulk CMOS, unlike the FD-SOI, the leak current and the soft error in the cell become a problem. However, these are the cases where the “H” side, that is, the V _DD is stored. Reduce the stored voltage. Therefore, when “H” is read out to the data line DL, the difference voltage with respect to the voltage (reference voltage) of the data line / DL, that is, the signal voltage becomes small. Since the signal voltage becomes relatively large on the 'L' side, that is, when 0V is stored, the coupling voltage Δ (C _WD ) −Δ (C _P ) may be lowered by the amount of decrease. In other words, Δ (C _P ) should be increased conversely. Regardless of the FD-SOI or bulk CMOS, in the 2-T cell, the coupling voltage is set to V _DD / 2 (250 mV in consideration of the magnitude of the signal voltage of positive and negative polarity and the magnitude of the gate voltage of the sense amplifier MOST. ) May be set so that positive and negative polarity signals are read out symmetrically. For this purpose, the gate size of the precharge MOST is desirably about W _P = 50-100 nm, which is about half the gate area of the memory cell MOST.

Figure 7 connects the gate and the well, such as MOST intersecting bonds in the sense amplifier (terminal BN of FIG. 1), examples of changing the V _T of the MOST dynamically, to operate the sense amplifier at high speed It is. Whether it is a 1-T cell or a 2-T cell, even a completely new enhanced depletion type sense amplifier that operates dynamically can be realized. This is apparent from the example of NMOST, V _DD = 1V in FIG. 9C, for example. At the end of precharge, the gate voltage and well voltage of M ₁ and M ₂ are both V _{DD / 2 (} 0.5 V), so their V _T is 0.05 V (point A). When the negative signal v _S is read out to the data line DL ₀ and starts to be amplified, the sense amplifier activation signal ACT is turned on, and M ₁ in the NMOS amplifier is first turned on, and the gate voltage of M ₂ Begins to fall. At this time, since v _S is small, M ₂ is also turned on slightly to try to lower the gate voltage of M ₁ , but since there is a voltage difference of v _S , it does not drop as much as the gate voltage of M ₂ . In this process, the V _T of M ₂ increases, and this works in a direction that does not lower the gate voltage of M ₁ further. In other words, the difference in V _T between both MOSTs increases with time, and the difference between both gate voltages becomes larger, that is, the amplification is accelerated. As a result, the gate (DL ₀ ) of M ₂ continues to be discharged. Subsequently, when the PMOS amplifier is turned on by the activation signal / ACT, a voltage difference has already occurred in the data pair line, so that V _T of PMOSTM ₄ is smaller than that of M ₃ . Accordingly, the data line / DL is more charged by _{M 4.} Thus, _{V T} of NMOSTM ₁ is reduced, thereby further accelerating the discharge of the data line. In the final stage of amplification, the data line DL is discharged to 0V and / DL is charged to V _DD . The _{V T} of the MOST in the on state becomes smaller and smaller, because the increasingly large _{V T} of the MOST off, amplified by the feedback effect is completed at high speed. After amplification completion, if the ON state NMOST _(M 1, M ₄₎ be _{V T} becomes small (point B in FIG. 9 (c)), the off-state MOS
Since _{V T} of _(M 2, _{M 3)} is sufficiently large (C point in FIG. 9 (c)), 2 pieces of inverters, i.e., composed of inverter composed and _{M 2} and _{M 4} in _{M 1} and _{M 3} the inverters, one does not flow very large V _T Since known subthreshold current. For example, in the example of _V DD = 1V at NMOST thickness of 10nm in BOX Figure 9 (c), NMOST the 1V in the inverter is input, since the well voltage becomes 1V, its _{V T} negative Since the well voltage is 0V, the NMOS _T to which 0V is input is 0V, so that the VT becomes positive 0.1V or more. The same applies to PMOST. When the NMOST in the inverter is in the enhanced state, the other PMOS is in the depletion state. That sense amplifier of this embodiment, a high current driving capability of depletion type MOST, the higher enhancement type MOST V _T, a high-speed amplification becomes possible with a small sub-threshold current. The MOST structure, the sensitivity of _{V T} against the well voltage is high is desired. For this purpose, the thickness of the BOX layer is reduced. If V _DD is lower, for example even in the case of 0.5V or less, the lower limit of the degree to which tunneling current thickness of the BOX layer, for example oxide film is not an issue, for example, if the order of 2 nm, the sensitivity of V _T against gate voltage The depletion type MOST can be realized. FIG. 8 shows operation waveforms obtained for each of the 1-T cell and the 2-T cell. For each, the case where the gate and the well are not connected and the case where they are connected are obtained. Here, data line capacitance C _D = 8 fF, cell node capacitance C _S = 2 fF (1-T), 0.75 fF (2-T), data corresponding to the case where 32 cells are connected per data line Line voltage V _DD = 0.5 V, precharge MOST gate size W _P = 50 nm, cell transistor size W / L = 97 nm / 65 nm, word line and precharge signal rise time tr and fall time tf are 0, respectively. .1 ns is assumed. In the configuration in which the gate and the well are not connected, the substrate voltage V _BN of NMOST is 0 V and the substrate voltage V _{BP of} PMOST is 0.5 V. It is clear that the gate and the well operate at high speed.

It is the figure which showed the cross-sectional structure of the memory cell and peripheral circuit transistor of this invention. It is the figure which showed the layout example of the 1-T and 2-TDRAM cell using FD SOIMOST. FIG. 3 is a configuration diagram of an array and a sense amplifier using the memory cell of FIG. 2. It is the figure which showed the data line and sense amplifier circuit structure using 1-T and 2-T cell. 5 is a comparison table showing the voltage of each data pair line immediately before the sense amplifier operation, the differential voltage (voltage difference between the pair lines) and the gate voltage of the MOST to be turned on in the sense amplifier. It is an example of a wave form diagram of read-out operation before sensing operation of 1-T and 2-T cells. FIG. 3 is a diagram illustrating a circuit configuration of a gate / well connection sense amplifier. It is the figure which showed the cycle operation | movement using the gate well connection sense amplifier and non-connection sense amplifier of 1-T and 2-T cell. It is the figure which showed the cross-sectional structure of SOIMOST, the threshold value dispersion | variation of bulk MOST, and SOIMOST, and the well potential dependence of the threshold voltage.

Explanation of symbols

Threshold voltage of _{V T ··· MOST, / ACT,} ACT ··· amplifier activation signal, _{DL 0,} / _DL 0 ... etc. data lines, Si regions on SOI ... buried oxide film, BOX · · - the buried oxide _film, WL _0, WL _1, ... etc. word line, STI ... isolation region, p-Sub ... p-type semiconductor substrate, n-Well ... n-type substrate region, p + - ..P-type well region, n + ... n-type well region, CT ... contact, diffusion, diffusion layer region, PL ... plate electrode, F ... minimum processing dimension, SA, SA ₀ , SA ₁ ... sense amplifier, MC ... memory _{cells, C WD, C 'WD} ··· word lines data lines coupling _{capacitance, V DD} ... power supply _{voltage, C} S ... cell node _{capacitance, C} D ... Data line capacity, PC: Precharge times , _C P · · · precharge signal data line coupling _{capacitance, W} P · · · precharge circuit gate _sizes, V BN ··· NMOST well _potential, V BP ··· PMOST well potential.

Claims (23)

A plurality of word lines for driving the memory cells; a plurality of data pair lines orthogonal to the word lines for transferring information to and from the memory cells; and a MOS connected to the intersection of the word lines and the data lines It consists of a plurality of memory cells consisting of a transistor and a capacitor, and a MOS transistor that precharges the data line. By precharging the data line, the voltage coupled to the data line is driven by driving the word line. A semiconductor memory device, characterized in that it is approximately equal to or smaller than a voltage coupled to a data line, and the two coupled voltages have opposite polarities. The voltage coupled to the data line by precharging the data line is coupled toward the minimum value of the voltage that the data line can take, and the voltage coupled to the data line by driving the word line is 2. The semiconductor device according to claim 1, wherein the semiconductor device is coupled toward a maximum value of a voltage that can be taken by the data line. A plurality of word lines for driving the memory cells; a plurality of data pair lines orthogonal to the word lines for transferring information to and from the memory cells; and a MOS connected to the intersection of the word lines and the data lines A plurality of memory cells including a transistor and one capacitor, and a MOS transistor for precharging the data line, the voltage coupled to the data line by precharging the data line is a voltage that can be taken by the data line. A semiconductor device that is coupled to the maximum value side. 4. The semiconductor device according to claim 1, wherein the precharge voltage of the data line is set to be approximately halfway between the maximum value and the minimum value of the voltage that can be taken by the data line. 5. The semiconductor device according to claim 1, wherein the memory cell is connected to two intersections of the word line and the pair of data lines. 6. The semiconductor device according to claim 5, wherein the data pair lines are composed of every other data line, and every other data pair line is selectively operated. 7. The semiconductor device according to claim 1, wherein a sense amplifier composed of a cross-coupled MOS transistor is connected to the pair of data lines. 8. The semiconductor device according to claim 1, wherein a maximum voltage of the data line is 1V or less. A circuit including a MOS transistor having a fully-depleted SOI structure having a double gate having a first gate and a well layer existing under a buried oxide film as a second gate, and a memory comprising the MOS transistor having the structure and a capacitor A semiconductor device including a cell. 10. The semiconductor device according to claim 9, wherein the capacitor includes a first gate of the MOS transistor having the structure as a first electrode and a drain or source of the MOS transistor as a second electrode. 11. The semiconductor according to claim 10, wherein the MOS transistor, the SOI layer and the second gate of the capacitor in each memory cell in the memory cell array constituted by the memory cell group are common to each other. apparatus. 12. The semiconductor device according to claim 11, formed on a common well. 12. The semiconductor device according to claim 11, wherein a DC voltage is applied to the second gate. 11. The semiconductor device according to claim 10, wherein the first gate electrode of the MOS transistor and the first gate electrode of the capacitor are formed of different materials. 12. The semiconductor device according to claim 11, wherein the first gate electrode of the capacitor is formed of a common electrode layer in the array. The semiconductor device according to claim 9, wherein the capacitor has a substantially planar structure. The first gate of the MOS transistor is connected to a word line, the drain or source of the MOS transistor is connected to a data line, and the source or drain of the MOS transistor is connected to the electrode of the capacitor. Semiconductor device. 18. The semiconductor device according to claim 17, wherein a DC voltage substantially half the maximum voltage of the data line is applied to the other electrode of the capacitor. 15. The semiconductor device according to claim 14, wherein a work function of the MOS transistor is higher than a work function of the capacitor. 18. The semiconductor device according to claim 17, wherein the transistor in the memory cell is an N-type MOS, and a negative voltage is applied to the gate when the transistor is not selected. 10. The semiconductor device according to claim 9, wherein the well of the sense amplifier and the well of the array composed of cross-coupled MOS transistors are common. 10. The semiconductor device according to claim 9, wherein the circuit includes a sense amplifier composed of cross-coupled MOS transistors, and the gate and well of the transistor are connected. 23. The semiconductor device according to claim 22, wherein the MOS transistor dynamically changes between a depletion mode and an enhancement mode.

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