JPS63140489A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To ensure the voltages of a pair of bit lines against fluctuating at the end of equalization and to perform a more precise equalizing action by employing a 1st conductive channel type transistor which an equalization signal turns on and a 2nd conductive channel type transistor which the inversion signal of the equalization signal turns on and simultaneously equalizing the bit lines. CONSTITUTION:At the time of equalization, the equalization signal is applied to the gate of an n-channel type transistor 6, and simultaneously the inversion signal of the equalize signal is applied to the gate of a p-channel type transistor 7. As a result the two transistors 6 and 7 short-circuit the space between the bit lines 1 and 2. The equalize signal is inverted to turn off the two transistors 6 and 7, thereby terminating that equalization. At that time, the two equalization signals are coupled with a pair of bit lines 1 and 2 to offset the move of a voltage, and the equalization ends while the voltage level during the equalization can be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device having means for equalizing bit line pairs.

[Prior Art] FIG. 3 is a diagram showing part of a sensing circuit of a conventional dynamic memory.

In the figure, a sense amplifier 3 is connected to a bit line pair 1.2 connected to a plurality of memory cells, which amplifies a minute potential difference that appears between the bit line pair 1.2 when reading data. In the figure, 1 connected to bit line 1
Only one memory cell 4 is shown. The memory cell 4 is composed of a capacitor and a transfer gate, and a word line 5 is connected to the transfer gate. Also,
An equalizing transistor 6 is connected to the bit line pair 1 and 2 to short-circuit the bit lines 1 and 2 to equalize the potential.

In this semiconductor memory device, the equalizing transistor 6 is turned on and the bit lines 1 and 2 are turned on before reading data.
Bit lines 1.2 are equalized in advance by short-circuiting between them. Next, when the word line 5 connected to the transfer gate of the memory cell 4 becomes high level, the transfer gate becomes conductive and the charge (information) accumulated in the capacitor of the memory cell is transmitted to the bit line 1.

At this time, the sense amplifier 3 amplifies the minute potential difference that appears between the bit line pair 1.2, thereby determining whether the stored information is "1" or "0".

As explained above, since data is determined based on a minute potential difference between bit lines, the operation of equalizing the bit line pair before reading has a very important meaning.

[Problems to be Solved by the Invention] However, in the conventional semiconductor memory device configured as described above, only n-channel transistors are used to short-circuit the bit lines, so that the input signal to the gate is When the transistor is turned off by going from a high level to a low level, the level of the bit line also decreases due to coupling due to capacitance between the gate and source and between the gate and drain of the transistor. This is especially true in the recently common (1/2) Vcc bit line pre-precharge method in which the bit line is precharged to a voltage that is 1/2 of the power supply voltage VCC. This results in precharging at a level lower than the C level, leading to problems such as a lack of read margin.

This invention was made to solve the above-mentioned problems, and provides a semiconductor memory device in which the equalization level can be set to a desired value without being coupled by an equalizing transistor when bit line equalization is completed. The purpose is to obtain.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a first conductive channel type transistor that is turned on when an equalization signal φ is applied to its gate, as a transistor that shorts between bit lines; A second conductive channel type transistor that is turned on when an equalize signal φ, which is an inverted signal of the equalize signal φ, is applied to the gate thereof is used, and both of these transistors simultaneously equalize the bit lines.

[Function] In the semiconductor memory device according to the present invention, when the signal applied to the gate of one transistor changes from a high level to a low level at the end of equalization, the voltage of the bit line pair tends to decrease due to coupling, but at the same time, Since the signal applied to the gate of the other transistor changes from low level to high level, the voltage on the bit line pair tends to rise due to coupling. Therefore, the voltage movements of the bit line pair due to both transistors are canceled out, and the voltage of the bit line does not change.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of the main parts of a semiconductor memory device according to the present invention. Bit line pair 1 connected to multiple memory cells
, 2 are connected to a sense amplifier 3, similar to the conventional semiconductor memory device shown in FIG. Also in FIG. 1, only one memory cell 4 connected to the bit line 1 is shown, and the word line 5 is connected to the transfer gate of this memory cell.

This semiconductor memory device uses an n-channel transistor 6 and a p-channel transistor 7 as equalizing transistors that short-circuit between bit lines 1 and 2, and the source and drain of each transistor 6 and 7 are connected to the bit lines, respectively. Connected to lines 1 and 2.

Next, the equalizing operation of bit line pair 1.degree.2 in this semiconductor memory device will be explained. During equalization before reading data, an equalize signal φ that changes from a low level to a high level is applied to the gate of the n-channel transistor 6 as shown in FIG. As shown in FIG. 2(b), by applying an equalize signal 7 that changes from a high level to a low level, the n-channel type transistor 6 and the p-channel type transistor 7 are turned on, and the bit lines 1 and 2 are connected between the bit lines 1 and 2. short-circuited by two transistors 6.7.

This equalization is carried out by lowering the high-level equalization signal φ applied to the gate of the n-channel transistor 6 and high level the low-level equalization signal φ applied to the gate of the p-channel transistor 7. The process ends by turning off the two transistors 6.7. At this time, the n-channel transistor 6
The voltage of the bit line pair 1, 2 tends to decrease due to the coupling between the equalize signal φ applied to the gate of the p-channel transistor 7 and the bit line pair 1, 2.
The bit line pair 1.2 is coupled to the equalization signal 7 applied to the gate of the bit line pair 1.2. Since the other voltages tend to rise, the movements of these voltages cancel each other out, and equalization ends at the same voltage level as during the equalization period.

Therefore, the next operation, data reading, can be performed with sufficient margin.

In the above embodiment, one n-channel transistor 6 and one p-channel transistor 7 are used to short-circuit between the bit lines 1.2, but it is also possible to use a plurality of these transistors 6.7. In this case as well, the same effect as in the above embodiment can be obtained by configuring the bit line pair 1 and 2 so that the decrease and increase in voltage of the bit line pair 1 and 2 due to the n-channel transistor 6 and the p-channel transistor 7 cancel each other out. It will be done.

Further, in the above embodiment, an equalization signal is applied directly to the gates of the n-channel transistor 6 and the p-channel transistor 7, but it is possible to connect several transistors to these transistors 6 and 7 to control this transistor. via n-channel transistor 6 and p
An equalization signal may be applied to the channel type transistor 7.

[Effects of the Invention] As described above, according to the present invention, since both the first conductive channel type transistor and the second conductive channel type transistor are used as transistors for bit line equalization, the coupling due to the end of equalization is reduced. The decrease and increase in the voltage of the bit line pair are canceled out, so that the voltage of the bit line pair does not fluctuate, and a more reliable equalization operation can be performed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device according to the present invention, FIGS. 2(a) and (b) are waveform diagrams of equalization signals applied to equalization transistors, and FIG. 3 is a conventional semiconductor memory device. FIG. 3 is a circuit diagram of the device. In the figure, 1.2 is a bit line, 4 is a memory cell, 6 is an n-channel transistor, and 7 is a p-channel transistor. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a plurality of memory cells, a bit line pair that inputs and outputs information to and from the memory cells, a first conductive channel type transistor that shorts the bit line pair in response to a first equalization signal; A semiconductor memory device comprising a second conductive channel type transistor that simultaneously shorts a bit line pair in response to a second equalize signal complementary to the first equalize signal.