JPH0449194B2 - - Google Patents

Description

Claim 1 (a) At least one pair of bit lines 30, 38
and (b) at least one dynamic memory for each bit line, each storing a first voltage state corresponding to a first data state or a second voltage state corresponding to a second data state. cells 22, 32; and (c) one of these storage cells is connected to a corresponding bit line in response to a supplied storage address, with both said bit lines floating to a third voltage state. and sets the bit line connected to the memory cell to a fourth voltage state if the first voltage state is stored in the memory cell connected to the bit line. (d) connecting means 24, 34 for driving a fifth voltage state if the second voltage state is stored in the memory cell connected to the memory cell; (d) receiving a latch signal; a sense amplifier 4 connected directly to each bit line of the pair and driving the bit line with the lower charge to a lower voltage state;
4, and (e) a pull-up circuit 6 for each bit line of the pair.
0,68, each (a) a control connection connected to receive the first precharge signal P and a controlled path connected between the supply voltage V _cc and the precharge connection 122; (b) a control connection connected to receive a second precharge signal P _p and a bit line 30, 38 associated with said precharge connection 122 and each pull-up circuit; a second transistor 1 having a controlled circuit connected between
24; (c) a control connection connected to the precharge connection 122; and a third precharge signal.
It has a controlled path connected between a connection connected to receive P ₁ and a control connection of a fourth transistor 128, described below. (d) the supply voltage V _cc and the bit lines 30,3;
the fourth transistor 128 having a controlled path connected between the first precharge signal P and the first precharge signal P for a predetermined period of time, the fourth transistor 128 having a controlled path connected between the first precharge signal P and the first precharge signal P, After the circuit has been precharged, a second precharge signal P _p is activated when each bit line 30, 38 is at a voltage state greater than one transistor threshold below the third voltage state.
the third precharge signal is applied to the second transistor 124 at a voltage level that does not cause the transistor 124 to conduct.
P ₁ is applied to the third transistor 128 at a voltage level that pulls the connected bit line of the pair to a high voltage state after the other bit line has been driven to a low voltage state. (f) after driving the bit line previously connected to the memory cell to the low voltage state or to the high voltage state, the memory cell is (g) determining the voltage state of at least the bit line previously connected to the storage cell before connecting both bit lines together; (h) after driving one of the bit lines of the pair to the low voltage state and driving the other bit line to the high voltage state, transmitting the bit lines of the pair to the high voltage state; The bit lines are connected together such that the third voltage state is between the first voltage state and the second voltage state and the third voltage state is between the fourth voltage state and the fifth voltage state.
connecting means 50, 52 for balancing the voltages of both bit lines at the third voltage state when the bit lines are in the third voltage state. Device. 2. A separating means 50, 52 for separating the bit lines from each other after driving one of the bit lines to a low voltage state and driving the other bit line to a high voltage state. 2. The dynamic constant-speed access storage device according to claim 1. 3. A first transistor having a drain terminal and a source terminal is connected between one of the bit lines of the pair and the latch connection 46 of the sense amplifier, and 50 and the latch connection of the other of the bit lines of the pair, the second transistor 52 having a drain terminal and a source terminal.
and a gate terminal of each transistor is configured to receive a balancing signal that turns each transistor into a conductive state and balances the voltage of both bit lines with the third voltage by charge transfer of these bit lines. A dynamic constant-speed access storage device according to claim 1, which is connected thereto. 4 each storage cell, a drain terminal connected to one of the bit lines, a gate terminal connected to the row line, and a storage capacitor 26, 36 having a second terminal connected to a common connection. Claim 1 constituted by an access transistor 24, 34 having a source terminal connected to the first terminal.
Dynamic uniform access storage device as described in Section 1. TECHNICAL FIELD The present invention relates to semiconductor integrated circuits, and more particularly to constant-speed access memory devices that utilize dynamic memory cells. BACKGROUND ART The operation of conventional dynamic constant access memory circuits is described in US Pat. No. 3,588,844 and US Pat. No. 3699537 and U.S. Patent No. 3699537 and Proebsting et al.
It is described in the specifications of No. 3902082 and No. 396706. As shown in the Wallström and Pravesteing patent, sense amplifiers are commonly used to sense the differential voltage on each bit line connecting each storage cell. The connection of a storage cell to a bit line changes the previously developed voltage on this bit line to produce the desired data state as a differential voltage on each bit line. However, the voltage change on the bit line caused by the connection of the memory cell to the bit line is extremely small, and detection of such a small voltage change poses a serious problem in the structure of a dynamic constant-speed access memory device. Another problem is that electrical noise is picked up by the bit line and this electrical noise can overshadow the desired voltage offset produced by the storage cell. In addition, manufacturing tolerances in integrated circuits can result in unbalanced bit lines that interfere with reading the memory cells. In response to these problems, conventional memory devices have associated dummy cells with each bit line. The dummy cells are precharged to a given voltage state and connected to the unselected bit line in each pair of bit lines during each storage cycle. However, providing a large number of dummy cells with their cooperating circuits increases the size of the integrated circuit and requires more circuits. Because of the problems described above, this method operates without the need for dummy cells for each bit line, while at the same time providing a reliable identification of the voltage state stored in each storage cell. There is a need for quick access storage. DISCLOSURE OF THE INVENTION The present invention provides a method for operating a dynamic constant access storage system with the following steps. A high voltage state corresponding to a first data state or a low voltage state corresponding to a second data state is stored in the dynamic storage cell. The storage cell is then connected to one of the bit lines after setting the bit lines to an intermediate voltage state. When a memory cell storing a low voltage is connected to a bit line, the voltage on this bit line is reduced. When a memory cell storing a high voltage is connected to a bit line, the voltage on the bit line increases. When the voltage state of one bit line is changed by connecting a storage cell to that bit line, the other bit line of the pair is held substantially at the set intermediate voltage state. drooping After connecting a storage cell to one of the bit lines, the bit line with the lowest voltage is driven to a low voltage state and the other bit line is driven to a high voltage state. After driving the corresponding bit line to a low voltage state or a high voltage state, the storage cell
The connection is disconnected from the corresponding bit line. After disconnecting the storage cell from its corresponding bit line, each bit line is connected to the other to an intermediate voltage state in preparation for a new cycle.

[Brief explanation of the drawing]

For a more detailed explanation of the invention and its advantages, reference will now be made to the accompanying drawings. FIG. 1 is a circuit diagram of a dynamic constant speed access memory device according to the present invention;
The figure is a timing diagram of various signals occurring in the dynamic constant speed access memory device illustrated in FIG. 1, and FIG. 3 is a circuit diagram of the sense amplifier illustrated in FIG. 1.
Figure 4 shows the pull-up shown in Figure 1.
It is a circuit diagram of a circuit.

[Detailed description of the invention]

A dynamic constant access storage system according to the present invention is illustrated in FIG. The storage device 10 has an address line 12.
The memory address is sent through the group of . address line 12
are provided in each of a plurality of row decoders such as row decoder 14. Each address line 12 is connected to a plurality of respective column decoders, such as decoders 16 and 17. The address bits for the selected row line are provided in parallel over each line 12 one at a time during the store cycle. Also, the address bits for the selected column are provided later on each line 12 during the store cycle. This is illustrated by the address waveforms A _p -A _o shown in FIG. The row address bit selects a row decoder, such as decoder 14, and activates row line 18. Row line 18 is connected to a dynamic storage cell 22 that includes an access transistor 24 and a storage capacitor 26 . The gate terminal of access transistor 24 is connected to row line 18 and the source terminal of access transistor 24 is connected to the first of storage capacitors 26.
is connected to the terminal. The remaining terminals of storage capacitor 26 are connected to a ground node 28. The drain terminal of access transistor 24 is connected to bit line 30. Row line 20 is charged by row decoder 21 and connected to dynamic storage cell 32 . Dynamic storage cell 32 includes an access transistor 34 and a storage capacitor 36.
The gate terminal of access transistor 34 is connected to line 2.
0 and its source terminal is connected to the first terminal of storage capacitor 36. The remaining terminals of storage capacitor 36 are connected to ground connection 28. The drain terminal of access transistor 34 is connected to bit line 38. When driving row line 18 to a high voltage state, the corresponding access transistor 24 is activated and a conductive path is formed between bit line 30 and storage capacitor 26. The voltage on the row line selected by the row decoder is illustrated by timing signal 40 shown in FIG. sense amplifier 44
is activated in response to a latch signal transmitted via latch connection 46. The latch signal L is
This is illustrated as waveform 48 in FIG. Memory device 10 includes a balanced circuit having transistors 50 and 52. The source terminal, drain terminal, and drain terminal of the transistor 50 are
The source terminal of transistor 52 is connected between bit line 38 and latch connection 46, and the source terminal of transistor 52 is connected between bit line 38 and latch connection 46. The gate terminal of each transistor 50, 52 is connected to a connection 54 that receives a balanced signal E. Balanced signal E is illustrated as waveform 56 in FIG. When balanced signal E is set to a high voltage state, each transistor 50, 52 is turned on, connecting each bit line 30, 38 to connection 46.
Connect to. Pull-up circuit 60 is connected to bit line 30 via line 62. The pull-up circuit 60 is
It operates in response to precharge signals P, P _p and P ₁ illustrated as waveforms 63, 64 and 66 in FIG. 2, respectively. A similar pull-up circuit 68 is connected to bit line 38 via line 70. Each pull-up circuit 60, 68 detects when the voltage on its corresponding bit line is higher than a preset voltage level, and when receiving a precharge signal,
Pull the bit line up to the supply voltage as described below. Each bit line is provided with a column transistor that carries data states into and out of each storage cell. The source and drain terminals of column transistors 74 are connected to bit line 30 and input/output line 76.
connected between. A gate terminal of column transistor 74 is connected to column decoder 16 .
Similarly, the drain and source terminals of column transistor 80 are connected between bit line 38 and input/output line 82. The gate terminal of column transistor 80 is connected to column decoder 17 which, like column decoder 16, is responsive to the same column address signal. Each column decoder 16, 17 has an address line 12
In response to column address bits received via the memory cell, the selected column transistors are activated to transmit data states to and from the addressed storage cell. Input/output lines 76, 82 are connected to an input/output circuit 84 which serves to transmit data states written into and read from each storage cell. Data states are received from external circuitry via data input terminal 86 and transmitted to external circuitry via data output terminal 87. Next, the operation of the dynamic constant speed access storage device 10 according to the present invention will be described with reference to FIGS. 1, 2, 3, and 4. This circuit is assumed to operate with a 5.0V power supply. A store cycle is initiated by a row address strobe (RAS) signal 90.
The RAS signal 90 becomes active when transitioning from a high level to a low level. Row address bits are provided to row decoder 14 as shown by waveform 92a. The row address bits are received immediately after the RAS signal goes active. row decoder 14
sends a row enable signal 40 to the selected row line. When row enable signal 40 is at a level of 5V, access transistor 2 in storage cell 22
4 becomes conductive, connecting storage capacitor 26 to bit line 30. Bit lines 30, 38 are prebalanced to a voltage level of approximately 2.0V, as shown by waveform 96. storage capacitor 26
was previously charged to the stored level of 5.0V, then the bit line 30 will be connected to the storage capacitor 26.
For charge sharing between bit line 30 and bit line 30, it is driven to approximately 2.3V as shown by waveform 96a in FIG. However, if storage capacitor 26 had previously been discharged to ground potential, bit line 30 would have waveform 96.
As shown by b, it becomes about 1.8V. After connecting storage cell 22 to bit line 30, latch signal L, shown as waveform 48, is at ground potential. Sense amplifier 44 responds to the latch signal by bringing one of the lower voltage bit lines connected thereto to ground potential. If capacitor 26 has been previously discharged, the voltage on bit line 30 will be as shown by waveform 96b when this voltage is brought to ground potential. However, if storage capacitor 26 is charged to the stored high voltage level as shown by waveform 96a, bit line 30 is unaffected by the operation of sense amplifier 44. However, if bit line 30 were to rise to the voltage shown by waveform 96a, bit line 30 would exceed the voltage on bit line 38, shown as waveform 98, and bit line 38 would be at ground potential, as shown by waveform 98a. However, if the voltage on bit line 30 is pulled down by storage capacitor 26, the balanced voltage on bit line 38 is not affected by sense amplifier 44. This condition is illustrated by waveform 98b. After sense amplifier 44 pulls one of the bit lines to ground potential and precharges pull-up circuits 60 and 68 with precharge signal P, precharge signals P ₀ and P ₁ are received to activate pull-up circuits 60 and 68. . Each pull-up circuit 60, 68 detects which one of the bit lines has a voltage higher than a preset voltage. One of the bit lines will be at ground potential and the other bit line will be at a balanced voltage or at an increased voltage of 2.3V caused by connecting to a storage capacitor storing a high voltage of 5V. Bit lines with high voltages are pulled up to the supply voltage.
For a bit line receiving a high charge from a storage cell, this condition is illustrated by waveform 96a. The bit line at balanced voltage is shown by waveform 98b. At this time, the storage capacitor connected to the bit line has returned to its original voltage. When one of the bit lines is driven to the supply voltage and the other bit line is brought to ground potential, column transistor 7
4,80 are turned on, and each bit line 30,3
8 are connected to input/output lines 76 and 82, respectively. The voltage state of each bit line is transmitted to input/output circuit 84 via each input/output line. The input/output circuit 84 includes a sense amplifier to detect the differential voltage between the input/output lines 76 and 82. A sense amplifier in the input/output circuit measures the voltage state stored in the storage cell and transmits this voltage state via data output line 87. After bringing one of the bit lines to ground potential and the other bit line to the supply voltage, the data state in the storage cell is again stored. Row line 18 then returns to ground potential, separating the charge on the storage capacitor. These bit lines are then left floating. A balanced signal 56 is then applied to the gate terminal of each transistor 50, 52, causing each transistor 50, 52 to conduct and connecting bit line 30 to bit line 38 via latch connection 46. This connection shares charge to each bit line and balances the bit lines to a voltage approximately halfway between the supply voltage and ground potential. This is shown in both waveforms 96 and 98. In this case, each waveform 96, 98 is 2V
Return to the equilibrium voltage of . A typical circuit for sense amplifier 44 shown in FIG. 1 is illustrated in FIG. The source and drain terminals of pass transistor 104 are connected between bit line 30 and connection 106. The source and drain terminals of second pass transistor 108 are connected between bit line 38 and connection 110. Both transistors 1
The gate terminal of 04,108 is connected to a high voltage source, such as the supply voltage _Vcc . Each transistor 104, 108 is always conductive and acts as a resistor. The drain terminal of transistor 112 is connected to connection 106 , the source terminal is connected to connection 46 , and the gate terminal is connected to connection 106 . Sense amplifier operation occurs after the storage cell is connected to one of the bit lines, line 30 or line 38. One of the bit lines will then be at a higher voltage than the other bit line. For example, assume that bit line 30 is at the higher voltage. When the latch signal gradually brings the connection 46 to ground potential, the bias from the gate to the source of the transistor 114 is greater than the bias from the gate to the source of the transistor 112, so the transistor 114 is lower than the transistor 112. It is turned on before. When transistor 114 conducts, connection 110 is discharged through transistor 114 to latch connection 46. When connection 110 is discharged, the gate bias of transistor 112 is reduced to prevent transistor 112 from becoming conductive. When the latch signal is pulled down to ground potential, transistor 11
4 continues the conductive state. This is because bit line 30 and connection 106 remain in their previous high charge state. When connection 110 is discharged, transistor 108 becomes conductive, thereby discharging bit line 38. That is, after the latch signal goes completely to ground potential, the bit line 38 also goes to ground potential. After connecting the memory cell to one of the bit lines 38
When is at the higher voltage, transistor 112 becomes conductive, discharging connection 106 and bringing bit line 30 to ground potential. A circuit diagram of pull-up circuits 60 and 68 is illustrated in FIG. The drain terminal of transistor 120 is connected to the _Vcc power supply, and the source terminal is connected to connection 1
22, and its gate terminal is connected to receive a precharge signal P. Transistor 124 has a drain terminal connected to connection 122, a source terminal connected to bit line 30, and a gate terminal connected to receive precharge signal P _p . Transistor 126 has a drain terminal connected to receive precharge signal P ₁ , a gate terminal connected to connection 122 , and a source terminal connected to the gate terminal of transistor 128 . The drain terminal of transistor 128 is _Vcc
It is connected to a power supply, and its source terminal is connected to a bit line 30. When receiving precharge signal P, transistor 120 becomes conductive and precharges connection 122 to a high voltage state. When the precharge signal returns to a low voltage level, connection 122 remains floating at a high voltage state. When precharge signal P _p reaches approximately 2V, transistor 124 becomes conductive if bit line 30 is in a sufficiently low voltage state, and at least one transistor threshold voltage is established between the gate and source terminals of transistor 124. exists. transistor 124
When conductive, connection 122 is discharged to bit line 30. However, if the charge on bit line 30 is high enough to cause a voltage difference between the gate and source terminals of transistor 124,
If the transistor threshold voltage is above, transistor 124 will not become conductive due to precharge signal P _p , leaving connection 122 floating at a high voltage level. The P ₁ signal is then applied to the drain terminal of transistor 126. When connection 122 is at a high voltage, transistor 126 conducts and the source of transistor 126 follows signal P ₁ above V _cc . This bootstraps connection 122 to a high voltage level due to the channel capacitance of transistor 126. The total voltage level of the bootstrapped precharge signal P ₁ applied to the gate terminal of transistor 128 reduces the total supply voltage.
_Vcc is applied to bit line 30, thereby placing the bit line at the voltage state of _Vcc . That is, when the voltage on bit line 30 is above a preset level, the bit line is connected to precharge circuit 60.
The supply voltage increases due to the operation of bit line 3.
If the zero voltage is less than the preset level, the precharge circuit 60 will have no effect on the bit line 30. The reason why dummy cells are used in the prior art is to balance the capacitance on the bit line before the sensing operation. The present invention is based on bit lines 30, 38.
This makes it possible to perform accurate sensing operations without relying on balancing the above capacitance. In the present invention, the bit lines are connected directly to the sense amplifier, rather than being connected through means for balancing capacitance as in the prior art. Storage cell 32 does not directly replace the dummy cell; its function is simply to hold the equalization voltage set during a storage read operation [see waveform 98 in FIG. 2]. Therefore, the memory cell 22
There is no problem even if there is no strict symmetry between and 32. This is because according to the invention, balancing of bit line capacitances is not required. Even if transistor 32 is not strictly symmetrical with transistor 22, there is no problem in implementing the present invention since transistor 32 functions to maintain a balanced voltage. The reason for connecting the bit line directly to the input node of the sense amplifier during sensing operation is as follows. By connecting the bit lines 30, 38 directly to the sense amplifier 34, the bit line having the lower of the two voltages after a sensing operation is pulled to ground potential when the sense amplifier is latched. becomes certain. Meanwhile, a pull-up circuit pulls the bit line having the higher of the two voltages to the supply voltage. This increases the potential difference to be detected and makes detection easier. The reason for balancing the bit line voltages outside the memory cycle is as follows. An important technical effect of this balancing is that the bit line 30,3
8 to provide a reference voltage. memory cell 2
2, the voltage on the bit line associated with this memory cell will rise or fall depending on the state stored in the memory cell. As described above, the sense amplifier pulls down the voltage on the higher voltage bit line and the pull-up circuit pulls up the voltage on the lower voltage bit line. After this sensing operation, both voltages are balanced and ready for a new cycle. ie equilibrate before starting a new cycle. In fact, in FIG. 2, the equilibrium signal E is high outside the memory read cycle, and
As explained above, balancing occurs before the RAS signal is set. In short, the present invention provides a method for connecting each bit line to approximately half the supply voltage, 2V, before connecting the storage cells to each bit line.
It is in a dynamic constant-speed access memory that is balanced to . The sense amplifier senses the bit line voltage difference created by connecting a storage capacitor to one of the bit lines and brings the bit line with the lower voltage to ground potential. The pull-up circuit pulls the higher voltage bit line to a higher voltage. After transferring the voltage state through the input and output lines and after separating the memory cells, each bit line is left floating and connected to each other via a latch connection, and the bit lines are The balanced voltage is restored by charge transfer. To explain more specifically the effects of the pull-up circuits, each pull-up circuit 60, 68 detects the voltage on the bit line connected to it and outputs the following two signals.
Performs one of the actions of the species. That is, when the voltage on a connected bit line is higher than a predetermined level, the voltage on that bit line is raised to the supply voltage _Vcc . On the other hand, when the voltage on the connected bit line is lower than a predetermined level, it has no effect on the voltage on that bit line. The pull-up circuit is
In addition to providing a sufficient potential difference between the bit lines to be sensed by the sense amplifiers in the input/output circuits, the appropriate bit lines must be set to write the maximum voltage to the storage capacitor at the end of the read cycle.
It has the important effect of raising the voltage to V _cc . The effect of this pull-up circuit is obtained by the transistor shown in FIG. A first precharge signal P is supplied to transistor 120, which turns on. The precharge connection section 122 becomes in a high voltage state. The first precharge signal is then removed and the precharge connection 12
2 becomes a floating state. A second precharge signal P _p is then provided to transistor 124 and, if bit line 30 is in a low voltage state, transistor 124
conducts and precharge connection 122 discharges to the bit line, so the pull-up circuit does not act on the voltage on the bit line. However, if bit line 30 is in a high voltage state, transistor 124 will be in the second
It does not become conductive even with the precharge signal. A third precharge signal P ₁ is then provided to transistor 126 . Precharge connection part 1
22 is floating, the third precharge signal P ₁ can bootstrap the precharge connection 122 such that the entire voltage level of the third precharge signal P ₁ is
26 to the gate terminal of transistor 128. Therefore, the total supply voltage V _cc is equal to bit line 30
is applied to the bit line, pulling the voltage on the bit line to _Vcc . This pull-up circuit requires only enough charge to substantially charge the bit line to a high voltage state. In other words, in this pull-up circuit
There is no direct current path between _Vcc and ground at any time. This pull-up circuit functions to directly turn off the bit line. There is no need to detect the potential difference between both bit lines in order to determine which of the bit lines should be pulled up to _Vcc . This allows the pull-up circuit to be located at the end of the bit line rather than between the bit lines where the sense amplifier is located. By locating the pull-up circuit at the end of the bit line, the effect of shortening the memory access time can be obtained. This eliminates the need for input/output circuits connected at the end of the bit line, i.e. near the pull-up circuit, to have the pull-up voltage propagated down the bit line (the bit line has a relatively high capacitance). (Because of this, there is a considerable delay before a voltage pulse applied to one end reaches the other end.) In other words, the entire bit line potential difference is applied to the input/output circuit, and therefore, when the pull-up circuit is enabled, the input/output circuit can be enabled immediately thereafter, making it possible to increase the speed. Although one embodiment of the present invention has been illustrated in the accompanying drawings and described in detail, the present invention is not limited to the above-described embodiment, and it goes without saying that various changes and modifications can be made without departing from the scope of the present invention. It is.