JPS54100233A - Integrated memory - Google Patents

Integrated memory

Info

Publication number
JPS54100233A
JPS54100233A JP693978A JP693978A JPS54100233A JP S54100233 A JPS54100233 A JP S54100233A JP 693978 A JP693978 A JP 693978A JP 693978 A JP693978 A JP 693978A JP S54100233 A JPS54100233 A JP S54100233A
Authority
JP
Japan
Prior art keywords
time
high level
signal
level
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP693978A
Other languages
Japanese (ja)
Other versions
JPS6242356B2 (en
Inventor
Tadahide Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP693978A priority Critical patent/JPS54100233A/en
Publication of JPS54100233A publication Critical patent/JPS54100233A/en
Publication of JPS6242356B2 publication Critical patent/JPS6242356B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators

Abstract

PURPOSE:To obtain an integrated memory which needs no intermediate voltage generator circuit by installing the transistor connected to a pair of digit lines divided into two and the dummy cell comprising two units of the transistor and the storage capacity. CONSTITUTION:When clock signal phi31 is changed from low to high level at time t31, a short circuit is given between digit line 33 and 34. And the potential of the both digit lines divided into the high and low levels becomes the intermediate level. When signal phi32 is changed to the high level at time t32, the intermediate potential is stored at contact N33 and 34 of dummy cell 39 and 40. Signal phi31 and phi32 feature the low level at time t33. And in case address line 37 becomes the high level at time t34, dummy address 42 also features the high level. At the same time, the memory signal is read out to digit line 33 from memory cell 35, and the intermediate potential is read out to digit line 34 from the dummy cell. Signal phi33 is changed to the high level at time t35, and the sense amplifier is activateed to amplify the potential difference between N31 and 32. Then signal phi34 is turned to the high level at time t36, and the potential difference is amplified to the maximum level.
JP693978A 1978-01-24 1978-01-24 Integrated memory Granted JPS54100233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP693978A JPS54100233A (en) 1978-01-24 1978-01-24 Integrated memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP693978A JPS54100233A (en) 1978-01-24 1978-01-24 Integrated memory

Publications (2)

Publication Number Publication Date
JPS54100233A true JPS54100233A (en) 1979-08-07
JPS6242356B2 JPS6242356B2 (en) 1987-09-08

Family

ID=11652211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP693978A Granted JPS54100233A (en) 1978-01-24 1978-01-24 Integrated memory

Country Status (1)

Country Link
JP (1) JPS54100233A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0045399A2 (en) * 1980-07-31 1982-02-10 Siemens Aktiengesellschaft Monolithic integrated semiconductor memory
JPS57501001A (en) * 1980-06-02 1982-06-03
JPS59203298A (en) * 1983-05-04 1984-11-17 Nec Corp Semiconductor memory
US4503523A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Dynamic reference potential generating circuit arrangement
JPS61144793A (en) * 1984-12-18 1986-07-02 Nec Corp Method of driving semiconductor memory
JPS61145794A (en) * 1984-12-19 1986-07-03 Nec Corp Driving method of semiconductor memory

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57501001A (en) * 1980-06-02 1982-06-03
EP0045399A2 (en) * 1980-07-31 1982-02-10 Siemens Aktiengesellschaft Monolithic integrated semiconductor memory
US4393478A (en) * 1980-07-31 1983-07-12 Siemens Aktiengesellschaft Monolithically integrated semiconductor memory with dummy and charge equalization cells
US4503523A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Dynamic reference potential generating circuit arrangement
JPS59203298A (en) * 1983-05-04 1984-11-17 Nec Corp Semiconductor memory
JPH0480479B2 (en) * 1983-05-04 1992-12-18 Nippon Electric Co
JPS61144793A (en) * 1984-12-18 1986-07-02 Nec Corp Method of driving semiconductor memory
JPS61145794A (en) * 1984-12-19 1986-07-03 Nec Corp Driving method of semiconductor memory

Also Published As

Publication number Publication date
JPS6242356B2 (en) 1987-09-08

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