JPS5778695A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS5778695A
JPS5778695A JP55151935A JP15193580A JPS5778695A JP S5778695 A JPS5778695 A JP S5778695A JP 55151935 A JP55151935 A JP 55151935A JP 15193580 A JP15193580 A JP 15193580A JP S5778695 A JPS5778695 A JP S5778695A
Authority
JP
Japan
Prior art keywords
word line
memory cell
output signal
level
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55151935A
Other languages
Japanese (ja)
Other versions
JPS6131554B2 (en
Inventor
Hide Konishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55151935A priority Critical patent/JPS5778695A/en
Publication of JPS5778695A publication Critical patent/JPS5778695A/en
Publication of JPS6131554B2 publication Critical patent/JPS6131554B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To increase the readout and wirte-in speeds of a memory cell, by boosting the potential of a word line in advance within a smaller range than threshold voltage of a transfer transistor, when the word line is selected by a line decoder. CONSTITUTION:When a word line 1 is selected from plural word lines by a line decoder 4, an output signal phi1 of an H level is inputted to the gate of transistors (TR)T1, T2 from an address transient detector 5, and an output signal anti-phi2 of an L level is inputted to a TR T3. Accordingly, the TR T1 and the TR T2 are turned on, and the word line 1 is boosted to prescribed voltage within a smaller range than threshold voltage of a transfer transistor T4 by an electric power supply VDD. Subsequently, after the output signal phi1 has become an L level, the word line 1 is selected, also the TR T4 is turned on by terminal voltage phi3, and read-out and write of a memory cell 3 are executed through a bit line 2. In this way, the readout and write-in speeds of the memory cell 3 are increased.
JP55151935A 1980-10-29 1980-10-29 Semiconductor storage device Granted JPS5778695A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55151935A JPS5778695A (en) 1980-10-29 1980-10-29 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55151935A JPS5778695A (en) 1980-10-29 1980-10-29 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS5778695A true JPS5778695A (en) 1982-05-17
JPS6131554B2 JPS6131554B2 (en) 1986-07-21

Family

ID=15529411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55151935A Granted JPS5778695A (en) 1980-10-29 1980-10-29 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS5778695A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61260496A (en) * 1985-05-14 1986-11-18 エツセジ−エツセ　ミクロエレツトロニカソチエタ　ペル　アノニマ Precharging circuit for word line of memory system having particularly programmable memory cell
JPS61265792A (en) * 1985-05-20 1986-11-25 Fujitsu Ltd Semiconductor memory circuit
JPS62232795A (en) * 1986-04-02 1987-10-13 Mitsubishi Electric Corp Mos type memory circuit
JPH0589673A (en) * 1991-03-14 1993-04-09 Samsung Electron Co Ltd Driver circuit for word line in semiconductor memory device
JP2010152974A (en) * 2008-12-25 2010-07-08 Toshiba Corp Semiconductor memory device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61260496A (en) * 1985-05-14 1986-11-18 エツセジ−エツセ　ミクロエレツトロニカソチエタ　ペル　アノニマ Precharging circuit for word line of memory system having particularly programmable memory cell
JPS61265792A (en) * 1985-05-20 1986-11-25 Fujitsu Ltd Semiconductor memory circuit
JPS62232795A (en) * 1986-04-02 1987-10-13 Mitsubishi Electric Corp Mos type memory circuit
JPH0589673A (en) * 1991-03-14 1993-04-09 Samsung Electron Co Ltd Driver circuit for word line in semiconductor memory device
JP2010152974A (en) * 2008-12-25 2010-07-08 Toshiba Corp Semiconductor memory device

Also Published As

Publication number Publication date
JPS6131554B2 (en) 1986-07-21

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