JPS61265792A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To shorten a reading and writing by setting a corresponding word line to an intermediate level of a first and a second levels when a reading and a writing control signals are not inputted with an output signal of a decoder selected. CONSTITUTION:When a decoder is selected, a decoder output signal Xi is h level, both of a control signal phi or a writing control signal WE are L level, a P channel transistor 11 and an N channel transistor 18 are turned off, and the N transistor 12 is turned on to set a signal WLi of a word line to an intermediate level M of the L level and the H level by an intermediate level supply circuit 13. Thereby, the reading and or the writing time of the data can be shortened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor memory circuits, particularly so-called static R
This relates to AM (hereinafter referred to as SRAM).

[Conventional technology]

FIG. 6 is a circuit diagram for explaining the problems of a conventional semiconductor memory circuit, where l is a word line (WL), 2 is a memory cell, and 3 is a bit line negative R element consisting of a transistor TI and 72. It is. Furthermore, the memory cell 2 has a load resistance R
, and 12, read/write transistors T3 and T4
and driver transistors T5 and T6. 4 and 5 are bit lines.

Assume that a certain amount of information is currently stored in the cell, the driver transistor T5 is on, and the driver transistor T6 is off. Therefore, the bit line 4 is at a low level (hereinafter referred to as "L"), and the bit line 5 is at a high level! Suppose that the word line 1 is at the current level s (hereinafter referred to as "H"), the word line l is selected, and the read/write transistors T3 and T4 are turned on. Therefore, as shown by the arrow in the figure, from the power supply VCC to the transistor T I-T 3 1 T 5
A current 1 flows through the power supply VSS.

By the way, in the asynchronous fisRAM, this current 11 flows as long as a word line is selected, and since any word line is generally selected, this current always flows.

Further, this current II flows in all cells connected to the selected word line.

In particular, there was a trend to pay more attention to SRAMs made by Dayonghui, which caused problems in terms of power consumption.

Note that when the cell is not selected, the read/write transistor T
Even when T3 and T4 are off, the current I2 flows as shown, but the current flow! Since it is larger, it is important to reduce the current It to reduce power consumption.

In order to solve this problem, various methods have been proposed in the past, one of which is a method of keeping the word line specified by the address in the selected state only for the minimum period necessary for reading or adding -1. There is.

FIG. 7 is a timing diagram showing an example of this.

Add is an address signal, and WE is a write control signal.

WL is a word line selection signal, and DOυ is a read data signal. According to this method, in a read operation, a predetermined word line is selected by the address signal Add (W
L="H") Data is read from the cell to the bit line 4.5, but when the read data is latched by a latch circuit (not shown), this is detected and the word line is set to the unselected state 11 (WL=
Similarly, in the write operation, a predetermined word line is selected (WL=“H”) and data is written into the cell, but when the write is completed, the word line is unselected. l! B (WL="L").

In this way, according to the conventional method, the word line specified by the address is selected only during the period necessary for read or write operations (WL="H"), and the word line is left unselected @(Wt ="L"), the period during which current flows from the bit line into the cell can be shortened, and wasteful power consumption can be prevented. This was particularly effective for SRAMs with long cycle times.

[Problem that the invention seeks to solve]

As described above, it is true that the conventional method can significantly reduce power consumption.
Therefore, when the capacitive load on the word line is large, it takes time to bring the word line into a non-selected state, resulting in a problem that read and write times become longer.

The present invention was created in view of these points, and an object of the present invention is to provide a semiconductor memory circuit that can reduce power consumption and shorten read and write times.

[Means for solving problems]

As shown in FIG. 1, the configuration of the semiconductor memory circuit according to the present invention includes a logic circuit (OR circuit 6. circuits 7 and 10, a NAND circuit 8, an AND circuit 9, and an N-channel transistor 12), and a circuit (P-channel transistor 11. N-channel transistor 18. and an intermediate level supply circuit 13).

Note that 21 is a word driver (wn), which corresponds to that in FIG. 3, which will be described later.

[Effect]

According to the above logic circuit, when the decoder is not selected and the decoder output signal (XI) is at the "L" level, the P-channel transistor it and the N-channel transistor 12 are turned off, and the N-channel transistor 1B is turned on, so that the word line signal (WLi) is set to L'' level (first level).

The decoder is selected and the decoder output signal (XI) is “
H'' level and for a predetermined M period when the address changes.
The control signal (φ) or write control signal (
When WE) is at H level, N-channel transistors 12 and 18 are off, and P-channel transistor ti
is turned on and the word line signal (WLi) goes to 'H' level (
second level).

Further, when the decoder is selected and the decoder output signal (Xt) is at the "H" level, but both the control signal (φ) or the write control signal (WE) are at the "L" level, the P channel transistor 11 and the N channel The transistor 1B is turned off, the N-channel transistor 12 is turned on, and the intermediate level supply circuit 13 outputs the word line signal (WLi
) is set to middle 11 level (third level, M” level).

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

ft515! J is a block diagram of a word driver circuit of a semiconductor memory circuit using a CMO3 according to an embodiment of the present invention, and 6 is a diagram showing a control signal (φ) and a write control signal (WE) by 2.
The manually operated OR circuit 7 is an inverter circuit that inverts the output signal of the OR circuit 6.

Here, φ is “H” for a certain period of time from when the address changes.
This is a control signal that becomes a level (described in detail later with reference to FIGS. 4 and 5).

W E 4i This is a write control signal indicating a read when the level is ``L'' and a write when the level is ``H''.

Further, 8 is a NAND circuit which generates the output signal (xl) of the decoder and the output signal A of the OR circuit 6 by two people.

Reference numeral 9 is an AND circuit that inputs the output signal (Xt) of the decoder and the output signal B of the inverter circuit 7, and 10 is an inverter circuit that inverts the output signal (Xt) of the decoder.

11 is a P-channel transistor whose source is the VCC power supply, whose gate is the output of the NAND circuit 8, and whose drain is the word line (
12 is an N-channel transistor for transfer gate whose drain is connected to the word line (WLi).
WLi), whose gate is connected to the output of the AND circuit 9.

Reference numeral 13 denotes an intermediate level supply circuit, which includes three N-channel transistors 15 and 16 connected in series to the load N-channel transistor 14 and their gates and drains.
．． 17, the output of which is connected to the source of the N-channel transistor 12. Note that the number of transistors constituting the intermediate level supply circuit 13 and the size of each transistor are determined by taking into consideration the magnitude of the required intermediate level voltage (Vn) and the power consumed by the supply circuit itself.

18 is an N-channel transistor whose drain is connected to the word line (WLi), whose gate is connected to the output of the inverter circuit IO, and whose source is connected to the VSS power supply.

The word line (WLi) is connected to the gate of the read/write transistor in the cell shown in FIG.

Next, the operation of the circuit of this embodiment shown in FIG. 1 will be explained.

This will be explained with reference to the timing diagram shown in FIG.

The symbols in FIG. 2 correspond to those in FIG.

When the address corresponding to word M (WLi) has not been stored in the decoder (not shown) for a long time, the decoder output signal (xl) is at the "L'" level.

At this time, the output C of the NAND circuit 8 is at "H" level.

Since the output D of the AND circuit 9 is at the "L'I level" and the transistors 11 and 12 are off, while the transistor 18 is on, the word m (WLi) is at the "L" level. Therefore, the signal on this word line is N-channel transfer gates (T3 and T4 in the cell used as gate signals) are closed (see Figure 6), and no current flows into the cell via the bit line on the "L" level side. When A is set by the control signal (φ) and the write control signal (WE)
Even if the levels of point and point B change, the level states of point 0 and point D do not change.

On the other hand, when the address corresponding to 7-Fil (Wl, +) is sent to the decoder, first the decoder output signal (
X,) becomes H” level (in Figure 2, address A1
(assuming that the decoder output signal (xI) becomes "H" level), the transistor 18 is cut off. At this time, the control signal (φ) and the occupation control signal (WE) are still at the "L" level, so the A point is "L".
Level, point B has "H" level. Therefore, NAND circuit 8
The output C of is “H” level and the output of the AND circuit 9 is also “H”
The transistor 11 is turned off, the transistor 12 is turned on, and the level of the word line (WLi) becomes the "M" level output from the intermediate level supply circuit 13. For this reason, the transfer gate in the cell (Tgo in Figure 6).

The conductivity of T4) is higher than when the word line (WLi) is not selected, but lower than when it is selected, and the conductivity of T4) is higher than when the word line (WLi) is not selected, but lower than when it is selected. A minute current flows.

On the other hand, when a change from address A1.1 to address A is detected and the control signal (φ) goes to "H" level, output signal A of OR circuit 6 goes to "H" level and output signal B of inverter circuit 7 goes to "H" level. “L” level, therefore the output signal C of the NAND circuit 8 is “L” level, and the output signal C of the AND circuit 9 is “L” level.
Since the word line (WLi) becomes "L" level and transistor 11 is turned on and transistor 12 is turned off, the word line (WLi) becomes "H" level.
level. For this reason, the transfer gate (
T3 * Ts ) is completely conductive.

Data is read.

The data read in this way is controlled by the control signal (φ).
is latched by a latch circuit (not shown) while it is at 'H' level.At this time, the pulse width of the control signal (φ) is set to a width sufficient to latch the data.The control signal (
φ) becomes “L” level and the write control signal (WE) becomes “
If the signal A remains at the “L” level, the signal A becomes “L” level and reliable.
No. B becomes "H" level. On the other hand, since the decoder output signal (X+) is still at "H" level, the signal C
is at "H" level, and the signal is at "H" level. As a result, transistor 11 is turned off and transistor 12 is turned on, while transistor 18 remains off, so that the word line (WLi) becomes "M" level again.

This state corresponds to the write a1w signal (WE
) is held at the "H" level while the decoder is selected (the decoder output signal (xl) is at the "H" level).

In this state, when the primary write control signal (WE) is at “H” level, that is, the write mode is set, the control signal (φ) becomes “
As in the case of the high level, the transistor 18 remains off, the transistor 11 turns on, and the transistor 12 turns off, so the word line (WLi) goes to °'H''.
Level and transfer game in the cell) (T3
.

T4) is fully conductive and data is written.

Next, when the address changes from A to A1÷1, the word line (
WLi) returns to the "L" level, the signal C becomes the "H" level, the signal becomes the "L" level, and at this time the signal A becomes the "L" level.
Since the signal B is at the "H" level, the transistors 11 and 12 are off, and the signal E is at the "H" level, so the transistor 18 is on, and the word line (wLt) is at the "H" level.
It becomes L″ level.

As described above, in this embodiment, while the decoder output signal (xl) is at the "H" level, that is, while the decoder is outputting the selection output, the control signal (φ) or the write control signal (
When at least one of the control signals (WE) becomes "H" level, the word line (WLt) becomes "H" level, and the control signal (
If both φ) and write control signal (WE) are at “L” level, even if the decoder output signal (X+) is a selection output, word 1! (WLi) is not held at "H" level but at an intermediate level.

Therefore, the word line (WLi) becomes completely "H" level only during the period required for reading and writing.

The amount of current flowing from the bit line to the cell is reduced, and the lead
Rather than completely returning the word line (WLt) to the "L" level after writing, when the word line (WLi) is at the "H" level, the word line (WLi) is set to an intermediate level, so after reading, the same address is written. When this happens, the word line (WLi) can be quickly raised.

FIG. 3 shows a semiconductor memory circuit (four rows and four rows) according to an embodiment of the present invention.
19 is a column address decoder, 20 is a row address decoder, 21 is a word driver, 22 is a memory cell, 23 is a column address transition detection circuit, 24 is a delay circuit, and 25 is an R- It is a 5y lip flop.

Also, 26 is a latch circuit, and 27 is a sense amplifier.

28 is D0L11 Batsuhua? 29 is Dinba, Fa.

30 is a write buffer, and AO''A3 is an address signal.

FIG. 4 is a circuit diagram for explaining the operation of the column address transition detection circuit 23 shown in FIG. and an OR circuit 35.

The circuit operation of FIG. 4 will be explained with reference to the timing diagram of FIG. 5. Note: The symbols in the jSs diagram correspond to the symbols in FIG.

When the column address signal aO changes from the "L" level to the "H" level, the output signal Ao(d) of the delay circuit 31 also changes from the "L" level to the H level after a certain period of time. Ixflusive OR circuit 3
A pulse having a pulse width equal to the transition time shift of the input signal is output to the output PG of No. 3. Similarly, 1st column address signal a
When O changes from the "H" level to the "L" level, the exhaustive off circuit 33 generates a pulse.

On the other hand, a pulse is also generated from the output PI of the exhaustive OR circuit 33 when the level of the column address signal A1 changes. That is, column address signal AO or AI
When at least one of the large inputs changes, the OR circuit 35
A pulse is generated at the output φ0 of.

Next, this pulse is input to the set input of the RS flip flop 25, setting the clip flop, and also input to the delay circuit 24. Then, the pulse of the output signal φ1 of the delay circuit 24 output after a predetermined time is R-
Reset the flip-flop by inputting the reset manual input to the S flip-flop 7p25. As a result, the R-S flip-flop 25 outputs a pulse having a pulse width set by the delay time of the delay circuit 24.

As mentioned above, from the R-S flip-flop 25,
A pulse with a predetermined pulse width is output every time the level of the column address signal All or AI changes. This is the pulse of the W control signal φ.

Note that the φ0 pulse is a one-shot pulse that is generated without much delay in response to a change in the level of the column address, and the φ1 pulse is generated when the data read from the cell selected for the column address is A one-shot pulse generated around the time it reaches the output of the sense amplifier 27.
'J, data is taken into the latch circuit 26, and the φ pulse is a pulse that rises (low) when the column address level changes, and rises (low) after Dour is latched.

As shown in FIG. 3, the intermediate level supply circuit 13 described above (FIG. 1) can be commonly connected to a plurality of word drivers. Only one word driver is selected, so This is because even if they are commonly connected, their functions can be fully demonstrated.

In this manner, this configuration enables a high-speed semiconductor memory circuit with low power consumption without requiring a particularly large area.

〔Effect of the invention〕

As explained above, according to the semiconductor memory circuit according to the present invention, in a state where a word line is selected, after reading or writing is completed, the word line is brought to an intermediate level state unless the input address changes. Because it is something to keep
It is possible to shorten the rise time of the word line during reading or writing, and therefore it is possible to shorten the time for reading or writing data. Further, the current flowing from the bit line to the cell in the intermediate level state is very small, so it is possible to save power consumption as a whole.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a word driver circuit of a semiconductor memory circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment circuit of FIG. Further, FIG. 3 is an overall configuration diagram of a semiconductor circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram for explaining the operation of the column address transition detection circuit 23 shown in FIG. 3. FIG. 5 is a timing diagram for explaining the circuit operation of the fourth vlI. FIG. 6 shows the problems of a conventional semiconductor memory circuit.
FIG. 7 is a timing chart for explaining problems in another conventional semiconductor memory circuit. 6...OR circuit 7.10...Inverter circuit 8...NAND circuit 9...AND circuit 11...P channel transistors 1, 2, 18...N channel transistor 13.
...Intermediate level supply circuit Figure 1 Figure 2

Claims (1)

[Claims] When the output signal of the decoder is in the non-selected state, the corresponding word line is set to the first level of the non-selected state, and when the output signal of the decoder is in the selected state and the read control signal or write control When a signal is input, the corresponding word line is set to the second level of the selected state, and when the decoder output signal is in the selected state but no read control signal or write control signal is input, the corresponding word line is set to the second level of the selected state. 1. A semiconductor memory circuit comprising: a circuit for setting a word line to a third level that is an intermediate level between the first level and the second level.