JPS59201464A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the generation of hot electrons and enable high speed action by a method wherein the output potential of a substrate bias generating circuit is impressed on a semiconductor substrate, and this potential is impressed on a selected word line. CONSTITUTION:A well region of the second conductivity type is formed in the substrate of the first conductivity type. The source and drain regions 131 and 132 are formed in a region 12, and a gate electrode 15 is formed on the clearance between these regions. The region 131 is provided with an impurity region 16, and an electrode 18 for a capacitor is formed on this region 16 via insulation film 17. Further, a wiring layer 19 constituting a bit line is connected to the region 132. The substrate potential VBB is impressed on the substrate 11, and the potential VCC on the region 12. A memory selecting signal having the amplitude between the potential VCC and the potential VSS (earth) is supplied to the word line connected to the electrode 15, and a memory information signal having said amplitude to the bit line. Since this constitution is that of a C-MOS, hot electrons can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and is particularly applicable to a large-capacity dynamic memory configured with a high-density hybrid MO8 circuit.

[Technical background of the invention and its problems]

Semiconductor storage devices can be roughly divided into ROM (continued read only memory) and RAM (read/write memory). There are two types of RAM: static RAM, in which the memory cells are composed of 7 digits and 70 digits, and dynamic RAM, in which the memory cells are composed of one selection transistor and one memory cell.

The above-mentioned dynamic RAM occupies a small area per bit and can be inexpensively priced per bit, so it is widely used in computer storage devices and the like.

By the way, conventional dynamic RAMs are composed of N-channel type MOS transistors and MOS capacitors, which can be manufactured at low cost, but various problems have arisen as the degree of integration increases. First of all, there is a malfunction caused by hot electrons generated when a high electric field is applied to a microscopic MO3 type element being dragged into a dirt oxide film. This problem is particularly serious in N-channel type MOS transistors operating as pentode tubes.

Second, since it uses a dynamic sense method that reads signals from memory cells onto precharged bit lines, the memory cell selection transistor (MO8) does not operate as a pentode and the word line rises. This method has the disadvantage that the data readout time becomes longer due to a delay in the transmission time and a decrease in the channel conductivity of the transistor.

Thirdly, as the capacitance of the capacitor decreases with miniaturization, the storage signal capacity of the memory cell decreases.

Above 1. One way to solve the second problem is to use a CMO8 circuit for memory cells.
By using a MOS circuit, we can replace the N-channel type load MO8) transistor, which often operates with a pentode, with a P-channel type MOS transistor, thereby avoiding the problem of hot electrons and reducing the bit line glitch potential to the word line. By setting it equal to the standby potential of the selected word line, when the potential of the selected word line rises, the selection MO8) quickly turns on and transmits a signal by triode operation. For example, as shown in FIG. 1, each memory cell is a P-channel MOS transistor Q.
The bit line BL is connected to one end of the transistor Q1, and the word mWL is connected to the dart. Then, beep) the potential of the line BL is set to V. In addition to precharging to the C (5V) level, the potential of the word line WL during standby is reduced to the Vcc level, and only the selected word line is reduced to the V, . . . (OV) level, thereby reducing the speed increase.

However, with the above configuration, it is not possible to write a potential with an amplitude B of 5V from the V level to the ■cc level into the memory cell. This is because the potential stored in the capacitor is the selection MOS) transistor Q
This is because the threshold voltage Vth1 decreases by the same threshold voltage Vth1 as the third problem. It is more advantageous to do so. For this reason, the conventional N-channel type dynamic R
In AM, the word line potential is ``Voo + Vth''.
The bootstrapping method has been used above. However, in order to realize this, it is necessary to take into account the drop in threshold voltage of the word line selection MOS (Runnostar), so a node is boosted to more than "Vcc + 2 This is undesirable because a high field is applied to the MOS transistor.

[Purpose of the invention]

This generation ψJ was made in view of the above-mentioned circumstances, and its purpose is to prevent the generation of pot electrons, improve I/C'Sfr interlocking ability, and improve memory cell performance. It is an object of the present invention to provide a highly integrated half-dimensional memory device capable of preventing a decrease in storage signals.

[Summary of the invention]

That is, in the present invention, a memory cell for storing information is provided at each intersection of a plurality of word lines formed in a well region of conductivity type opposite to that of the semiconductor substrate and a plurality of bit lines crossing the word lines. arranged to form a memory cell array,
This memory cell array is driven by a first potential supply source supplying a first potential and a second potential supply source supplying a second potential. Furthermore, the above 1. A substrate bias generation circuit that generates a third potential based on the x-th and z-th potentials supplied from the second @ supply source is provided, and the output potential of this substrate bias generation circuit is applied to the semiconductor substrate, and this potential is is applied to the selected word line "T" to either write or read information into the selected memory cell.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be described with reference to drawings f:#. In FIG. 2, 1 is a semiconductor substrate of the first conductivity type (P type), and the inner button of this substrate 11 is of the second conductivity type (N type).
A well region 12 is formed. In the well region 12, P-type impurity regions 131 and 132, which will become the source and drain regions of the selection MO8l transistor, are formed separated by a predetermined distance. A dirt electrode I5 is formed through the impurity region zs1. A P-type impurity region 16 is coupled to the impurity region zs1, and a capacitor electrode 18 is formed on this region 16 through an insulating film 17. Further, an interconnection layer 19 constituting a bit line is connected to the impurity region 132.The equivalent circuit is the same as that in FIG.

A substrate potential V1111 (third potential) is applied to the semiconductor substrate 11, and a potential Vcc (second potential) is applied to the well region 12. In addition, the word Hwr has the second
Potential V. A memory cell selection signal having an amplitude between C and the third potential VB□ is supplied, and the bit line ELK is at the second potential Vc.
A storage information signal is supplied which corrects the amplitude between c and the potential vss (first potential). Each of the above potentials is "
vcc>v38>vHB”? -frfJ Section Kpy
,,.

Since FIG. 3 shows a substrate bias generation circuit (Teyano Bong circuit) that outputs the third potential V0, it is formed on the same semiconductor substrate as the memory cell array. This Chernor pump circuit consists of an oscillation circuit 21. A capacitor 22 to which the output of this oscillation circuit 21 is applied to one electrode is connected in series between an output terminal 23 and a ground point (first potential) vss, and the connection point is connected to the other electrode of the capacitor 22. MOS transistor Q2.

The dart of transistor Q2 is connected to the output terminal 23, and the dart of transistor Q3 is connected to the connection point between transistors Q2 and Q3. Then, it is configured to obtain the converted potential vflB from the output terminal 23.

FIG. 4 shows a word line drive circuit for driving the word lines by applying the third potential vBB to the address input signals A'l'1. A*□+yama r A”n is supplied to the NOR circuit 24i, and the output terminal of this NOR circuit 24I is connected to the gate of the transistor Q4 via the inverter circuit 251.

Here, A"l is the address signal AI or its complementary signal Ai
It means either one of the following. One end of the transistor Q4 is connected to a terminal 26 to which a word line potential setting signal φ is supplied during data reading, and the other end is connected to the NOR circuit 2.
It is connected to a terminal 27 to which a power supply potential (second potential) vcc is applied via a transistor Qs connected to the output terminal of the transistor 4i. One end of the word line WL+ is connected to the connection point of the transistors Q4 and Q5, and the word 9 line WL i
The other end is connected to the terminal of the transistor Q61Q7 connected in series between the terminal 28 to which the word line potential setting signal φWL during writing is applied and the terminal 29 to which the output potential vIIB of the charge pong circuit is applied. Ru. Furthermore, a transistor Q8 is connected between the dirt of the transistors Q61Q7 and the terminal 29, and this transistor Q8
Dart 8 is connected to the connection point between transistors Q6 and Q7.

The operation of the above configuration will be explained with reference to the timing chart of FIG. Address signal A11A21・
...+ An is II v, 1lsII level and Ilv,
When any of the c'l levels changes, the outputs of the other NOR circuits except the NOR circuit 241 in the selected row go from the precharge level "vccll" to the ""ss'" level. Therefore, the transistor Q4 in the selected row is on and Qll is off, and the transistor Q4 on the unselected row is off and Q6 is on. At this time, when the signal φ falls to l,,1 level, the potential of the selected word line WL+(7) becomes [vss+1VTp
IJ (VTp is the threshold voltage of the Pf Jarnell type MO8 transistor).

Therefore, when bit fe3ABL is precharged to 'v,olI level, the selection transistor of the memory cell is turned on when the word line potential drops to "VCC" TPIJ, and from then on, this selection transistor operates as a triode. Therefore, data can be read out at high speed and has high sensitivity.

Furthermore, in the case of "writing and rewriting", it is necessary to lower the word line potential to "ss I v7 p l J". This is to write the Vss level into the memory cell, and at this time, the signal φWL is changed from the "vss" level to the Vss level.
, raising cII levels. Word line WL1 is rV8
8+IVTPIJ, transistor Q6 is on and Q7 is off, so transistor Q s
+ The potential at the connection point A of Q7 increases. This potential is at terminal 28. The value (Voc-ΔV) is determined by resistance division by the through current at the connection point A and the terminal 29. Note that if the current capacity of the transistor Q7 is set to a small value, the through current will be small, and this through current will not cause any particular problem since it flows only in the selected row. Further, since the potential vB11 is applied to the substrate, the change in the potential vBR is large in capacitance and can be almost ignored. If the signal φWL is returned to the "■ss#" level after a predetermined time from the "vcc" level, the through current will disappear.In this case, the 1 connection point A does not return to the °vBB' level, but becomes "vs81 level," so that the word line 7
The potential VBnK is set without entering the 0-take state. However, "vs, -■,!8〉vBB" is completely ignored.

With this configuration, it is possible to write a signal with the amplitude of the power supply voltage (from the "vss" level to the "v0 level") into the memory cell without applying a bootstrap to the potential BB to obtain an even lower (or higher) potential. There are no nodes to which a high electric field is applied.In addition, the 0MO3 configuration greatly reduces the generation of hot electrons, making it possible not only to achieve high-speed reading but also to increase the amount of stored signals, resulting in reliable operation. .

In the above embodiment, an N-type well region is formed within a P-type semiconductor substrate, and a dynamic memory cell array is formed within the well region. However, it is also possible to form a P-type well region within an N-type semiconductor substrate. However, a well region internal pressure dynamic memory cell array may be formed. Further, the same effect can be obtained by forming a dynamic memory cell array in a semiconductor substrate and applying the output potential VllB of a charge pump circuit to a well region formed in the semiconductor substrate.

〔Effect of the invention〕

As described above, the present invention provides a highly integrated semiconductor memory device that can prevent the generation of hot electrons, is capable of high-speed operation, and is also capable of preventing a decrease in memory signals in memory cells. nru.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a memory cell of a semiconductor memory device according to a conventional example and an embodiment of the present invention, FIG. 2 is a cross-sectional configuration diagram of a memory cell in a semiconductor memory device according to an embodiment of the present invention, and FIG. 4 is a circuit diagram showing a word line drive circuit for driving a word line, and FIG.
The figure is a timing chart for explaining the operation of the circuit shown in FIG. 4.

Claims (3)

[Claims] (1) A memory that stores information and is arranged in a matrix at each intersection of a semiconductor substrate, a plurality of word lines formed in a well region of a conductivity type opposite to the semiconductor substrate, and a plurality of bit lines that intersect with the word lines. a cell array, a first potential supply source supplying a first potential and a second potential supply source supplying a second potential, which drive the memory cell array; a substrate bias generation circuit that generates a third potential based on the first and second potentials supplied from a second potential supply source and applies it to the semiconductor substrate; What is claimed is: 1. A semiconductor memory device comprising: means for applying voltage to a selected word line; and configured to perform one of writing and reading information to and from a selected memory cell. (2) The semiconductor memory device according to claim 1, wherein the semiconductor substrate is of P type, and the third potential is lower than the first potential. (3) The semiconductor memory device according to claim 1, wherein the m-th semi-bound substrate is of N type and p, and the third potential is higher than the second potential.