JPS6364359A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent leakage from an information signal holding means, and to ensure memory by using intermediate potential between supply voltage and a ground level as one end of the voltage amplitude of a reading-writing line. CONSTITUTION:An element isolation region 10 isolating a pair of memory cells is formed to a semiconductor storage device, and capacitances 11a, 11b are isolated by the region 10. The capacitances 11a, 11b are operated as information signal holding means, and each connected to switching transistors 12a, 12b. Source-drain regions on the side not connected to the capacitances 11a, 11b of the transistors 12a, 12b are connected to bit lines 13a, 13b. The bit lines 13a, 13b are changed at potential Vm slightly deformed to a power supply level from a ground level and the power supply level, and a charge injection level from the bit lines 13a, 13b is used as Vm.

Description

[Detailed Description of the Invention] A. Industrial Application Field The present invention is directed to DRA~4 (Guinaminoku RAM) which reads and writes information signals using information No. 13 and tQ.
etc. in semi-written form (g device: ■1).

B0 Summary of the Invention The present invention provides a memory comprising a means for holding information (δ), a switching transistor disposed between the information holding means and a write line (Jl). A first voltage potential at which carriers can be injected into a switching transistor in a semiconductor memory location where cells are arranged and the voltage amplitude of the read/write line is set to a first potential and a second potential y-. By setting the voltage to an intermediate potential that is shifted to the second voltage side, leakage from the l/r fift signal holding means is stopped and a real information signal is recorded.

C0 Conventional technology For example, DRA ~ 1st half! Then, as shown in FIG. 7 (al), the n-body memory device v, 1>
72, which is an information signal holding means, is transmitted through the summer region 71.
"+72b is formed, this volume) 1!72a, 721]
・Wide food line) Shaku (No. 3) so that it touches VT!
Next, switching transistors 73a and 73b are formed for turning on and off.The source and drain regions of one of the switching transistors 73a and 73b are used for reading and writing information signals. Bit line 7 which is the bit protruding write line =
la, connected to 74b\E Ll, this bit line 74
a, 74 bf +n to sense amplifier (not shown)
Vt is ζ, and due to the negative iγ1 vibration of this sense amplifier, the corresponding bit line 74a is set to a voltage amplitude of, for example, Ov, which is the ground voltage, and the voltage Vcc, which is 5V.

74b changes by U position.

D. Problems to be Solved by the Invention If the problem is to be solved by an N-channel switching transistor, it is as follows. 8 and 1, select the selected cell as shown in Figure 7 131:! M
Leakage from 72a to non-moscale cell + x7zb +3
In addition, there is leakage C through the switching transistor 73b from the bit line as shown in 7th Section 1(C), and the subthreshold of the field transistor and switching transistor 73b in the nested isolation region 71 is weak. Leakage B and C caused by operation in the (inverted) state pose problems in memory operation.

To deal with this, there are measures to increase the size of the element isolation region 71 and to increase the gate length of the switching transistors 72a and 72b, but this increases the cell size and tends to reduce the size of the elements. It would be contrary to.

In addition, as a countermeasure against the above-mentioned leakage, there are techniques such as forming a channel stopper region and increasing the threshold (direct voltage vth) of the switching transistor, but this increases the number of processes such as impurity absorption during seedling production. Therefore, even with Leak's 1qt control method and 7, it is impossible to say that it is perfect.

Therefore, the present invention solves the above-mentioned problems.
, Prevents leakage from No. 3 holding means and ensures reliable information! ”
Proposal of a semiconductor memory device that performs storage in item (iii) (means for solving the E9 problem with the same purpose) Item 3 holding means and its information
A switching transistor disposed between the read/write line and the read/write line is arranged, and the potential of the read/write line is set to a first potential and a second potential. In a semiconductor memory device in which writing is performed by changing between This problem is solved by a semiconductor memory device whose special feature is to have an intermediate potential that is shifted to .

Here, the first potential is a low level potential when the switching transistor of the memory cell is a %MO3) transistor;
When V and the ground rail are Ov, the potential is Ov. In addition, when the switching transistor of the memory cell is i) MOS transistor, it is at a high level potential.
When the ground level is QV, the potential is 5V.

Further, the second potential is a high-level potential when the switching transistor of the memory cell is an NMOS transistor, and for example, if the power supply voltage Vcc is 5V,
When the ground level is Ov, the potential is 5V.

In addition, the switching transistor of the memory cell is NMO
In the case of an S transistor, it is a low level potential; -For example, the power supply voltage Vcc is 5V, and the ground level is QV.
When it is, the potential is 0■.

The above-mentioned intermediate potential is a potential obtained by shifting the first potential to the second potential side, which is at least on the second potential side with respect to the potential potential when the switching transistor is turned off, and is at least on the second potential side with respect to the potential potential when the switching transistor is turned off. This is a potential on the second potential side of the electric potential.

Note that the information signal holder Y2 is something that electrically holds the information signal, and may be, for example, a cell capacitor. Also, a read/write line is a wiring that connects to a switching transistor and connects to other circuits for reading or writing σ'l, and its name such as a bit line or data line is unknown. Hey 41.

The voltage amplitude of the F0 action read/write line does not directly correspond to the power supply voltage and the ground level, but the read/write line of the present invention changes the voltage amplitude to an intermediate potential obtained by shifting the first potential to the second potential. It can be one end of the amplitude.

By setting this intermediate potential, it is possible to prevent carriers from flowing out to the cell capacitor, which is an information signal holding means, when the switching transistor is in the off state, for example, due to the relationship between the potentials. It is also possible to prevent carriers from flowing out into the cell capacity.

G. Example Preferred embodiments of the present invention will be described with reference to the drawings.

In the semiconductor memory device as an embodiment of the present invention, the first potential of the bit line, which is the read/write line, is set to an intermediate potential, so that leakage can be prevented and the reliability of its operation can be increased. It is something that can be done.

Below, we will mainly explain the potential relationship between W when the switching transistor is an NMOS transistor, but it is not limited to this, and when the switching transistor is a PMO3)
In the case of a transistor, the same explanation can be given by reversing the potential relationship.

First, the semiconductor memory device of this embodiment is a DRAM and has a potential relationship as shown in FIG. 1, for example. 1lffi (al is a cross-sectional view of the semiconductor memory device corresponding to FIG.
1a and llb are formed so as to be separated from each other by the above-mentioned element region 1.
Switching transistors 12a and 12b are formed so as to be parallel to the switching transistors 12a and 12b, respectively.
The source/drain regions on the side not connected to the bit lines 13a and 13b are connected to the bit lines 13a and 13b.

Semiconductor memory 4g in which such a pair of memory cells are arranged
A diagram showing the corresponding potential relationship of the device is shown in FIG. be able to.

That is, as shown in FIG. 1 (bl), in the semiconductor memory device of this embodiment, the voltage amplitude of the bit line is changed from the voltage tA voltage Vcc and the ground level (OV) to the bit line of the conventional semiconductor memory device. Rather than using the first potential, which is the potential that can be the carrier of the switching transistor,
The potential of is set as the intermediate potential Vm. In addition, Figure 1 (bl
shows the injection of charge from the bit line 13a into the capacitor 5tlIF1. Here, to explain in detail the intermediate potential Vm, the switching transistors 12a, 1
When 2b is an NMO3) transistor, the carriers are electrons, and the first potential for injecting the carriers is, for example, 0■. Then, the second potential is the power supply voltage Vcc
For example, when 5■, the intermediate potential Vm is O
The potential is higher than v by ΔV. This ΔV
The value of is a value whose absolute value is larger than the difference between at least the larger value of the potential potential of the switching transistor when it is off and the potential potential of the element AileH region, and OV. Then, by swinging (potential change) the bit lines 13a and 13b between this intermediate potential Vm and the second potential mentioned above in accordance with the information signal, the switching transistors indicate an off state. 12
From the relationship between b and the potential barrier of the element sub-region 11, a predetermined selected capacity! The required writing will be done only in *t I 1 a. Furthermore, the intermediate potential Vm is determined by a sense amplifier circuit (see Figs.
(see Fig. 5).

Here, to explain the change in potential with reference to FIG. 1, the switching transistor 12a is connected to the word line t:ir.
Since iR1 is in the on state, the via line 13a and the gas are connected, as shown in Fig. 1(b).
(When fortune-telling is performed using the column eporolle and input, the potential of the bit line 13a is 5 to 0, and the above rFjli!I electric 1 ke Vm is set instead of 1. Therefore, the bit line t3a is If it is Ov, despite the potential of the element isolation region 10, there is an area where one toyaria is adjacent to the other via X1 in the figure!it l Ib?li
However, in the semiconductor memory device of this example,
The leakage of the intermediate potential V m i to the capacitor 11b which is in contact with the element by μA larger than the potential of the element S'J region 10 is suppressed every month. -Nita, by setting the two-leg intermediate potential Vm, the potential of the switching transistor 12b is the two-leg intermediate potential +! /, since the value is smaller than V m, the non-Δ selection switching transistor 12b
Leakage through ×2 in the figure is also prevented, and malfunctions such as bit reversal are effectively prevented! will be subject to

Note that the switching transistors 12a and 12b are pM
In the positive case of an os transistor, the relationship of potentials is reversed, but it can be treated in the same way, for example, carriers can be injected.
As an example, the electric currents i and I have the same relationship as OV.

Next, a sense amplifier circuit which can be used in an example semiconductor memory device and which can easily generate the intermediate potential Vm will be described with reference to FIGS. 2 to 5. Note that these sense amplifier circuits 1 and 13 form a part of the semiconductor memory device of the present invention.

First, the sense amplifier circuit shown in FIG. 2 connects the NMOS transistor 21 to the common connection point 25 of the NMOS transistors 23 and 24 of the sense amplifier 22, each consisting of a pair of PMO3) runnostars and N~10SI-runsistors. Connected.

The gate of this NMOS transistor 21 is connected to the common connection point 25, and the source and drain of this NMOS transistor 21, which are not connected to the common connection point 25, are supplied with a signal for driving the sense amplifier circuit. (1) n is supplied.

The NMO5 transistor 21 shown in FIG. 2 is particularly formed in a P-type -N) diode, and the normal plate potential V's is, for example, a diode (for example, OV).
By setting the value of the two consecutive Δ■ to its dark value voltage vth
Therefore, it is possible to easily supply the intermediate potential Vm having a value larger than the first potential of, for example, 0■ by the dark value voltage VLh to the bit line or the like.

The sense amplifier circuit shown in FIG. 3 has a warp, a pair of P
Sense amplifier 32ON configured with MOS transistor and NMO3) Randisk MOS transistor 3
3.34, an NMOS transistor 31 is connected to the common J +N connection point 35. The gate of this NMO5) transistor 31 is connected to the common connection point 35 mentioned in 4.
l) 4: At the point 35) A signal Φ for driving the relevant sense amplifier circuit is connected to the source and drain.
n is supplied.

The NMOS transistor 31, not shown in FIG. The value of can be taken as its dark value voltage ■th,
For example, it is possible to easily supply an intermediate potential m having a value larger than the first potential of OV by the dark value voltage vth to a bit line or the like.

The sense amplifier circuit shown in FIG.
The NM○S transistor 43 of the sense amplifier 42 is composed of an OS transistor and an NMO3) transistor.
At the common connection point 45 of 44, P~! OS transistor 41
are connected. The gate of this PMOS transistor 41 is connected to the PMOS transistor 41 that is not connected to the common connection point 45.
A, No. 3 Φ which is commonly connected to the source and drain of the S transistor 41 and drives the Y1 sense amplifier circuit.
n is iJ%,,I+ ('?1.ru.

The NMO transistor 41 shown in FIG. 4 is particularly formed on an N-type substrate, and by setting the substrate potential Vss to, for example, the power supply voltage Vcc (for example, OV), the above-mentioned ΔV can be reduced. (11 “1”) Dark value voltage Vt
n+k (Vcc)! (Substrate effect J.

A higher intermediate potential Vm can be supplied to the bit line or the like.

The sense amplifier circuit shown in FIG.
NMOS transistor 53.
A 2MO3) transistor 51 is connected to a common connection point 55 of 54. The gate of this PMOS transistor 51 is connected to the PMOS transistor 51 that is not connected to the two-leg common connection point 55.
It is commonly connected to the source and drain of the L-transistor 51 and is supplied with a signal Φn for driving the sense amplifier circuit.

The NMOS transistor 51 shown in FIG. 5 is formed where an N-type well is formed in a P-type substrate, and by setting the substrate potential Vss to the potential of the common connection point 55, the above-mentioned The value of
An intermediate potential Vm having a value larger than i by voltage Vth can be supplied to a bit line or the like.

Sense amplifiers shown in Figures 2 to 5 in Section 2: (No. 11 is an NMo5
This circuit is used when the transistor is used, but when the switching transistor of the memory cell is a 2MO3) transistor, the sense amplifier 22.32.42
．． The source/drain regions of the 52 PMO3I-transistors are common (the transistor 21 is connected to the
．． 31.4151 can be connected to reverse the potential relationship.

Alternatively, a diode may be used.

Note that the above Φn and Φp supplied to the transistors l) to fOS) of the sense amplifier are controlled as shown in FIG. 6, for example. The falling and rising timings of Φn and Φp are not limited and are the same as conventional well-known control) 1. By using the sense amplifier circuit as described above, the approximate threshold value of each transistor can be adjusted. It is possible to easily create eight intermediate potentials Vm corresponding to the voltage vth.
, 1 to control the bit line using the intermediate potential Vm of 2
], it is possible to effectively prevent leaks and the like, thereby increasing the reliability of the memory operation.

In the above-described embodiments, an example in which the switching transistor is an NMO3) transistor has been mainly described, but a PMO5) transistor may also be used. Further, the semiconductor memory device is not limited to DRAM, and any semiconductor memory device may be used without departing from the gist of the present invention.
It goes without saying that the 'l' device can also be used.

H3 Effects of the Invention The semiconductor memory device of the present invention prevents harmful effects such as leakage from the above-mentioned control 1111 of the read/write line without increasing the gate length or the width of the element area. Therefore, the degree of integration of the device can be improved, and malfunctions such as bit inversion can be prevented, thereby increasing the reliability of the memory operation.

Furthermore, from a design standpoint, for example, the threshold voltage vth of the switching transistor can be lowered to an extent that does not become too high, and the degree of freedom and speed in designing this peripheral circuit can be improved.

Further, in terms of manufacturing, even if there are variations in the dark voltage Vth of the switching transistors, the switching transistors can operate satisfactorily, which is advantageous in terms of yield.

[Brief explanation of drawings]

FIG. 1 is a diagram of a semiconductor memory device of the present invention,
The first circle (a) is a cross-sectional view of an example of the semiconductor memory device of the present invention, and FIG. 13 shows an example of a sense amplifier circuit according to a semiconductor device. Figure 4 is a circuit diagram showing still another example of the sense amplifier circuit in the semiconductor memory device of the present invention, and Figure 5 is a circuit diagram showing still another example of the sense amplifier circuit in the semiconductor memory device of the present invention. This is the circuit 14 which shows another example of the sense amplifier circuit (Hiiragi's Matari Jyō, 2) related to the above-mentioned sense amplifier circuit.
Waveform diagram showing the clock for Dil' 3, No. 7
The figure is a diagram for explaining the problems of the conventional method, and FIG.
Z (7) Sectional IF + J diagram, No. 7121 + bl Haso (
7) A diagram showing an example of the potential relationship, and FIG. 7(C) shows another example of the potential relationship.
12.11.1.2b... Switching trunk 13a, 1.3b... Bit line 1'f ++
'F Out jcji Person Sony Stock Representative Company Agent Patent Attorney Koike Mimi
In Murakae - waveform diagram Figure 6 and L Song α sequence Figure 7

Claims (1)

[Claims] Memory cells each having an information signal holding means and a switching transistor disposed between the information signal holding means and a read/write line are arranged, and the voltage of the read/write line is set to a first level. In a semiconductor memory device in which writing is performed by changing a potential between a potential and a second potential, a first potential that can inject carriers into the information signal holding means of a switching transistor connected to the read/write line is set to a first potential. 1. A semiconductor memory device characterized in that the semiconductor memory device has an intermediate potential shifted toward the potential side of No. 2.