JPS5538611A - Memory circuit - Google Patents

Memory circuit

Info

Publication number
JPS5538611A
JPS5538611A JP10879278A JP10879278A JPS5538611A JP S5538611 A JPS5538611 A JP S5538611A JP 10879278 A JP10879278 A JP 10879278A JP 10879278 A JP10879278 A JP 10879278A JP S5538611 A JPS5538611 A JP S5538611A
Authority
JP
Japan
Prior art keywords
signal line
bit lines
coupling
sense
sense output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10879278A
Other languages
Japanese (ja)
Other versions
JPS6156596B2 (en
Inventor
Osamu Kudo
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10879278A priority Critical patent/JPS5538611A/en
Publication of JPS5538611A publication Critical patent/JPS5538611A/en
Publication of JPS6156596B2 publication Critical patent/JPS6156596B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To perform refresh operation of low power consumption in safety by amplifying a difference in voltage between a couple of bit lines and then by outputting it as a complementary output to a sense output node. CONSTITUTION:Throught pre-charge signal line (phiP), bit lines D and D' are pre- charged by using transistors TrQP11 and TrQP21. Then, address and dummy address signal lines W and Wd are driven to read pieces of information of a memory cell and dummy cell to bit lines. After those pieces of information are applied to sense output nodes (a) and (a ), separate signal line (phiC) is decreased down to a low potential to turn coupling TrQR11 and QR21 OFF. Next, the sense output nodes are boosted up through coupling capacitors CP11 and CP21 at the same time that activation TrQS1 is turned ON by driving sense activation signal line (phiS). As a result, the level of the H side surpasses a high power potential and the level of the L side decreases down to a low power potential. Then, coupling Tr at the L side turns ON to discharge the bit line at the L side and Tr at the H side never turns ON to hold the charge at the H side.
JP10879278A 1978-09-04 1978-09-04 Memory circuit Granted JPS5538611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10879278A JPS5538611A (en) 1978-09-04 1978-09-04 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10879278A JPS5538611A (en) 1978-09-04 1978-09-04 Memory circuit

Publications (2)

Publication Number Publication Date
JPS5538611A true JPS5538611A (en) 1980-03-18
JPS6156596B2 JPS6156596B2 (en) 1986-12-03

Family

ID=14493587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10879278A Granted JPS5538611A (en) 1978-09-04 1978-09-04 Memory circuit

Country Status (1)

Country Link
JP (1) JPS5538611A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56127992A (en) * 1980-02-11 1981-10-07 Fairchild Camera Instr Co Method of discriminating logic state of memory cell and sense amplifier
EP0045215A2 (en) * 1980-07-29 1982-02-03 Fujitsu Limited Active pull-up circuit
EP0056433A2 (en) * 1981-01-19 1982-07-28 Siemens Aktiengesellschaft Reading circuit for a monolithic integrated semiconductor memory
US4542484A (en) * 1981-08-05 1985-09-17 Nippon Electric Co., Ltd. Sense amplifier with high speed, stabilized read-out
USRE37593E1 (en) 1988-06-17 2002-03-19 Hitachi, Ltd. Large scale integrated circuit with sense amplifier circuits for low voltage operation
USRE40132E1 (en) 1988-06-17 2008-03-04 Elpida Memory, Inc. Large scale integrated circuit with sense amplifier circuits for low voltage operation
JP2008234829A (en) * 2004-03-08 2008-10-02 Fujitsu Ltd Semiconductor memory

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0524237Y2 (en) * 1986-06-06 1993-06-21
JPH0527037Y2 (en) * 1986-09-12 1993-07-08
JPS63105900U (en) * 1986-12-26 1988-07-08
JP2008269785A (en) * 2008-07-04 2008-11-06 Renesas Technology Corp Semiconductor memory device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56127992A (en) * 1980-02-11 1981-10-07 Fairchild Camera Instr Co Method of discriminating logic state of memory cell and sense amplifier
EP0045215A2 (en) * 1980-07-29 1982-02-03 Fujitsu Limited Active pull-up circuit
EP0056433A2 (en) * 1981-01-19 1982-07-28 Siemens Aktiengesellschaft Reading circuit for a monolithic integrated semiconductor memory
US4542484A (en) * 1981-08-05 1985-09-17 Nippon Electric Co., Ltd. Sense amplifier with high speed, stabilized read-out
USRE37593E1 (en) 1988-06-17 2002-03-19 Hitachi, Ltd. Large scale integrated circuit with sense amplifier circuits for low voltage operation
USRE40132E1 (en) 1988-06-17 2008-03-04 Elpida Memory, Inc. Large scale integrated circuit with sense amplifier circuits for low voltage operation
JP2008234829A (en) * 2004-03-08 2008-10-02 Fujitsu Ltd Semiconductor memory

Also Published As

Publication number Publication date
JPS6156596B2 (en) 1986-12-03

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