JPS6156596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit device using an insulated gate field effect transistor.

1 transistor/cell type MOS memory [X]
In this case, there is no need to increase the amount of information stored in memory cells and reduce power consumption. For this purpose, a sense circuit is required that has a large potential difference between "high level" and "low level" during refreshing and has low power consumption. FIG. 1 shows a conventional sense circuit. In this sense circuit, after reading information from the memory cell, the potential of the signal line φ _C is set to an intermediate level to drain the charge from the "low" side bit line, so it is possible to achieve low power consumption. At the same time, the charge on the bit line on the high side also dissipated to some extent, so the potential difference between the low and high levels during refreshing decreased, and the amount of information stored in the cell decreased. In order to improve this drawback, the sense circuit shown in FIG.
This is a method in which the signal line φs that activates the sense circuit is also applied to the sense node through a capacitor to raise the "high" level (Proceedings of the 1978 IEICE Semiconductor Division National Conference, P136). Although this sense circuit can compensate for the potential difference between the "high" and "low" levels, it requires a large capacitance, resulting in an increase in bit line capacitance, which is not desirable in terms of cell area and sense sensitivity.

An object of the present invention is to propose a sense circuit that consumes low power and has a large potential difference between "high" and "low" levels during refreshing.

The sense circuit according to the present invention is a memory circuit using a gated flip-flop type sense circuit that amplifies the voltage difference between a pair of bit lines and outputs it as a complementary output to a sense output node. first and second transistors each including a transistor for transmitting a signal between the bit line and having one end connected to the output node and the other end connected to a signal line that is activated after reading information from the memory cell; It is characterized by having a capacity of 2.

According to the present invention, because of the presence of the capacitor whose terminals are the sense output node and the signal line, it is possible to suppress the dissipation of charges on the "high" side. Further, because the capacitance is extremely small due to the action of the transistor interposed between the sense output node and the bit line, there is no need to substantially increase the capacitance of the bit line. Therefore, the amount of information in the memory cell can be expected to increase with low power consumption, and highly reliable memory operation can be achieved.

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 3A and 3B are a circuit diagram and an operation waveform diagram of an embodiment of the present invention.

In this embodiment, the sources and drains of coupling transistors Q _R21 and Q _R11 are connected between complementary bit lines D and sense output node a, respectively, and the separation signal line φc is connected to their gates. In addition, the sense output node a has a coupling capacitance
Cp ₂₁ and Cp ₁₁ are connected to sense activation signal line φs. In this embodiment, the transistor Q _R11 ,
Q _R21 is a depletion type transistor with a threshold voltage of -2V, and the other transistors are all enhancement type transistors with a threshold voltage of 1V.

First, the bit line D is precharged by the precharge signal line φp using the transistors Qp ₁₁ and Qp ₂₁ .

Next, address and dummy address signal lines W
and Wd are driven to read the information of the memory cells and dummy cells to the bit lines. After taking this information into the sense output node a, the separation signal line φ
c to a low voltage, and the coupling transistors Q _R11 , Q _R
Turn off ₂₁ . After this, the sense activation signal line φs
Activate transistor Qs by driving ₁
At the same time as turning on, the sense output node a is booted up through the coupling capacitors Cp ₁₁ and Cp ₂₁ . This operation causes the "high" side level to rise above the high power supply potential, and the "low" side level to move toward the low power supply potential. Since the coupling transistor is of the depletion type, as the "low" side sense output node drops, the "low" side coupling transistor turns "on" and the charge on the "low" side bit line is dissipated. On the other hand, the potential of the “high” side sense output node is higher than the “high” side bit line potential, so
The "high" side coupling transistor is not "turned on" at all, and no charge on the "high" side bit line is lost.

The present invention provides that the transfer gate in the circuit shown in FIG. 3 is a depletion type transistor.
QR ₁₁ and QR ₂₁ . Therefore, when reading out information from a memory cell and transmitting it to nodes a and a of the sense amplifier, a potential approximately equal to the power supply potential is applied to the gate of the depletion type transistor, thereby making the depletion type transistor sufficiently conductive. A large amount of cell signal can be effectively transmitted to the sense node.

On the other hand, when a normal enhancement transistor is used as a transfer gate, the level decreases by the threshold of this transistor, especially when transmitting a high-level signal, and the variation in threshold between the two transfer gates cancels out the readout signal. This makes high-sensitivity reading difficult.

Furthermore, in the present invention, which uses a depletion type transistor when the sense amplifier is activated, by grounding the gate of this transistor, the transfer gate connecting the low level side bit line and the sense node is turned on, and therefore the bit line is The width can also be effectively increased. In order to perform such an action with an enhancement type transistor, the gate potential must be set to an intermediate level, which makes reproducibility and controllability difficult.

As shown in this example, according to the invention,
Refresh operation is extremely safe and low power consumption operation is possible.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional sense circuit, FIG. 2 is a circuit diagram of another conventional sense circuit, FIG. 3A is a sense circuit diagram of an embodiment of the present invention, and FIG.
3 is an operation waveform diagram of FIG. A. FIG.

Claims (1)

[Claims] 1. In a memory circuit using a gated flip-flop type sense circuit that amplifies the voltage difference between a pair of bit lines and generates complementary outputs at a pair of sense output nodes, a depletion type transistor for controlling signal transmission; and first and second capacitors each having one end connected to the output node and the other end connected to a signal line that is activated after reading information from the memory cell. . A memory circuit characterized in that the depletion type transistor takes approximately two values of a power supply potential and a ground potential, and is controlled by a signal that changes from the power supply potential to the ground potential with the start of sensing.