JPS6326897A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To attain the battery back-up of a refreshing operation by making the number of word lines at the time of refreshing smaller electrically than the number of word lines at the time of read and write operation, thereby reducing power consumption when the chip is not selected. CONSTITUTION:As a refreshing control signal line is activated at the time of refreshing operation, word separate control signals 14, 14' are activated by division control devices 13, 13' irrespective of signal values of decoding signal lines 12, 12'. Accordingly, when a specific word line 6 is activated, division word lines 7, 7' are activated. In such case, a specific bit line 8 is not selected, and charge precharged to the bit line 8 is sent to a memory cell 3, accumulated information is written again by amplifying function of the cell itself. As the cell itself has the amplifying function of self accumulated voltage, time required for refreshing of information can be shortened very small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device using volatile memory cells, and in particular to a semiconductor memory device using volatile memory cells, and in particular to an MO3 semiconductor memory device that enables information storage using a battery.
The present invention relates to random access memory devices.

[Conventional technology]

As a semiconductor memory device using volatile memory cells,
Examples include dynamic memory devices and pseudo-static memory devices. Since these memory devices do not have a current supply means for statically holding information in the memory cells, the cell area can be reduced and they are suitable for high integration. (1985 IEEE International Solid State Circuits Conference (1985 IEEE Inter
nationalSolid-3tate C1rcu
its Conference) February 15, 1985, pp. 250-251) (11th European Solid State Circuit Conference)
Solid 5tate C1rcuit Confe
rCnce) September 16-18, 1985, 139-1
(p. 46) However, in these memories "A'12," information cannot be refreshed with sufficiently low power, and therefore information cannot be stored using batteries.

[Problem that the invention seeks to solve]

In the conventional memory devices mentioned above, reading information
In order to achieve low power consumption and high-speed operation in a chip selected state in which a write operation is performed, only the minimum necessary number of word lines is activated. That is, a so-called word line division technique is used to equivalently increase the number of word lines.

By the way, the chip non-selection (standby) state f5i that performs the refresh (reproduction) operation of information stored in the memory cell
The power consumption pop required to supply power to the bit line in this case is expressed by the following equation.

Pnp=k・(ΔVB/VCC)”・C[lB−2
N□(1) where k is a constant, ΔVs is bit line voltage amplitude, VCC
is the power supply voltage, CBB is the bit line capacitance per unit bit,
N is the number of addresses required for word line selection (therefore, Q
N is the number of word lines). According to equation (1) above, in order to satisfy the requirements during read and write operations, the value of N must be increased, so the power consumption during refresh operations is reduced to the extent that battery backup is possible. Can not do it.

In addition, in the above memory device, in the chip selection state where read and write operations are performed, a so-called precharge period is required to charge the bit line within a certain cycle time. A means of supplying power to the bit lines must be used. On the other hand, when the chip is not selected for refresh operation,
Make the cycle time sufficiently large without destroying information (
(100 times more than in the chip selection state). However, in the above-mentioned conventional memory cell device, the same bit line power supply means is used regardless of whether a chip is selected or not, so the power required to drive the bit line power supply means when a chip that performs a refresh operation is not selected is There was a problem that it could not be reduced.

An object of the present invention is to extremely reduce power consumption during a refresh operation in a chip non-selected state in a semiconductor memory device using volatile memory cells as described above, and to enable battery backup for the refresh operation. It is in.

[Means for solving problems]

In order to achieve the above object, the first aspect of the present invention is to increase the number of word lines during a read and write operation without using a method of increasing the number of word lines by dividing word lines during refresh. It is characterized by comprising a means for electrically reducing the number of parts.

In addition, the second aspect of the present invention is to provide two types of bit line power supply means with different driving powers for each bit line, and when reading and writing, the bit line has a driving power suitable for the read and write operations. Use the supply means and drive when refreshing! The present invention is characterized by switching to a bit line power feeding means having a small PIIFrX force, that is, a small self-parasitic capacitance.

[Effect]

Refreshing information is started by activating a word line, reading the information of all memory cells connected to the word line onto each bit line, and amplifying this information by the memory cell itself or by a column amplifier. The data is stored in the memory cell again and the process ends. Therefore, in a refresh operation, some word lines can be shared as long as the bit lines are not shared through memory cells.

That is, during a refresh operation, the number of word lines can be equivalently reduced compared to during read and write operations, thereby achieving lower power consumption.

Furthermore, the cycle time during the refresh operation in the chip non-selected state can be made approximately 100 times longer than the cycle time during the read and write operations.

Therefore, the precharge period for charging the bit line can be similarly lengthened. Therefore, the driving power of the power feeding means to the bit line can be reduced accordingly, and in other words, the self-parasitic capacitance thereof can also be reduced. In this way, by switching to a bit line power supply means with a smaller driving capacity during a refresh operation than during a read or write operation, the electric power for driving the bit line power supply means can ideally be reduced to one-hundredth of the conventional power.
It can be made smaller and lower power consumption can be achieved.

〔Example〕

FIG. 1 is a schematic circuit diagram of a memory device according to a first embodiment of the present invention in which a volatile memory cell having a self-amplification function is used, and FIGS. 2(a) and 2(b) show a circuit diagram.

FIG. 2(a) is a signal timing chart showing an example of the operation waveform, and FIG. 2(b) is a signal timing chart during an information read operation, and FIG. 2(b) is a signal timing chart during a refresh operation.

In the figure, 1.1' is a memory array, 2 and 2' are bit line power supply means arrays, 3 is a memory cell, 4 is a bit line power supply means, 5 is a word line dividing means, 6 is a main word line, and 7.
7' is a divided word line, 8 is a bit line, 9 is a power supply line, 10
11 is a refresh control signal line; 12.12' is a decode signal line; 13.13
' is word line division control means according to the present invention, 14.14'
indicates a word line division control signal line.

The operation of a memory device having such a configuration is started when an input signal to the chip changes or when a refresh control signal inside the chip is activated. First, all bit lines 8 in the memory array are precharged by the bit line power supply means 4. In the case of reading information from a memory cell or writing information to a memory cell, since the refresh control signal line 11 is inactive, the decode signal lines 12 and 12' by the address decoder are used as the word line division control means. 13 and 13' and word line division control signal lines 14 and 14', the signals are inputted as they are to the word line division means 5. Next, when a specific word line 6 is selected and activated, only one of the divided word lines 7 and 7' is activated (in FIG. 2(a), the divided word line 7 is activated).
is activated), read and write operations to the memory cell 3 are performed via the bit line 8.

On the other hand, in the case of a refresh operation, the refresh control signal line 11 is activated, so the word line division control means 13.13' controls the word line division regardless of the signal on the decode signal line 12.12'. Signal line 14.
14' are activated together. Therefore, firstly, when a specific word line 6 is activated, divided word lines 7 and 7' are activated together. In this case, a particular bit line 8 is not selected, and therefore the charge precharged on the bit line 8 flows into the memory cell 3, and the stored information is written again by the amplification function of the cell itself. In this case, since the cell itself has a self-storage voltage amplification function, the time required to refresh information can be minimized, and therefore the voltage amplitude ΔVn (formula (1)) of the bit line is also less than O, SV. can do.

According to this embodiment, the number of word lines during refresh operation is 2.
N (formula (1)) is 1 compared to the case where the embodiment is not applied.
/2. Also, bit line voltage amplitude ΔV
n (formula (1)) can also be miniaturized as described above. Therefore, the power consumption when a chip that performs a refresh operation is not selected can be extremely reduced, making it possible to realize a battery backup memory device that requires low power.

FIG. 3 is a diagram showing a more concrete example of the embodiment shown in FIG. This is a case where a cell composed of MOSFETs is used.

Further, FIG. 4 is a diagram of another embodiment specifically showing the embodiment of FIG. 1, in which a cell composed of one MOSFET and one capacitor is used as the memory cell 3. . In this case, each bit line 8
A column sense amplifier 15 is provided.

Therefore, in this embodiment, it is not possible to make the bit line voltage amplitude ΔVa as small as in the embodiment shown in FIG. As is clear from equation (1), it is possible to reduce the power consumption during the refresh operation, making it possible to realize a battery backup memory device.

Note that the memory cells used in the present invention can basically be used as long as they are volatile cells. In particular, a four-element type memory cell composed of four MOSFETs, as in the embodiment shown in FIG. , N
It is formed within a P-type well formed on a mold substrate. Also,
Needless to say, the present invention can also be applied to a 4MO5 type memory cell in which PMO8FET is used as a transfer transistor and NMO3FET is used as a drive transistor. In this case, the memory cell is selected and refreshed when the word line is at a low level.

In addition, in the above embodiment, in order to simplify the explanation, the number of word line divisions is set to 2 during non-refreshing (read and write operations), but the number of word line divisions is set to 2 during non-refreshing operations (read and write operations). In order to achieve this, it is necessary to further increase the number of word line divisions.

In the above embodiment, it is of course possible to increase the number of word line divisions, but in that case, (1)
As is clear from the formula, the above effects can be further improved.

Further, in the above embodiment, the word line dividing circuit has been described as an example, but the present invention can be applied to all word lines that do not share a bit line via a memory cell.

FIG. 6 is a circuit diagram schematically showing a second embodiment of the present invention. In the figure, 3 is a memory cell, 40
41 is a bit line power supply means which is activated by the drive signal line 10 when a chip is selected (during read and write operations) and supplies charge from the power supply line 9 to the bit line 8; 41 is a bit line power supply means when the chip is not selected (
A bit line power supply means is activated by the drive signal line 10' during a refresh operation) and supplies charge from the power supply line 9 to the bit N8. 6 indicates a word line. Access to the memory cell in the chip selected state is as follows: The process is started by activating the bit line power supply means 2 having a large driving capacity using the drive signal line 10 and precharging the bit line 8 at high speed. Thereafter, a predetermined bit line and word line are selected by a decode signal, and information is written into and read from a predetermined memory cell via the bit line. In this case, in order to shorten the cycle time required for the access operation, the time required for bit line precharging is minimized. That is, it is necessary to increase the driving power of the bit line power supply means 40. On the other hand, in a chip non-selected state, an information refresh operation is performed so that the information stored in the volatile memory cells is not destroyed. This operation is started by activating the bit line power supply means 41 by the drive signal line 10' and precharging the bit line 8. Then, a predetermined word line is selected and the information data output on the bit line is transferred to the memory. This is performed by amplifying the data by the cell itself or by a column sense amplifier, etc., and then rewriting the data into the memory cell. In this case, the difference from the chip selection state is that the cycle time required to refresh the information stored in the memory cells is sufficiently large without destroying the information (100 times the access cycle time in the chip selection state). (above)). Therefore, in this case, the time required for precharging the bit line can be similarly increased. That is, the driving power of the bit line power supply means 41 can be reduced.

As a result, the parasitic capacitance of the bit line power supply means driving signal line can be dramatically reduced, so that the power required to drive the bit line power supply means can be reduced.

According to this embodiment, the power required to drive the bit line power supply means when a chip is not selected can ideally be reduced to 17100 or less compared to the case where the present invention is not applied. Since the power consumption can be extremely reduced, it has a great effect on realizing a memory device capable of battery backup that requires low power consumption.

FIG. 7 is a diagram of an embodiment specifically showing the embodiment of FIG. 6, in which an NMO3FET is used as the bit line power supply means 40 and 41, and a cell consisting of four NM○5FETs is used as the memory cell. This is the case.

FIGS. 8(a) and 8(b) are diagrams showing an example of the operation waveforms, and FIG. 8(a) is during an information read operation.

FIG. 6(b) shows a signal timing chart during a refresh operation.

When access to a memory cell is started by an external signal or the like in the chip selection state (at the time of read or write operation), the bit line power supply drive signal line 10 becomes high potential regardless of the previous state and the bit line The power supply means 40 is activated and the bit line 8 is precharged at high speed. During a period in which a predetermined word line 6 is selected, the signal is at a low potential, the bit line power supply means 40 is inactivated, and during this period, information in the memory cell 3 is read out via the bit 88. When the read is completed, the bit line is again precharged at high speed by the signal from the drive signal line 1O in preparation for the next access. In this case, the drive signal line 10' is fixed at a low potential and the bit line power supply means 41 is not activated. On the other hand, in the chip non-selected state (during refresh operation), the drive signal line 10 is fixed at a low potential, the bit line power supply means 40 is not activated, and the drive signal line 10' and the bit line power supply means 41 operate as described above. Perform the same action. However, since the cycle time in this case is sufficiently longer than in the above-mentioned case, after the memory cell's own information amplification function completes the refresh at high speed, the bit line power supply means 4 with low driving capacity
1 to pre-charge the bit line at a low speed. Therefore, the power required to drive the bit line power supply means can be reduced.

FIG. 9 is a diagram of another embodiment specifically showing the embodiment of FIG. 6, in which NMO3FE is used as the bit line power supply means 40.
'T is a case where a PMO3FET is used as the bit line power supply means 41. In this case, FIGS. 10(a) and (b)
As shown in FIG. 3, by reversing the low potential side and the high potential side of the waveform of the drive signal line 10' in the above embodiment, the same operation as in the above embodiment can be achieved.

Note that the memory cells used in the present invention can basically be used as long as they are volatile cells. In particular, a four-element memory cell composed of four NMO3FETs, as in the embodiment shown in FIG. 7, is optimal. Formed within the mold well. Also.

It goes without saying that the present invention can also be applied to a 4MO3 type memory cell in which a PMO3FET is used as a transfer transistor and an NMO5FET is used as a drive transistor. In this case, the memory cell is selected and refreshed when the word line is at a low level.

Further, FIG. 11 is a diagram of still another embodiment specifically showing the embodiment of FIG. 6, in which one NMO3 is used as a memory cell.
This is the case when a cell consisting of one capacitor is used. 12th
Figures (a) and (b) are diagrams showing examples of the operation waveforms,
tzl(a) is a signal timing chart during an information read operation, and FIG. tzl(b) is a signal timing chart during a refresh operation. In this case, since the memory cell itself does not have an information amplification function and reading information from the cell is destructive reading, the read operation and refresh operation are performed using the dummy cell 16 and column sense amplifier 15, but the bit Regarding the line driving method, the operation is similar to that of the previous embodiment. Therefore, in this case as well, as in the previous embodiment, the power consumption during refresh operation can be extremely reduced.

〔Effect of the invention〕

As explained above, according to the present invention, information can be read,
Since the power consumption during the refresh operation can be reduced without affecting the write operation in any way, it is possible to realize a memory capable of battery backup that requires low power consumption.

[Brief explanation of the drawing]

1 is a schematic circuit diagram of an embodiment of the first invention of the present invention, FIGS. 2(a) and 2(b) are diagrams showing operating waveforms of the circuit of FIG. 1, and FIG. 3 is a diagram of the circuit of FIG. 4 is a circuit diagram showing another specific embodiment of FIG. 1; FIG. 5 is a schematic circuit diagram of the second embodiment of the present invention; FIG. 6 is a circuit diagram showing a specific embodiment of the present invention; is the fifth
A circuit diagram showing a specific embodiment of the figure, FIGS. 7(a) and (b)
is a diagram showing operating waveforms of the circuit in FIG. 6, FIG. 8 is a circuit diagram of another embodiment of FIG. 5, and FIGS. 9(a) and (b) are diagrams showing operating waveforms of the circuit in FIG. 8. 10 are circuit diagrams of still another embodiment of FIG. 5, and FIGS. 11(a) and 11(b) are diagrams showing operating waveforms of the circuit of FIG. 10. 1.1'...Memory cell array 2.2'...Pit line power feeding means array 3...Memory cell 4.40.41...Bit line power feeding means 5...Word dividing means 6...・Main word line 7.7'...Divided word line 8...Bit line 9...Power line 10.10'...Bit line power supply means drive signal line 11・
...Refresh control signal lines 13, 13'...Word line division control means 14, 14'
...Word line division control signal line 15...Column sense amplifier 16...Dummy memory cell

Claims (1)

[Claims] 1. In a semiconductor memory device using volatile memory cells, means for electrically making the number of word lines during an information refresh operation smaller than the number of word lines during read and write operations. A semiconductor memory device comprising: 2. In a semiconductor memory device using volatile memory cells, a first power supply unit supplies power to the bit line during information read and write operations, and a second power supply unit supplies power to the bit line during a refresh operation. A semiconductor memory device comprising: means. 3. The semiconductor memory device according to claim 2, wherein the drive power of the second power supply means is smaller than the drive power of the first power supply means.