JPS55153194A - Integrated semiconductor memory unit - Google Patents

Abstract

PURPOSE:To provide dynamic MOSRAM with a sufficient automatic refreshing function by composing a memory cell of two transistors and one storage capacitor. CONSTITUTION:Memory cell 1 consists of transistor TR controlling input-output operation for memory information, TR controlling the refreshing of memory information and storage capacitor. When activated clock 10 is high in level, refresh word line RW, for example, is selected and held at a high level to read charge accumulated in the storage capacitor to refresh bit line RB1, and refresh bit line RB2, on the other hand, is held at an intermediate potential between two high and low levels by dummy cell 4. Then, activating refreshing sense amplifier 3 amplifies the potential difference between bit lines RB1 and RB2 and refreshed memory information is rewritten in cell 1. When clock 10 is low in level, refreshing operation comes into effect by a clock generated by low-frequency clock generating circuit 12.