JPS63275096A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a pseudo static RAM having no loss in an access time by commonly placing two sense systems in respective memory cells. CONSTITUTION:The memory cell can be connected to any adjacent bit line by two transistors. A word line system is divided into the two systems, the word line can be independently selected and raised, the respective half of the bit lines are used to have the two sense systems and the sense system of a folded bit line system can be attained. For instance, when the word line WL0 is selected by a row decoder #1, the respective memory cells are connected every other bit line by the selected word line, respective sense amplifiers are connected to respective bit line pairs divided at the center and every other sense amplifier is activated by the sense amplifier activating signals of the two systems. Thereby, the pseudo static RAM having no loss in the access time is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to semiconductor memory devices, particularly pseudo-static RA.
It concerns M.

(Prior Art) Conventionally, semiconductor memory devices, particularly MOS RAMs, are divided into dynamic types and static types depending on the operating state of the memory cells. Dynamic RAM is suitable for increasing capacity because the number of prime elements constituting a memory cell is smaller than that of static RAM. On the other hand, dynamic RAM has the disadvantage that the timing of externally supplied signals required for its operation is rougher than that of static RAM, and timing control is difficult. Therefore, pseudo-static RAM has the ability to adjust the volume to human level, and external timing control is as easy as static RAM.
(1'5eudo 5tatic RAM, Virtu
ally 5tatic RAM) has been proposed.

This pseudo-static RAM will be described below as a conventional example.

FIG. 8 is a configuration diagram of a conventional pseudo-static RAM;
The figure is an operation timing diagram. This RAM is 1
It uses a memory cell consisting of two transistors and one capacitor, and the refresh operation of the memory cell data required for this is performed completely on-chip, and has a structure that allows it to operate in the same way as a static RAM. be.

In FIG. 8, the refresh timer measures the time interval at which refresh is required, and outputs a refresh operation request signal when the time at which refresh is required is reached. At this time, if the memory cell section is not used in normal operation, a refresh operation is performed immediately,
If it is in use, wait until the memory cell section is released before starting the fresh operation. Conversely, if the refresh operation is performed first, the normal operation is also started after waiting for the refresh operation to be completed. At this time, the access time increases.

The normal/refresh selector shown in the figure performs such switching between normal/refresh operations. As a result, the address signal input to the row decoder is switched between an external input row address via the row address buffer or a refresh row address from the refresh address counter. This switching system
This is the address MUX in the figure.

With such a configuration, the user can perform externally static RAM without being aware of the refresh operation at all.
It can be used in exactly the same way. However, on the other hand, as mentioned above, if a refresh operation has been started when entering a normal access cycle, the normal access operation is performed inside the chip after waiting for the end of the refresh operation. In some cases, there is a problem that access time is delayed.

That is, as mentioned above, at fixed time intervals determined according to the refresh timer, the word line corresponding to the row address specified by the refresh address counter rises, and by performing a sense operation, the word line selected by the rising word line is Performs meris cell refresh operation. The address counter counts by 1 each time one refresh cycle ends, and when the count goes back to -1 (1!), which means that the refresh operation has completed one cycle for all word lines, it returns to the original value. Perform the action. In this manner, refresh cycles are performed synchronously with the refresh timer and occur independently of normal access cycles performed by external timing. Therefore, the access time is the longest when the normal access cycle is started immediately after the refresh cycle is started.

FIG. 9 shows operating waveforms in such a case. Now, when the external address input signal is changed, the normal access request state is entered, but at this time, if a refresh cycle has been started, the word line (refresh word line) specified by the 5 address counter for refresh operation. rises and performs sense operation,
After performing the refresh operation, this word line is brought down, and then the word line (normal operation word line) corresponding to the row address input externally for normal access is brought up to perform normal access. As described above, under the worst conditions, the operations of raising the refresh word line, sensing operation, and lowering the refresh word line are extraneous during one cycle, and the access time is delayed by nearly double.

In this type of operation, during the period when a certain word line is turned on and a sense operation is performed, other memory cells connected to the bit line used for this cannot be set to the selected state (other word lines cannot be activated). This is due to a restriction resulting from the structure of the memory cell array of a conventional dynamic RAM.

(Problems to be Solved by the Invention) Since the conventional pseudo-static RAM is configured as described above, it is not possible to perform a refresh cycle and a normal access cycle at the same time. There was a problem with that.

This invention was made in order to solve the problems mentioned in -F, by making the structure of the memory cell array as uncomplicated as possible, and by allowing two sense systems to coexist in each memory cell. A refresh cycle and a normal access cycle can be performed at the same time, so
The object is to obtain a pseudo-static RAM without loss of access time.

(Means for Solving the Problems) A semiconductor memory device according to the present invention has a memory cell array consisting of a plurality of word lines, bit lines, and groups of memory cells located at the intersections of these. The bit line is connected to a first bit line through one transfer gate, and is further connected to a second bit line adjacent to the first bit line through a second transfer gate.

(Function) In the present invention, since the memory cells are divided into two ports without increasing the number of bit lines, a refresh cycle and a normal access cycle can be performed simultaneously.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a memory cell array according to an embodiment. A memory cell is composed of one capacitor and two transistors, and the two transistors connect adjacent bit lines (BLI and BL2.BLI and BL2
) can also be connected. There are two word lines (WL
,,WL,-----・and,WL,',WL,°...
...), and these are as shown in Figure 3.
It is driven by two separate row decoder and word line drive circuit systems. In such a memory cell array,
The word line system is divided into two systems, and word line selection and rising and falling operations are possible for each system independently.

In addition, the total number of bit lines is the same as the conventional folded bit line system shown in FIG.
A system sense system was adopted, and a folded bit line type sense system was made possible.

Below, first, the operation of one of the two sense systems will be explained.

Now, word line WL is input by row decoder #1.

Considering the case where is selected, one memory cell is connected to every other bit line by the selected word line. Every other bit line connected to a memory cell forms a pair of two adjacent bit lines, and each bit line is divided at its center. A sense amplifier is connected to each bit line pair, and every other sense amplifier receives two sense amplifier activation signals (φ!+01 φ3
゜ and φs+, $s+). FIG. 4 shows an example of a sense amplifier circuit.

FIG. 5 shows the operation timing, and FIGS. 6(a) to 6(d) show the waveforms of the bit line potential. Now external signal RA
When S falls, the external manually input row address is latched, and the selected word line rises according to the row address. In the following explanation, a case will be taken as an example in which the word line WL in the meso array block #1 (IT diagram) rises.

When word line WL0 rises at time III t+, memory cells C, , .
C2 is connected, and the signal charges stored in these memory cells appear on their respective bit lines.

Generally, for example, bit line precharge voltage VpH=
In the case of Vcc, △V=+ and -! 3-・・・・・・-(1)-21+
Cn/(:s where CR: Bit line floating capacitance l1t C3: Memory cell capacitance!'i [+: When reading "H" - A potential change that occurs when reading "L" appears on the bit line.

Considering the case of FIG. 1, bit lines BL, BL
,,BT,°, One hundred Ll' floating 8 leaves! -CR, the transistor TI is in the “ON” state, so BL
l, BLt, BL+°, 100,.

Potential change △V a 1. l+ΔViffi,
ΔVdq.

is ΔV, L, l・+−・□ −−−−−−(2)”−2
1+C, /2・CS However, when +: C, = “H” reading –: C1 = “L” reading However, +: C2 = “H” reading –: C, = “L” reading becomes.

Normally, Co /Cs = about 10 to 20, so from the above equation, the signal voltage from the memory cell C1 appearing on BL is equal to the voltage of the memory cell C appearing on BL and B L ro.
This is approximately twice the signal voltage caused by 2.

After this, φ↑ falls at time lit t2, and after transistor T1 becomes “OFF”, φ3 at time t.
° rises, φso falls, and the sensing operation begins. Next, φ↑ rises at time t4.

When φT2 goes low, the signal information of the memory cell C2 detected and amplified by the sense amplifier SAG is written into the memory cell C2 again through BL.

In addition, in FIG. 5, φ1. The ``H'' level of φT 2 + φT3 is V cc + V TIT V
CC+: V T2+ V CC+ V T, is larger. However, v7. .

Va2+vT3 are the threshold voltages of the transistors T2 and T3, respectively.

FIGS. 6(a) to 6(d) show the above operation for four types of stored data in memory cells C, . . . C2.

As a result, it can be seen that for all four methods, the memory cell data is extracted and rewritten once.

Through the above operations, the data of memory cell C1 is finally latched by the sense amplifier SAG, and the data of memory cell C2 is latched by the sense amplifier SA. Since the original accumulated data is written, (1) If nl is raised again and the cycle ends, the read and rewrite operation of the accumulated data, that is, the refresh operation, will be performed for mesori cells C, C2. It has been done.

(2) Also, when the external signal CAS is subsequently turned off to select a column using the column address and output data to the memory cells of the corresponding column, normal and gold operations will be performed. This allows data to be output to the memory cells C, , C2. 7jS 2 shows a circuit diagram of this column selection system.

In this way, the company's operation is completely possible with conventional dynamic semiconductor memory devices.

The upper side is the word line WL0 in meso array block #
However, when a word line having a similar relationship to the word line WL0 in memory array block No. 2 is selected, as shown by the broken line in FIG.
Exactly the same operation is performed by reversing the waveforms of 〒2 and φT3.

By the operation described above, effects specific to the embodiment described below can be obtained.

(1) Every other bit line is kept in a completely inactive state (precharged state), so the capacitive coupling noise between the bit lines activated by this shielding effect is almost completely zero. Become.

In the case of charge method, the sum of stray capacitance of all bit lines is ΣC
R and the cycle period Tc, ■In the conventional example, when sensing, half of the total bits; ■In the embodiment, when sensing, the total bit becomes 1; Furthermore, in the rewrite operation, in the worst case, the total 1 V from ground potential to the bit line. In order to pull up to the C potential, the total is as follows, and even if a rewrite operation is performed, the current consumption will be the same as that of the conventional example at the worst.

In the above embodiment, there is sufficient time between time t3 and t4, and the bit line potential is equal to the ground potential and the power supply voltage (Vcc).
Although the case is shown in which φT2 falls by V- and φ〒1 rises after it is determined, the time interval does not need to be this large. If the time interval is made smaller, the value of equation (6) becomes smaller and can be made close to zero, so
Current consumption is reduced to nearly 2/2 of the conventional example.

(3) Furthermore, since the sensing operation is exactly the same as that of the folded pit line method, the canceling effect of the common mode array noise, which is an advantage of the folded pit line method, is not impaired.

Next, the word a drive system #2 drives the word line W, for example.
The sensing operation when L and ° are selected and activated will be explained. in this case.

In the above explanation, φ3o is φSir φqo
$, BL, BL2. , BL, is Y, , BL,
' to BL, °, BL, ° to BL, °, φPRO to φpH
By replacing each with +, the same company's sense (refresh) operation can be performed.

In the above operation, the two word line drive systems and the sense system do not share a bit line. #! In the word line drive system, bit lines BL,, BL,.

B L 2. Using B L 2 "-"""", in the same #2 system, bit lines 9L+', BLI', BL2°
, BL2°... are used, so both can operate simultaneously.

Here is an example in which a pseudo-static RAM is constructed using a memory cell array that operates as described above.

It is shown in FIG.

In this example, two row decoders $1. #2 and word line drive system #1. @2 uses one (#1) in the normal access cycle and the other (#2) in the refresh cycle. Therefore, the external input row address is input to the row decoder #1 via the row address buffer, and the output of the refresh address counter is input to the row decoder #2. #1 word line drive system is
It is activated by a normal operation request signal from a control circuit, and raises a word line selected by an external manual row address and generates a sense signal (φ3o, φ3°). #2 word line drive system is activated by a refresh operation request signal from the refresh timer,
The word line selected by the row address specified by the refresh address counter is raised and the sense signal frj (old, φII) is generated. At this time, as mentioned above, even if both operate at the same time, the normal access operation and the refresh operation are performed on independent row addresses without any problem, so it is possible to switch between the two and order them as in the conventional example. There is no need to perform additional steps, and there is no delay in access time as in the conventional example.

Further, a normal operation/refresh operation switching circuit (normal/refresh selector) and an atre switching circuit (address MUX) for switching address signals accordingly are not required, eliminating the possibility of malfunction in this part and reducing the circuit area.

As shown above, in this embodiment, refresh operations can proceed simultaneously even during normal access (background refresh is possible), so there is no problem with normal access operations! Automatic refresh is possible without any change in performance, and the characteristics of the pseudo-static RAM can be significantly improved.

Note that in the above embodiment, the bit line precharge potential is -
Although the case where the bit line precharge potential is VCC is shown, the present invention is applicable regardless of the bit line precharge potential.

Furthermore, the present invention can also be applied to cases where on-chip ECC (detection and correction) operations are performed during background refresh, for example, and in this case as well, the E S
There is an advantage that the time required for the arithmetic operation of C does not affect the normal access cycle at all (there is no increase in the access time, cycle time, etc. of the normal access cycle).

Furthermore, the memory cell array shown in the embodiment of the present invention basically has two systems of data output cards for each memory cell, and there is no increase in the number of bit lines, so two-board memory cells can be integrated. Therefore, its application field is not limited to pseudo-static RAM as in the embodiment.

(Effects of the Invention) As described above, according to the present invention, since the refresh cycle and the normal access cycle are configured to be able to be performed at the same time, it is possible to obtain a pseudo-static RAM without loss of access time. There is.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of a semiconductor memory device according to an embodiment of the present invention, FIG. 3 is a configuration diagram of a semiconductor memory device according to the embodiment, and FIG. T14 is a circuit diagram of a sense amplifier in the embodiment. , FIG. 5 is a waveform diagram showing the operation timing of the semiconductor memory device according to the embodiment, and FIGS. 6(a) to (d)
) is a waveform diagram showing the bit line potential in the example, FIG. 7 is a configuration diagram of a semiconductor memory device according to the example, FIG. 8 is a configuration diagram of a conventional semiconductor memory device, and FIG. 9 is a diagram of a conventional semiconductor memory device. The operating waveform diagram, FIG. 10, is a block diagram of the main parts of a conventional semiconductor memory device.

Claims (6)

[Claims] (1) It has a memory cell array consisting of a plurality of word lines, bit lines, and memory cells located at the intersections of these, each memory cell being connected to a first bit line via a first transfer gate, A semiconductor memory device further comprising a structure in which the first bit line is connected to a second bit line adjacent to the first bit line via a second transfer gate. (2) A memory cell selected by a certain word line has a structure in which it is connected to every other bit line that intersects with the word line, and every other bit line forms a pair of two, and each bit The line pair is divided into a first bit line pair and a second bit line pair, and includes first and second sense amplifiers connected to each pair, and the first and second bit line pair are used to store memory cell data. When reading signals to the bit lines, one side of the bit line pair is connected to each other via a transfer gate, and the transfer gate is connected to the other side when the sense amplifier is operating.
It is characterized in that it is brought into a non-conductive state, and after the sense amplifier operates, it is brought into a conductive state again, and the signal potential detected and amplified by the sense amplifier via the transfer gate is rewritten into the memory cell via the bit line on one side. A semiconductor memory device according to claim 1. (3) The sense amplifier and sense amplifier drive signal system are 2
3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is divided into two systems, and includes means for activating one or both of the two systems according to a selected word line. (4) Two systems of row decoders and word line drive systems are provided, and one of the two word lines that select each memory cell is driven by the first system and the other by the second system. A semiconductor memory device according to claim 3, characterized in that: (5) A refresh address counter is provided for specifying a row address to perform a refresh operation, and the externally input row address is input to a first system of row decoders, and the refresh address counter output is input to a second system of row decoders. Claim 4 characterized by
2. The semiconductor storage device described in . (6) Equipped with a refresh timer that specifies the time interval of refresh operation, and uses the output of the refresh timer to
6. The semiconductor memory device according to claim 5, wherein a refresh operation is performed completely asynchronously with an external signal.