JP2861198B2 - Control method of semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for controlling a semiconductor memory device such as a large-capacity dynamic random access memory.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional semiconductor memory device, and FIG. 4 is a time chart showing a conventional control method of the semiconductor device of FIG.

One block of the semiconductor memory device includes MOS type P-channel transistors Q ₁ and Q ₃ (hereinafter referred to as PTr Q ₁ and Q ₃ ); N-channel transistors Q ₀ and Q ₂ (hereinafter NTr Q ₀ and Q ₂ ). ), A bit line D, bit line level correcting capacitors C ₁ , C ₂ , a balancer including PTr Q ₆ , Q ₇ , Q ₈ , and NTr Q ₉ , Q ₁₀ , Q ₁₁ and Q ₁₂ are capacitors C ₃ , C ₄ ,
It is composed of C ₅ and C ₆ and a pair of memory cells. P
When Tr Q ₅ and NTr Q ₄ are on, the sense amplifier is activated. When the activation signal ▲ ▼ is at the logic level 0 (hereinafter referred to as “0”), PTr Q ₅ turns on and PTr Q raise the drain of _1, Q ₃ to the power supply voltage Vcc. Also, the activation signal S
When EG is at logic level 1 (hereinafter referred to as "1"), NTr Q ₄ turns on and pulls the sources of NTr Q ₀ , Q ₂ to ground. W
L ₀ , WL ₁ , WL ₂ , WL ₃ are word line signals. Activation signal ▲
▼ when the logic level "0", the bit line D, the voltage V ₀ the
Pre-charge and balance. Pull down signal ▲
▼ and ▲ ▼ are even-numbered word line signals WL, respectively.
₀ , WL ₂ selected cycle, odd-numbered word line signal W
In the cycle in which L ₁ and WL ₃ are selected, the logic level changes from logic level “1” to logic level “0”, the bit line level not connected to the memory cell is lowered from the voltage V ₀ , and the comparison voltage to the sense amplifier is reduced. The signal to give.

Next, the operation of the semiconductor memory device of FIG. 3 according to the conventional control method will be described with reference to FIG.

Activation signal PR is set to "1" balancer inactive at time t _1, the word line WL ₀ at time t ₂ is selected by simultaneously pull-down signal ▲ ▼ drop, the comparison voltage is applied to the sense amplifier. Time t ₃ or later, the activation signal ▲
▼ and ▲ ▼ become active, the sense amplifier is activated, and the voltage of the bit line D, is amplified. At time t _5, the word line signal after amplified bit line D, the potential is rewritten to the memory cell capacity is unselected reduction.
The sense amplifier at time t ₆ is deactivated, the bit line
D, is in a floating state of High or Low level. At time t _7, the balancer is activated, the bit line D, is reset to a level of the voltage V _0. Time t ₁ ~t ₇
Is one access cycle.

[Problems to be solved by the invention]

In the conventional method of controlling a semiconductor memory device described above, the word line is not selected while the sense amplifier is kept in the active state. Therefore, when a high-speed cycle operation is required, data is written to the memory cell (data restoration). ) There is a drawback that the data levels 1 and 0 are lower than the power supply level and higher than the ground level, respectively.

An object of the present invention is to provide a method for controlling a semiconductor memory device which does not cause the above-described disadvantage.

[Means for solving the problem]

A method for controlling a semiconductor memory device according to the present invention includes a memory cell group in which each memory cell has a capacitor element for charge storage;
A bit line group for supplying charges to the memory cells, a memory cell array unit including a sense amplifier group, and a word line for controlling connection between the memory cells and the bit lines;
A first sense enable signal for controlling the connection between the power supply for activating the sense amplifier and the sense amplifier, and a ground and a sense, each having a dummy word line group connected to each bit line via each correction capacitor; In a semiconductor memory device controlled by a second sense enable signal for controlling connection to an amplifier, after the second sense enable signal is changed from active to inactive, the selected word line and the sense amplifier are on the same side. , And then the potential of the selected word line is lowered to deselect it.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a time chart showing a first embodiment of a method for controlling a semiconductor memory device according to the present invention.

In this embodiment, the semiconductor memory device shown in FIG. 3 is controlled as shown in FIG. The operation between the times t ₁ and t ₃ is the same as that of the conventional example shown in FIG. When the bit line D, the amplification operation of the differential potential is completed at time t _4, lowering the activation signal SEG, the bit lines to a low level of floating. Pull-down signal at time t ₅ ▲
▼ was lowered to "0" to "1", through the capacitor C ₁ which acts as a pull-down capacity to below ground level by a couple of capacitor bit line of a low level, which has been a floating. At time t _6, and unselected the word line signal, it writes the level of ground level below the memory cell. Activating signal ▲ ▼ was deactivated at time t _7, bit line D, and are both floating state. At time t _8, the balancer is activated, the bit line D, is reset to the voltage V ₀ level. Between the time t ₁ ~t ₈ is one access cycle.

FIG. 2 is a time chart showing a second embodiment of the present invention.

This embodiment is different from the first embodiment in that the pull-down signal ▼ is kept at “1”, the voltage V ₀ is set lower than in the first embodiment, and the difference potential signal is increased. is there. There is no change in the temporal order of the deactivation of the sense amplifier and the deselection of the word line. In addition, this allows writing below the ground level to the memory cell (restoring).
Is the same as in the first embodiment.

In this embodiment, since only the bit line side connected to the accessed memory cell is pulled down (D or),
Only one pull-down signal needs to be controlled in one access cycle, and there is an advantage that the configuration of the control circuit is simplified.

〔The invention's effect〕

As described above, the present invention deactivates the sense amplifier before deselecting the word line, lowers the potential of the floating bit line via the pull-down capacitor, and then deselects the word line. Thereby, the level of writing (restoring) of data 0 to the memory cell can be made equal to or lower than the ground level without changing the configuration of the semiconductor memory device, the potential difference between data 1 and data 0 in the memory cell is expanded, As a result, the difference potential input to the sense amplifier for detecting data 1 and data 0 is expanded, and there is an effect that characteristics such as an operation margin of the entire semiconductor memory and a cell hold time can be remarkably improved.

Further, since the level correction capacitance is operated as a pull-down capacitance, the difference between the data 1 and 0 between the data 1 and 0 when the correction capacitance value fluctuates due to manufacturing fluctuations. There is also an effect that fluctuations in the operation margin can be absorbed without any occurrence.

[Brief description of the drawings]

FIG. 1 is a time chart showing a first embodiment of a method for controlling a semiconductor memory device of the present invention, FIG. 2 is a time chart showing a second embodiment of the present invention, and FIG. 3 is a conventional semiconductor memory device. FIG. 4 is a time chart showing a conventional control method of the semiconductor device of FIG. Q ₀ , Q ₂ , Q ₄ , Q ₉ , Q ₁₀ , Q ₁₁ , Q ₁₂ … N-channel MOS transistors (NTr), Q ₁ , Q ₃ , Q ₅ , Q ₆ , Q ₇ , Q ₈ … … P-channel MOS transistor (PTr), C ₁ , C ₂ … Pull down capacity, C ₃ , C ₄ , C ₅ , C ₆ … Memory cell capacity, ▲ ▼, ▲ ▼… Sense amplifier activation signal , ▲ ▼… Bit line balancer activation signal, V ₀ …… Bit line precharge voltage and counter electrode voltage of memory cell capacity, ▲ ▼, ▲ ▼ …… Pull down signal, WL ₀ , WL ₁ , WL ₂ , WL ₃ …… word line, D, …… bit line.

Claims (1)

(57) [Claims] A memory cell array section comprising: a memory cell group in which each memory cell has a charge storage capacitor; a bit line group for supplying charges to the memory cell; and a sense amplifier group. A power supply for activating the sense amplifier, including a word line for controlling connection between the memory cell and the bit line, and a dummy word line group connected to each bit line via each correction capacitor; In a semiconductor memory device controlled by a first sense enable signal for controlling connection with an amplifier and a second sense enable signal for controlling connection between a ground and a sense amplifier, the second sense enable signal is changed from active to non-active. After the activation, the potential of the dummy word line located on the same side with respect to the selected word line and the sense amplifier is lowered, and then the potential of the selected word line is reduced. A method for controlling a semiconductor memory device in which a position is lowered and is not selected.