JPS6258492A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute the stable action of an ambient circuit by activating simultaneously wholly the first sense amplifier by a clock for a pre-sense and activating the second sense amplifier only with the line selecting signal selected by the line address. CONSTITUTION:By an H level and a clock PSEN for the pre-sense, MOSFET- Q18 for activation is turned on, the electric potential of a node N is gradually decreased, the unbalance of the electric potential appearing at respective bit line pairs BLj and BLj is increased by the first sense amplifier SA1j. When the electric potential difference of the bit line pairs BLj and the inverse of BLj is made to some extent, the line selecting signal line selected by the row address, for example, CSL1 is made into the voltage level higher than the threshold voltage and the voltage level lower than an 'H' level, and thereby Q15 is switched on, the second sense amplifier of the bit line pair to be selected is activated and the selected bit line pair only is mainly sensed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that suppresses peak current during sensing operation and enables highly reliable operation.

[Technical background of the invention and its problems]

Recently, various types of rewritable semiconductor memory cells have been put into practical use. Among these, one MO as shown in Figure 3
Dynamic RAM (dRAM), which uses a memory cell consisting of 8FETs 31 and one MO8 capacitor 32, is the most highly integrated and is common. In this memory cell, the gate of the MO8FET 31 is connected to the column address line C (word line) WL, the drain is connected to the row address line C (bit line) BL, and the stored data is stored in the MO8 capacitor 32 in the form of charge. It is something.

When configuring dRAM using this memory cell, the fourth
A memory cell array is configured as shown in the figure.

That is, a plurality of word lines WLi that selectively drive memory cells and a plurality of bit lines BLj that transfer data between the memory cells are arranged to intersect with each other. Memory cells are connected. Word line W
A pair of dummy word lines DWL, DWL are arranged in parallel with Li, and dummy cells are connected to the intersections of these and each bit line BLj. This configuration employs a method in which paired bit lines BLj and BLj are arranged in a folded manner and a sense amplifier SAj is provided for each bit line pair. The sense amplifier SAj has two activation MO8s connected in parallel.
FET-Qss is grounded via Q56. Further, the bit lines BLj, BLj are connected to input/output lines I10. through transfer gate MO8FBT-Q53, Q54. Connected to I10.

The dRAM in FIG. 4 operates as follows by applying each internal clock as shown in FIG. First, a pair of bit lines BLj sandwiching a sense amplifier SAj.
, BLj becomes Mo 8 F Er T -Q43. when the precharge BLP goes to "H" level (for example, higher than Vcc + Vth). Q44 is turned on and all are precharged to Vcc. The node N of the sense amplifier 8Aj is precharged to Vcc. At the same time, the dummy cell write clock DCP becomes @H.
” level (e.g. Vcc), the MOS
F]13T-Qso, Q is turned on, and @L" level (for example, Vss) is written to the nodes of all dummy cells. Here, the dummy cell MOS capacitors C15, C
The capacitance of 16,... is the M08 capacitor C of the memory cell.
The size is 1/2 that of 1l, C12, .

Next, the clock BLP for precharging the bit line and the clock DCP for writing the ``L'' level into the dummy cells are both lowered to the ``L'' level to set the bit line to 70-ting. After that, when active operation 5 is started, one word line, for example, WLl, becomes 1H" level (above Vcc+Vth), and at the same time, the dummy word line DwII becomes "H" level, so that MO8F]13T-Q45. Q51 is turned on.As a result, the information of the MOS capacitor C11 appears in the bit aiBLs, and the information of the MOS capacitor C16 appears in the bit BLt, and the pair of pits 44
A potential difference is generated between BLI and BLI. This becomes the input to the sense amplifier SAl.

Sense amplifier 8A1 is activated in two stages. First, MO8FET for activation with small mutual conductance
- The unbalanced pits 5BLt, BLx are moved by setting Qss to the internal clock P8F, N to "H" level and lowering the level of node N.
The amplification of the potential difference between the two starts. Bit, 1BLt, B
When there is a certain potential difference between Ll and Ll, the activation MO8F FiT-Qs with large mutual conductance
s All internal po y ri M8 EN wo” f(”
The @H level side of the Q bit line is driven by the trap to keep the ``H'' level side of BLl and BLt near Vcc, and drops the ``L'' level side to Vss.
Amplifies the potential difference in the sensing operation. In a normal dRAM, more than 1000 sense amplifiers operate. However, among these bit lines, one pair of bit lines is selected by the row selection signal C3LjK selected by the row address, and the remaining bit line pairs are not selected. For example, the row selection signal C3ll
is selected, only the information on the bit line pair BLI, BLI is transferred to the transfer gate MQ8FET-Qss.
, Q54 to the input/output line I10゜Ilo As described above, in the conventional sense method, all 1 sense amplifiers are driven at the same time, so the bit lines connected to all sense amplifiers are discharged at the same time. be exposed. If this discharge is carried out in a short period of time, the peak current increases, causing a rise in the ground line potential Vss, which causes noise and adversely affects the operation of peripheral circuits.

[Purpose of the invention]

In view of the above points, the present invention provides a highly reliable semiconductor memory device that suppresses the peak current associated with the operation of a sense amplifier, thereby reducing noise caused by fluctuations in the power supply line and preventing adverse effects on the operation of peripheral circuits. The purpose is to provide

[Summary of the invention]

In the present invention, two sense amplifiers, a first sense amplifier and a second sense amplifier, are provided for a pair of bit lines. The first sense amplifiers are all activated at the same time by the pre-sense clock, and the second sense amplifiers are activated by the row selection signal (data on the selected bit line and the input/output line connected to the peripheral circuit) selected by the row address. signal that controls transfer).

〔Effect of the invention〕

According to the present invention, since only the first sense amplifier for pre-sense is operated for unselected bit lines, it is possible to suppress the peak current during the sensing operation and reduce the potential fluctuation of the power supply line. This enables stable operation of peripheral circuits and provides a highly reliable dRAM.

In addition, unselected bit line pairs are discharged slowly only by the first sense amplifier for pre-sense, so the bit line pairs are
The level drop on the H'' level side can be suppressed to a lower level than before.

Therefore, a complicated circuit such as an active pull-up circuit is not required as a circuit to recover from a drop in the ``H'' level of the bit line, and the bit line is pulled up using only capacitance coupling. The circuit can be simplified.

Furthermore, since the second sense amplifier is activated by the row selection signal, there is no need to provide a separate circuit to drive the second sense amplifier, and there is no need to increase the number of separate signal wires within the sense amplifier. This makes it possible to simplify the system configuration and prevent an increase in chip size.

[Embodiments of the invention]

The present invention will be explained in detail below. FIG. 1 shows the configuration of one embodiment. The configuration of the memory cell array part is the same as the conventional one, but the difference from the conventional one is that the first sense amplifier 5A1j and the second sense amplifier 5A are provided for each bit line pair BLj, BLj.
2j is provided, the second sense amplifier 5A2
An activation MO8FET-Q1s driven by a row selection signal C3Lj is connected to j. As for the first sense 7y transistor 5A1j, one MO8FET-Q18 for activation driven by P8EN for pre-sensing is conventionally connected in common. MO for activation of second sense amplifier 8A2j for main sense
The mutual conductance of 8FET-Q15 is the activation MO8FE on the first sense amplifier 5Alj side for pre-sense.
It shall be larger than that of T-Q18.

The sensing of dR and AM configured in this manner will be described next with reference to the signal waveforms shown in FIG.

First, all bit lines are precharged to Vcc by the precharging clock BLP going to 'H' level. At the same time, the clock DCP goes to 'H' level, causing each dummy cell to ' L” level is written. These clocks BLP.

DCP is set to 1L" level before entering active operation. And, before entering active operation, it is set to [-" level. Then, active operation is entered, one word line, for example, WLl, is selected, and information in the memory cells connected to it is transferred to the bit line.

Up to this point, the operation is the same as before.

Thereafter, the pre-sense clock PSEN goes to the "H" level, the activation MO8FET-Qss is turned on, and the potential of the node N gradually decreases, causing each bit line pair BLj.

The potential unbalance appearing at BLj is increased by the first sense amplifier 5A1jK. This pre-sense operation is relatively slow because the mutual conductance of MOSFET-Qlg is small. As shown in FIG. 2, this pre-sensing causes bit line pair BLj, B
, the "L" level side of the mouth decreases, but the "'H" level side remains almost unchanged.

Then, when the potential difference between the bit line pair BLj and BLj reaches a certain level, the row selection signal line selected by the row address, for example, C3L1, is set to i[<@H
By doing so, Qls is switched on, the second sense amplifier of the bit line pair to be selected is activated, and only the selected bit line pair is main sensed.Here, The reason why the level of C3L1 is set to a voltage level higher than the threshold voltage of Qls (lower than the @H" level) is to switch off Q16 or Q17 or to operate the pentode. This is to prevent the sense amplifier from malfunctioning due to the influence of the input/output lines I10 and Ilo.

In other words, Q16. This is to use Q17 as a transistor. When the main sense is completed, set the level of C3L1 to the "H" level or higher (Vcc + 'Vth or higher) to Q16. Q17 is operated as a triode and the signal on the selected bit line is transferred to input/output lines I10 and Ilo.

As described above, according to this embodiment, the first . The first sense amplifiers among the second sense amplifiers are all driven at the same time to perform pre-sense, and the second
The sense amplifier is selectively driven to perform main sensing. Therefore, the peak current value during the sensing operation is suppressed, and malfunction of the peripheral circuits due to the rise of the power line potential Vcc due to the peak current is prevented, thereby improving the reliability of the d-AM. Furthermore, since the second sense amplifier is activated by a row selection signal, the configuration of signals within the sense amplifier can be simplified.

In this embodiment, the level of C3L1 is set to a voltage level lower than the ``H'' level during main sensing, but the voltage level may be set to any value as long as the sense amplifier does not malfunction.

The present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of dRAM according to an embodiment of the present invention, FIG. 2 is a diagram for explaining its sensing operation, FIG. 3 is a diagram showing the FidRAM memory cell configuration, and FIG. 4 is a diagram showing the conventional FidRAM memory cell configuration. FIG. 5 is a diagram showing the configuration of dR,AM and is a diagram for explaining its sensing operation.
2, WL3 mountains)...word line, DWL, DWL...
・Dummy word line, BLj (BLI, drunk, BL2.
Robbery, BL3, drunkenness...) Bit line, SA 1j (SAII, 5A12, 5A13. ・
...)...Fourth sense amplifier, agent patent attorney
Nori Chika Ken Yudo Takehana Kikuo BPmu PSE~ Node NV Z ci 3'2'

Claims (3)

[Claims] (1) Multiple memory cells arranged in a matrix on a semiconductor substrate, multiple word lines that selectively drive these memory cells, and multiple pairs of bit lines that exchange information with the memory cells. , in a semiconductor memory device integrated with a plurality of sense amplifiers for detecting a potential difference between each pair of bit lines, first and second sense amplifiers are provided for each bit line pair as the sense amplifiers, and a first sense amplifier is provided for each bit line pair; A plurality of sense amplifiers are activated at the same time, and the second sense amplifier is activated only by a row selection signal selected by a row address that controls the connection between a selected bit line and an input/output line connected to a peripheral circuit. A semiconductor memory device characterized by: (2) The potential level of the row selection signal is different when activating the second sense amplifier and when transferring the data of the selected bit line to the input/output line connected to the peripheral circuit. A semiconductor memory device according to claim 1, characterized in that: (3) When the potential level of the row selection signal activates the second sense amplifier, the transistor that transfers data from the bit line to the input/output line operates as a pentode or switches off. 2. The semiconductor memory device according to claim 1, wherein the level is such that when data is transferred to the input/output line, each of the transfer transistors operates as a triode.