JP3335410B2 - Serial access memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed F using DRAM (Dynamic Random Access Memory) cells.
The present invention relates to a serial access memory used for an IFO (First In First Out) memory, a multiport RAM, and the like.

[0002]

2. Description of the Related Art Conventionally, a serial access memory of this type has a serial access memory section (SAM section) comprising a set of sense amplifiers and latch circuits for one bit line pair as shown in Japanese Patent Application Laid-Open No. 3-25791. It is configured. In a conventional serial access memory, first, a potential difference ΔV generated between a pair of bit lines due to a charge of a memory cell selected by a word line is amplified by a sense amplifier connected to the pair of bit lines. Then, when a sufficient potential difference is applied, the switch of the transfer gate is turned on and the data is stored in the SAM
Transfer to department. After data is transferred to the SAM unit, the word lines, transfer gates, and sense amplifiers are reset. S
Since the data of the AM unit accesses only the data of the bit specified by the serum decoder or the pointer, the operation of the word line is unnecessary, and the operation can be performed at high speed.

[0003]

In the conventional circuit configuration, one set of a sense amplifier and a SAM is required for each bit line pair. The greatest advantage of the DRAM is that since the memory cell has a structure of one transistor and one capacitor, the cell size per bit can be small, and as a result, the cost is low. The size of the memory cell is steadily miniaturized with the development of process technology. However, in the conventional circuit configuration, as the size of the memory cell becomes smaller, the bit line pitch becomes smaller, and it becomes difficult to lay out a pair of sense amplifiers and SAM units between the reduced pitch. There is a point.

The present invention provides a serial access memory having a circuit configuration which does not hinder the miniaturization of memory cells by relaxing the arrangement pitch of sense amplifiers and SAMs in order to solve the above-mentioned problems. Aim.

[0005]

In order to achieve the above object, in a serial access memory according to the present invention, a plurality of pairs of bit lines to which a plurality of memory cells are connected are connected to a sense amplifier via a switch. And any one of the bit line pairs is controlled in sequence.

[0006]

A switch connects a sense amplifier and a plurality of bit line pairs connected to the sense amplifier one by one in a cycle in a time-division manner.

[0007]

FIG. 1 is a circuit diagram of an embodiment of the present invention. WL
1, WL2 is a word line, BL1D, BL1D *, BL2
D, BL2D *, BL1U, BL1U *, BL2U, B
L2U * is a bit line, TG1 and TG2 are bit lines BL1
D: Control nodes of switches 111 to 117 for connecting BL2U * to sense amplifiers 121 and 123. When this node TG1 goes to "H" level, switch 11
When switches 3 and 117 are turned on and node TG2 is set at "H" level, switches 111 and 115 are turned on. SAN, SAP
* Is an operation signal node of sense amplifiers 121 and 123, E
Q represents sense amplifiers 121 and 123 and lines BL1D.
2U * equalizing signal node, HVcc is bit line B
The nodes connected to the precharge circuits 131 and 133 for L1D to BL2U * and the sense amplifiers 121 and 123 supply a precharge level. TG3 is a control node of the switches 141 and 143 connecting the sense amplifiers 121 and 123 and the SAM units 151 and 153,
When this node becomes “H”, the switches 141 and 143 are turned on, and when this node becomes “L”, the switches 141 and 143 are turned off.
Becomes CφU and CφD are column address selection lines, which are connected to switches 161 and 163. Switch 1
When 61 and 163 are turned on, the selected SAM unit 15
1,153 connected to nodes SAMD, SAMD *,
SAMU, SAMU * are connected to data buses SDB, SDB *.

The memory cells 101, 102,..., 108 are constituted by, for example, an NMOS transistor 101a and a capacitor 101b, taking the memory cell 101 as an example. The gate of the NMOS transistor 101a is connected to the word line WL1, and the source and the drain are connected to the bit line BL.
2D * and one electrode of the capacitor 101b. The other electrode of capacitor 101b is connected to potential source VcP.

Switches 111-117, 141, 14
3, 161 and 163 are composed of two NMOS transistors. Taking the switch 111 as an example, the NMO
The gates of S transistors 111a and 111b are commonly connected to control node TG2, and their sources / drains are connected to bit lines BL2D and BL2D * and sense amplifier 12 respectively.
1 and connected to

The sense amplifiers 121 and 123 each have 2
One NMOS transistor and two PMOS transistors. For example, the gates of the NMOS transistor 121a and the PMOS transistor 121c of the sense amplifier 121 are commonly used for the NMOS transistor 121b and the PM transistor 121c.
Connected to the drain of OS transistor 121d. The gates of the NMOS transistor 121b and the PMOS transistor 121d are commonly connected to the drains of the NMOS transistor 121a and the PMOS transistor 121c. NMOS transistors 121a, 121
The source of b is connected to the ground potential GND via the NMOS transistor 171. The gate of the NMOS transistor 171 is connected to the sense amplifier operation signal node SAN. Also, the PMOS transistor 121
The sources of c and 121d are connected to the power supply potential Vdd via the PMOS transistor 173. The gate of the PMOS transistor 173 is connected to the sense amplifier operation signal node SA.
Connected to P *. Note that the NMOS transistor 175
Is connected between the common connection line of the source of the NMOS transistor and the common connection line of the source of the PMOS transistor of the sense amplifier 121, and has its gate connected to the equalize signal node EQ.

The precharge circuits 131 and 133 are each composed of three NMOS transistors. The NMOS transistors 131a, 1 of the precharge circuit 131
Gates of 31b and 131c are commonly connected to an equalize signal node EQ. NMOS transistors 131a,
The drain of 131b is commonly connected to the node HVcc, and their sources are connected to the source and drain of the NMOS transistor 131c, respectively.

The SAM units 151 and 153 are the sense amplifiers 1
Each of the latch circuits 21 and 123 has the same circuit configuration. The difference between the SAM unit 151 and the sense amplifier 121 is that the sources of the NMOS transistors 151c and 151d are directly connected to the ground potential GND, and the PMOS transistor 1
The point is that the sources of 51a and 151b are directly connected to the power supply potential.

The bit lines BL1D and BL2D, BL
1D * and BL2D * are commonly connected via switches 111 and 113, and bit lines BL1U and BL2U and BL1
U * and BL2U * are commonly connected via switches 115 and 117.

FIG. 2 shows operation waveforms at the time of read transfer according to the embodiment of the present invention. The code of each node of the bit line, word line, selection line, etc. is used as it is as the code of the signal there. When the read transfer cycle starts from the reset state,
First equalize signal EQ is the equalization becomes "L" is released (t _1). Next, when the selected word line WL1 rises (t ₂ ), information of the memory cells 101, 103, 105, 107 connected to the word line WL1 is output to the bit lines BL1D *, BL2D *, BL1U *, BL2U *. , A small potential difference ΔV is generated between the bit line pair. The switch control signal TG2 coincides with the rising of the word line WL1.
Falls, the level of the bit lines BL1D and BL1D * is first output to the sense amplifier 121. Then, the sense amplifier operation signal SAN changes to “H” and the sense amplifier operation signal SAP * changes to “L” (t ₃ ), and the sense amplifier 121 operates to amplify the potential difference on the bit lines BL1D and BL1D *. After the completion of the amplification, the switch control signal TG3 rises (t ₄ ), and the data of the sense amplifier 121 is transferred to the SAM unit 151. Next, bit line B
If the data of L2D and BL2D * is not amplified, the data will be destroyed, so the rewrite operation is performed. The switch control signals TG3 and TG1 are lowered (t ₅ ), and the SAM 1
The sense amplifier is disconnected from the bit line 51 and the bit line pair BL1D, BL1D *, and the equalizing signal EQ rises (t ₆ ).
The sense amplifier 121 is equalized once. After lowering the equalizing signal EQ again (t ₇ ), the switch control signal TG2 rises to take the potential difference between the pair of bit lines BL2D and BL2D * into the sense amplifier 121, and operate the sense amplifier 121 again to amplify the potential difference. Let it. As a result, the data on the bit lines BL2D and BL2D * is rewritten. When the rewrite is completed, the word line WL1 falls, and all other signals are reset to the initial state, thereby completing the transfer cycle.

In this embodiment, a pair of sense amplifiers and SAMs are used in common for two bit line pairs. However, it is possible to use a common sense amplifier and SAM for more bit line pairs.

[0016]

As described above in detail, according to the present invention, even if the miniaturization advances and the arrangement pitch of the memory cells becomes smaller than the size of the sense amplifier and the SAM, it is necessary to increase the arrangement pitch of the memory cells. Absent. Sense amplifier,
By reducing the arrangement pitch of the SAMs, a process margin can be increased and an improvement in yield can be expected. Since the sensing operation is performed twice or more in one transfer cycle, the peak noise accompanying the sensing operation can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a serial access memory according to an embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

[Explanation of symbols]

WL1, WL2 Word lines BL1D, BL1D *, BL2D, BL2D *, BL1
U, BL1U *, BL2U, BL2U * Bit lines TG1, TG2 Switch control nodes 111, 113, 115, 117 Switches 121, 123 Sense amplifier

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-76195 (JP, A) JP-A-1-184693 (JP, A) JP-A-4-2055781 (JP, A) JP-A-63- 249998 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/40-11/4099

Claims (2)

(57) [Claims] A plurality of memory cells constituting one memory cell array; a plurality of bit line pairs to which the memory cells are connected; a switch provided at one end of the bit line pair; A sub-bit line pair connected to the bit line pair; a sense amplifier connected to the sub-bit line pair for amplifying a potential difference generated between the sub-bit line pairs; and a sense amplifier connected to the sub-bit line and storing the amplified potential difference. And a data bus connected to the latch circuit and outputting the stored potential difference, wherein the pitch of the sub-bit line pairs is larger than the pitch of the bit line pairs, An amplifier is connected to the plurality of bit line pairs, and is connected between the plurality of bit line pairs and the sense amplifier. And that the switch is a serial access memory, characterized by the sequentially connected one pair of the bit line pair of the sense amplifier. 2. The sub-bit line pair further comprises a sub-bit
2. The series according to claim 1, wherein a line equalizing circuit is connected.
Al access memory.