JPH1139863A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can reduce influence of delay time due to change of row address during the page mode and can also realize high speed access. SOLUTION: A data holding buffer 9 for temporarily holding the readout data of a sense amplifier 7 is provided between the sense amplifier circuit 7 and an input/output buffer 8. After the readout data of the sense amplifier circuit 7 is determined during the page mode reading operation, the data is transferred to the data holding buffer 9 and it is then outputted to an external data bus via the input/output buffer 8 by the data holding buffer 9. After data is transferred to the data holding buffer 9 from the sense amplifier circuit 7, a new word line is selected because of change of row address and the word line and bit line are reset to start the next read cycle. As a result, the memory access rate can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a dynamic random access memory (hereinafter, referred to as DRAM) that can be accessed at high speed.

[0002]

2. Description of the Related Art FIG. 5 shows a configuration of a general DRAM. As shown, the DRAM comprises a row address buffer 1, a row decoder 2, a memory cell array 3, a control circuit 4, a column decoder 5, a column address buffer 6, a sense amplifier circuit 7, and an input / output buffer (I / O buffer) 8. It is configured.

The row address buffer 1 holds the input row addresses AR ₀ , AR ₁ , AR ₂ ,..., ARn and outputs them to the row decoder 2. The row decoder 2 selects a word line specified by a row address from a plurality of word lines WL, and activates the selected word line.

The column address buffer 5 holds the input column addresses AC ₀ , AC ₁ , AC ₂ ,..., ACn and outputs them to the column decoder 6. The column decoder 6 generates a column selection signal YS for selecting a bit line specified by a column address from the plurality of bit lines BL of the memory cell array, and outputs the column selection signal YS to the sense amplifier circuit 7.

[0005] In the memory cell array 3, a plurality of word lines WL and a plurality of bit lines BL are wired so as to cross each other, and a plurality of memory cells are arranged in a matrix at respective intersections of the word lines and the bit lines.

At the time of memory access, row address A
The memory cells connected to the word line specified by R ₀ , AR ₁ , AR ₂ ,..., ARn are selected. A bit line is selected by the column addresses AC ₀ , AC ₁ , AC ₂ ,..., ACn, arranged at the intersection of the selected word line and bit line, and connected to the selected word line and bit line. Writing or reading is performed on the cell. The above-described memory accesses are all performed under the control of the control circuit 4. The control circuit 4 includes a control signal from the outside, for example, a row address selection signal RASB (Row Address Strobe) and a column address selection signal CASB (Column Address Strobe).
In accordance with Strobe), a control signal is output to each address buffer and decoder to control the operation of those circuits.

Various methods have been proposed for realizing high-speed data access in a conventional DRAM. Page mode access is one of them. The page mode access has a feature that the column address can be specified for each bit while the row address is kept constant. That is, when a column address is specified while the row address remains constant, the specified column is successively accessed by a plurality of bits by the sense amplifier.

FIG. 6 is a waveform chart showing signals at the time of page mode access. Hereinafter, an operation at the time of page mode access will be described with reference to FIG. After the row address is determined, the row address selection signal RASB falls, and in response to this, the word line specified by the row address is selected and activated by the row decoder 2.

After a predetermined time has passed after the row address is determined, the column address is determined, and the column address selection signal CASB falls. Note that the delay time from the falling edge of the row address selection signal RASB to the falling edge of the column address selection signal CASB is called RAS-CAS delay time, and is denoted by t _RCD in FIG.

After the column address is determined, a column selection signal YS is generated by the column decoder 5. In response to this, a predetermined sense amplifier is operated in the sense amplifier circuit 7, and the data stored in the memory cell corresponding thereto is operated. Is amplified by the sense amplifier, and further output to the outside via the input / output buffer 8.

As shown, a column address is specified for each bit during a page mode operation while a row address is kept constant. That is, the column address is set for each bit while the row address is kept at the low level, and after each column address is determined, the column address selection signal CASB falls, and in response to this, the designated bit is set by the sense amplifier. The line data is read.

In FIG. 6, a 4-bit column address is sequentially set with respect to the set row address, and 4-bit data is sequentially read out. Note that the actual DRAM is not limited to this, and more column addresses can be set for one row address. For example, for one word line, 8
Bits or 16 bits of data can be read in sequence.

As described above, by reading in the page mode, data for a plurality of bits can be read out by setting a column address a plurality of times for one row address setting, thereby realizing high-speed memory access. it can.

[0014]

In the conventional DRAM described above, when memory access is performed in a page mode, the word line and bit are reset and the newly designated row address is changed in accordance with the change of the row address. Since it is necessary to wait for the time required for the setup, there is a disadvantage that the access speed is reduced by changing the row address.

For example, as shown in FIG. 6, a time t _RCD is a data preparation time for selecting a new word line and amplifying a small signal of a memory cell.
_RP is the bit and word line reset time. The above-described delay due to the time t _RCD and the time t _RP causes a reduction in the access speed in the page mode.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the influence of a delay time due to a change in a row address in a page mode and realize a high-speed access to a semiconductor memory device, for example, , A DRAM.

[0017]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a plurality of memory cells arranged in a matrix, memory cells in the same row connected to the same word line, and the same column. Are connected to the same bit line, the word line selected at the time of memory access and the memory cell connected to the bit line are accessed, and the same word line is selected while the same word line is selected. A semiconductor memory device having an operation mode for sequentially accessing a plurality of connected memory cells, comprising: a sense amplifier connected to each of the bit lines for amplifying data transferred to the bit lines; An input / output buffer for outputting data to the outside or inputting write data from the outside to the inside, and a connection between the sense amplifier and the input / output buffer , And a data holding means for holding the read data of the sense amplifier, and outputs the held data to the output buffer.

In the semiconductor memory device of the present invention, a plurality of memory cells are arranged in a matrix, memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line, The memory cell connected to the selected word line and bit line at the time of memory access is accessed, and while the same word line is selected, a plurality of memory cells connected to the word line are accessed. An operation mode in which sequential access is performed, for example, a semiconductor memory device operable in a page mode. The semiconductor memory device is connected to each of the bit lines and amplifies data transferred to the bit lines. An input / output buffer for outputting or externally inputting write data, and connected between the sense amplifier and the input / output buffer; Data holding means for holding read data of the sense amplifier and outputting the held data to the input / output buffer, and connected between the data holding means and the sense amplifier, and an on / off state is controlled according to a control signal. And a transfer gate.

Further, in the present invention, preferably, when reading is performed in the above operation mode, for example, in the page mode,
The transfer gate is held in an ON state after the read data of the sense amplifier is determined, and after transferring the read data of the sense amplifier to the data holding unit,
It is kept off.

According to the present invention, in a semiconductor memory device, for example, a DRAM, data holding means for temporarily holding read data of the sense amplifier, for example, a latch circuit is provided between a sense amplifier and an input / output buffer; When reading is performed in the page mode, data read by the sense amplifier is transferred to the data holding unit and held by the data holding unit. The data holding unit outputs the held data to the outside via the input / output buffer. Therefore, after the read data of the sense amplifier is transferred to the data holding means, the sense amplifier and the data holding means can operate independently, and the DRAM can prepare for reading data for the next row address inside the DRAM. , And the effect of delay time caused by resetting of word lines and bit lines can be suppressed, and the access speed in the page mode can be improved.

[0021]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention.
FIG. 2 is a configuration diagram showing an entire configuration of the first embodiment. As shown in the figure, the DRAM of this embodiment includes a row address buffer 1, a row decoder 2, a memory cell array 3, a control circuit 4, a column decoder 5, a column address buffer 6, a sense amplifier circuit 7, an input / output buffer (I / O buffer). A buffer) 8 and a data temporary holding buffer (hereinafter, simply referred to as a data holding buffer) 9.

In the memory cell array 3, a plurality of word lines WL and a plurality of bit lines BL are wired so as to cross each other, and a plurality of memory cells are arranged in a matrix at respective intersections of the word lines and the bit lines. The memory cell is, for example,
A DRAM memory cell having a one-transistor, one-capacitor configuration, in which a gate of a selection transistor is connected to a word line, one diffusion layer is connected to a bit line, and the other diffusion layer is connected to a capacitor. . Each word line is connected to a row decoder 2, and each bit line is connected to a sense amplifier circuit 7 via a column selection circuit (not shown). The column selection circuit is controlled by a column selection signal YS from the column decoder 6.

The row address buffer 1 holds the input row addresses AR ₀ , AR ₁ , AR ₂ ,..., ARn and outputs the row addresses to the row decoder 2. The row decoder 2 selects a word line specified by a row address from a plurality of word lines WL, and activates the selected word line.
For example, a high-level voltage Vp is applied to a selected word line, and the voltage Vp is set to a voltage level sufficient to set a selection transistor in a memory cell connected to the word line to a conductive state. ing.

The column address buffer 5 holds the input column addresses AC ₀ , AC ₁ , AC ₂ ,..., ACn and outputs them to the column decoder 6. The column decoder 6 generates a column selection signal YS for selecting a bit line specified by a column address from the plurality of bit lines BL of the memory cell array, and outputs the column selection signal YS to a column selection circuit and a sense amplifier circuit 7 (not shown).

The control circuit 4 controls the row address buffer 1, the row decoder 2, the column address buffer 5, and the column decoder 6 in response to external control signals, for example, a row address selection signal RASB and a column address selection signal CASB. And outputs a control signal to control the operation of these circuits. Further, the control circuit inputs a control signal to the sense amplifier circuit 7 and the data holding buffer 9, and controls the operation of these circuits during a read operation.

The input / output buffer 8 receives external control signals, for example, an output enable signal OEB and a write enable signal WEB, and responds to these control signals to read data D ₀ , _{D 1, D 2, ...,} Dm was transferred to the data bus, and inputs the write data transferred from the data bus during the write to the memory cell array.

At the time of memory access, row address A
The memory cells connected to the word line specified by R ₀ , AR ₁ , AR ₂ ,..., ARn are selected. A bit line is selected by the column addresses AC ₀ , AC ₁ , AC ₂ ,..., ACn, arranged at the intersection of the selected word line and bit line, and connected to the selected word line and bit line. Writing or reading is performed on the cell.

The semiconductor memory device of this embodiment, that is, DR
In AM, to realize high-speed memory access,
Reading or writing is performed in a page mode method. FIG. 2 shows the waveforms of the row address selection signal RASB, column address selection signal CASB, row address, and column address during the page mode operation, respectively. Hereinafter, with reference to FIG. 1 and FIG. 2, the operation in the case where the memory access is performed in the page mode method will be described, and the features of the present invention will be more apparent.

As shown in FIG. 1, the DRAM of this embodiment
In the example, a data holding buffer is provided between the sense amplifier circuit 7 and the input / output buffer 8. At the time of reading, the data holding buffer temporarily holds the read data of the sense amplifier. Then, the held data is output to, for example, a data bus via the input / output buffer. Therefore, after the read data of the sense amplifier circuit 7 is transferred to the data holding buffer 9, the sense amplifier circuit 7 can prepare for the next data read. When reading is performed in the page mode, data read from the sense amplifier circuit 7 is stored in the data holding buffer 9.
, A new row address can be fetched, a new word line can be selected, and a word line and a bit line can be reset. For this reason, in the conventional DRAM, the row address update operation that affects the read speed in the page mode is immediately executed after data transfer from the sense amplifier circuit 7 to the data holding buffer 9 in the present embodiment, and the row address is updated. Time delay due to updating can be suppressed to a minimum, and the access speed of the page mode method can be improved.

Specifically, as shown in the waveform diagram of FIG. 2, in the portion indicated by the arrow a, the access cycle of the current page mode (hereinafter, this cycle) starts, and after the current row address is determined, Row address selection signal RAS
B falls. In response, the word line is selected and activated according to the current row address. As shown in the figure, the last one bit of the previous cycle is read at the same time when the current row address is set. Then, after reading, the data of the sense amplifier circuit 7 is transferred to the data holding buffer, and the data holding buffer outputs the data to the data bus. After the data transfer to the data holding buffer, the sense amplifier circuit 7 immediately starts the data read operation of this cycle.

After the column address is determined, the column address selection signal CASB falls, and the data of the bit line selected in response is read out to the sense amplifier circuit 7. After the data of the selected bit line is determined, it is transferred to the data holding buffer 9. Then, the column address corresponding to the next one bit is determined, the column address selection signal CASB falls accordingly, and the data of the next one bit is read out in the same manner as the above-described operation.

Then, the read operation of this cycle is performed at the portion indicated by arrow b in the precharge time t _RP of the row address in the next cycle. Then, although not shown, after the time t _RP , the final reading of this cycle is performed.

As shown in FIG. 6, in the present embodiment, when memory access is performed in the page mode,
With the change of the row address, at the time t _RCD required for selecting a new word line or the like, the last data read of the previous cycle is performed. Also, during the precharge time t _RP of the row address in the next cycle, data reading in this cycle is performed.

FIG. 3 shows a part of the DRAM of this embodiment.
That is, the sense amplifier circuit 7 and the data holding buffer 9
FIG. 3 is a circuit diagram showing a detailed configuration of FIG. As shown, a transfer gate 10 is provided between the sense amplifier circuit 7 and the data holding buffer 9.

The DRAM of this embodiment has, for example, a folded bit line (Folded Bit Line) structure, and a pair of bit lines BLi, BLBi (i = 1, 2) which are set to invert levels at the time of access. 2, 3...), A plurality of pairs of bit line pairs are provided.

FIG. 3 shows, as an example, three pairs of bit lines BL0, BLB0, BL1, BLB1, BL2, BLB.
Only 2 is shown. As shown, sense amplifiers SA0 and SA each including a flip-flop circuit are provided for each bit line pair.
1 and SA2 are connected. Sense amplifier S
A0, SA1, and SA2 are each composed of two pMOS transistors and two nMOS transistors. Here, the configuration of the sense amplifier SA0 will be described as an example.

The sense amplifier SA0 comprises nMOS transistors N1 and N2 and pMOS transistors P1 and P2. The gate of the nMOS transistor N1 is connected to the bit line BL0, the source is connected to the low-level drive voltage supply line SAL, and the drain is the bit line B
Connected to LB0. The gate of the nMOS transistor N2 is connected to the bit line BLB0, the source is connected to the low-level drive voltage supply line SAL, and the drain is connected to the bit line BL0. The gate of the pMOS transistor P1 is connected to the bit line BL0, the source is connected to the high-level drive voltage supply line SAH, and the drain is connected to the bit line BLB0. The gate of the pMOS transistor P2 is connected to the bit line BLB0,
The source is connected to the high-level drive voltage supply line SAH,
The drain is connected to the bit line BL0.

The data holding buffer 9 has a plurality of buffers BUF0, BUF0,
It is composed of BUF1 and BUF2. Here, the configuration of the buffer BUF0 will be described as an example.

The buffer BUF0 includes nMOS transistors NT1 and NT2 and pMOS transistors PT1 and PT2.
2. nMOS transistor NT1
Is connected to the bit line SBL0, the source is connected to the low-level drive voltage supply line BFL, and the drain is connected to the bit line SBLB0. The gate of the nMOS transistor NT2 is connected to the bit line SBLB0, the source is connected to the low-level drive voltage supply line BFL, and the drain is connected to the bit line SBL0. p
The gate of the MOS transistor PT1 is connected to the bit line SBL
0, and the source is a high-level drive voltage supply line BF
H, and the drain is connected to the bit line SBLB0. The gate of the pMOS transistor PT2 is connected to the bit line SBLB0, the source is connected to the high-level drive voltage supply line BFH, and the drain is the bit line SB.
Connected to L0.

The transfer gate 10 includes a plurality of transistors T
R0, TRB0, TR1, TRB1, TR2, TRB2
It consists of. These transistors are composed of, for example, nMOS transistors, the gates are commonly connected to a transfer control signal line CK0, and the diffusion layers are bit lines BLi and BLBi on the sense amplifier circuit side and bit line SBLi on the data holding buffer side, respectively. , SBLi. For example, one diffusion layer of the transistor TR0 is connected to the bit line BL0, and the other diffusion layer is connected to the bit line SBL0. One diffusion layer of transistor TRB0 is connected to bit line BLB0, and the other diffusion layer is connected to bit line SBLB0.

The transfer control signal is input to the transfer control signal line CK0 by, for example, the control circuit 4 shown in FIG. Further, each bit line SBL of the data holding buffer 9 is
0, SBLB0, SBL1, SBLB1, SBL2, S
The BLB 2 is connected to, for example, a data bus via the input / output buffer 8 shown in FIG.

Hereinafter, the sense amplifier circuit 7 and the transfer gate 1
0 and the operation of the data holding buffer 9 will be described. When the sense amplifier circuit 7 operates, a high level, for example, the power supply voltage V
The drive voltage at the _DD level is applied, and the low-level drive voltage supply line SAL is held at the low level, for example, the ground potential GND. Therefore, for example, according to the storage data of the selected memory cell, the bit lines BL0 and BLB
The small potential difference generated between 0 is detected by the sense amplifier SA0 and amplified.

The potential of the bit line BL0 and the potential of the bit line BLB0 are determined by the amplifying action of the sense amplifier SA0, and the data stored in the selected memory cell is read out as the potential difference between the bit line BL0 and the bit line BLB0. At the same time, the selected memory cell is rewritten by the bit line potential, thereby preventing storage data from being destroyed by reading.

After the bit line potential is determined, a high-level pulse is applied to the transfer control signal line CK0, and the transistors TR0, TR0,
Since TRB0, TR1, TRB1, TR2, and TRB2 are set to the ON state, the potential of each bit line held by the sense amplifier circuit 7 is transferred to each bit line of the data holding buffer 9 via the transfer gate 10. You. Therefore, a potential difference occurs in each bit pair of the data holding buffer 9. After the transfer operation, the transistors TR0, TRB0, TR1, TRB1, T
R2 and TRB2 are kept off.

Then, in the data holding buffer 9,
A high-level drive voltage, for example, a power supply voltage _VDD level is applied to the high-level drive voltage supply line BFH, and the low-level drive voltage supply line BFL is held at a low level, for example, the ground potential GND. Therefore, for example, a small potential difference between the bit line SBL0 and the bit line SBLB0 is latched and held by the buffer BUF0. Similarly, the potentials of the respective bit lines are held by the other buffers BUF1 and BUF2.

As described above, in the present embodiment, the data holding buffer 9 is provided at the next stage of the sense amplifier circuit 7, and the read data is transferred from the sense amplifier circuit 7 to the data holding buffer 9 via the transfer gate 10. As a result, after data transfer, the sense amplifier circuit 7 and the data holding buffer 9 are separated, the sense amplifier circuit 7 and the data holding buffer 9 can operate independently, and the next word line is selected while performing page mode output. Driving and data amplification by the sense amplifier circuit 7 can be performed. Therefore, the access speed in the page mode can be improved.

FIG. 4 is a waveform chart for comparing page mode reading between the present embodiment and a conventional DRAM. Hereinafter, the DRAM of this embodiment will be described with reference to FIG.
Will be described. As shown, in this embodiment, it is possible to read data from each memory cell in the memory row selected by the row address in the previous cycle until the falling edge of the row address selection signal RASB comes. After the row address selection signal RASB falls, the column address in this cycle becomes valid, and each memory cell in the selected memory row can be accessed.

In the conventional DRAM, the memory can be accessed only while the row address selection signal RASB is held at the low level in the page mode. After the row address selection signal RASB rises, the read data becomes invalid. Become. For example, as shown in the figure, in this embodiment, both data 1, data 2 and data 3 are valid, whereas in the conventional DRAM, only data 1 and data 2 are valid and data 3 is invalid. It is.

As described above, in this embodiment, more data can be read in the present embodiment than in the conventional DRAM, that is, the reading speed is improved as compared with the conventional DRAM.

As described above, according to the present embodiment, between the sense amplifier circuit 7 and the input / output buffer 8,
A data holding buffer 9 for temporarily holding the read data of the sense amplifier circuit 7 is provided. When the read data of the sense amplifier circuit 7 is determined at the time of reading in the page mode, the data is transferred to the data holding buffer 9 and input / output by the data holding buffer 9. The data is output to an external data bus via the buffer 8. After data is transferred from the sense amplifier circuit 7 to the data holding buffer 9, a new word line is selected in response to a change in row address, a word line and a bit line are reset, and the next read cycle can be started. Therefore, the memory access speed can be improved.

[0051]

As described above, according to the semiconductor memory device of the present invention, in the memory access by the page mode method, the effect of the delay time caused by the change of the row address can be suppressed, and the access speed can be improved. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is an operation timing chart of the semiconductor memory device of FIG. 1;

FIG. 3 is a circuit diagram showing an internal configuration of a sense amplifier and a data holding buffer.

FIG. 4 is a timing chart for comparing operations of the present embodiment and a conventional DRAM.

FIG. 5 is a circuit diagram showing a configuration example of a conventional semiconductor memory device.

FIG. 6 is an operation timing chart of the semiconductor memory device of FIG. 5;

[Explanation of symbols]

1 row address buffer, 2 row decoder, 3 memory cell array, 4 control circuit, 5 column decoder,
6 column address buffer 7 sense amplifier circuit
8 input / output buffer, 9 data temporary holding buffer, 1
0: transfer gate, SA0, SA1, SA2: sense amplifier, BUF0, BUF1, BUF2: buffer, BL
0, BLB0, BL1, BLB1, BL2, BLB2
SBL0, SBLB0, SBL1, SBLB1, SBL
2, SBLB2 ... bit line, V _DD ... power supply voltage, GN ...
Ground potential.

Claims (9)

[Claims] A plurality of memory cells are arranged in a matrix, memory cells in the same row are connected to the same word line, memory cells in the same column are connected to the same bit line, and a word line selected at the time of memory access is provided. And an operation mode in which a memory cell connected to a bit line is accessed, and a plurality of memory cells connected to the word line are sequentially accessed while the same word line is selected. A semiconductor memory device, comprising: a sense amplifier connected to each of the bit lines for amplifying data transferred to the bit line; and an input for outputting read data to the outside or inputting write data from the outside to the inside. An output buffer, connected between the sense amplifier and the input / output buffer,
A semiconductor memory device comprising: data holding means for holding the read data of the sense amplifier and outputting the held data to the input / output buffer. 2. The semiconductor memory device according to claim 1, further comprising a transfer gate between said data holding means and said sense amplifier for transferring read data of said sense amplifier to said data holding means. 3. The semiconductor memory device according to claim 2, wherein said transfer gate comprises a switching element whose on / off state is controlled according to a transfer control signal. 4. When reading is performed in the operation mode,
The transfer gate is held in an ON state after the read data of the sense amplifier is determined, and after transferring the read data of the sense amplifier to the data holding unit,
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is kept in an off state. 5. The semiconductor memory device according to claim 1, wherein said operation mode is a page mode. 6. A plurality of memory cells are arranged in a matrix, memory cells in the same row are connected to the same word line, memory cells in the same column are connected to the same bit line, and a word line selected at the time of memory access is provided. And an operation mode in which a memory cell connected to a bit line is accessed, and a plurality of memory cells connected to the word line are sequentially accessed while the same word line is selected. A semiconductor memory device, comprising: a sense amplifier connected to each of the bit lines for amplifying data transferred to the bit line; and an input for outputting read data to the outside or inputting write data from the outside to the inside. An output buffer, connected between the sense amplifier and the input / output buffer,
Data holding means for holding the read data of the sense amplifier and outputting the held data to the input / output buffer; connected between the data holding means and the sense amplifier;
And a transfer gate whose on / off state is controlled according to a control signal. 7. When reading in said operation mode,
The transfer gate is held in an ON state after the read data of the sense amplifier is determined, and after transferring the read data of the sense amplifier to the data holding unit,
7. The semiconductor memory device according to claim 6, wherein the semiconductor memory device is kept in an off state. 8. The semiconductor memory device according to claim 6, wherein said data holding means comprises a latch circuit. 9. The semiconductor memory device according to claim 6, wherein said operation mode is a page mode.