JPS6242356B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated memory, and particularly to an integrated memory that does not require a special intermediate potential generation circuit for dummy cells.

Although the following explanation will be made using n-channel MOS transistors for convenience of explanation, the present invention is based on p-channel MOS transistors.
Channel MOS transistors or any other type of transistor can be applied in essentially the same way.

An example of a conventional integrated memory is shown in FIG. 1
2 is an X decoder, 2 is a Y decoder, 3 and 4 are digit lines, 5 and 6 are memory cells, and 9 and 10 are dummy cells. Transistors T1, T2, T3, T
4 and T5 constitute a sense amplifier. FIG. 2 shows the waveforms of the main nodes and clock lines in FIG. 1.

The conventional example shown in FIG. 1 will be described below with reference to the waveforms shown in FIG. In the conventional integrated memory shown in FIG. 1, each digit line 3 and 4 and nodes N1 and N2 are at a constant voltage Vp until the clock signal φ1 falls from a high level to a low level at time t1.
is maintained. At the same time, the nodes N3 and N4 of the dummy cells 9 and 10 are maintained at a voltage Vo between the high and low binary memory signals. At time t2, X decoder 1
When, for example, address line 7 is selected from a large number of address lines by , and becomes a high level state, information in memory cell 5 is read out to digit line 3.
On the other hand, the dummy address line 12 goes into a level state, and the intermediate potential is read out from the dummy cell 10 onto the digit line 4. Conversely, when address line 8 is selected, the information in memory cell 6 is read out to digit line 4, and at the same time, the intermediate potential from dummy cell 9 is read out to digit line 3. As a result,
A minute potential difference is generated between the nodes N1 and N2, which is determined by the capacitance division between the memory cell capacitance Cs and the digit line capacitance C _B. When the clock signal φ2 is set to high level at time t3, the sense amplifier is activated and the node N
The potential difference between N1 and N2 is amplified, and the amplification is completed when the clock signal φ3 is set to high level at time t4 to raise the potential on the high level side of the digit line to the maximum. Thereafter, when the input/output gate 13 selected by the Y decoder 2 is made conductive, the signal of one digit line is output and the reading of the memory cell information is completed. Writing is performed by writing information into the digit line and memory cell through the input/output gate 13.

The integrated memory shown in Figure 1 has the disadvantage that a constant voltage generation circuit must be prepared to obtain the intermediate voltage Vo of the dummy cell, and there is also variation in the power supply voltage or the threshold voltage of the transistor. This has the disadvantage that the value of the intermediate voltage Vo changes, which adversely affects the original operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated memory that can automatically write an intermediate voltage to a dummy cell without the need to specially prepare an intermediate voltage generation circuit for the dummy cell.

The integrated memory according to the present invention includes memory cells arranged in a matrix, a plurality of address lines connecting select gate transistors of the memory cells in the column direction, and a plurality of address lines connecting the digit terminals of the memory cells in the row direction. A pair of digit lines divided into two halves of the book, an X decoder that selects one of the plurality of address lines, a Y decoder that selects one of the plurality of digit lines, and a a plurality of sense amplifiers respectively connected to the digit lines; a first transistor having a drain connected to one of the pair of digit lines, a source to the other digit line, and a gate to the first clock line; , a second transistor whose drain is connected to the digit line, whose gate is connected to the second clock line, and whose source is connected to the storage capacitor; the drain is connected to the digit line, the gate is connected to the dummy address line, and the source is connected to the storage capacitor and the source. A third transistor connected to the source of the second transistor, and a dummy cell formed of the second and third transistors and a storage capacitor connected to each of the pair of digit lines; means for making the first and second transistors conductive during the period, and means for making conductive a third transistor of a dummy cell connected to a digit line that is paired with a digit line connected to the read memory cell when reading memory cell information; An integrated memory characterized by comprising:

The integrated memory of the present invention short-circuits the digit line divided into high and low binary levels with the activation of the sense amplifier at the time of reset by the first transistor T1, so that the potential of the digit line is divided into two high and low levels. In order to automatically create an intermediate potential by storing this potential in a dummy cell and at the same time setting the precharge level of the digit line to this intermediate potential, a digit line precharge transistor and a precharge voltage source are required. It has a point that it does not. In addition, when active, the intermediate potential is always read from the dummy cell for the high and low binary levels read from the memory cell, so there is no need for an extra constant voltage generation circuit, and the intermediate potential due to fluctuations in the power supply voltage and threshold voltage This has the advantage of eliminating fluctuations in potential.

Hereinafter, an example of a typical implementation of the present invention will be described in detail with reference to the drawings. FIG. 3 shows an embodiment of the present invention. FIG. 3 shows an X decoder 31, a Y decoder 31,
The decoder 32 is shown with one digit line and sense amplifier section extracted from an integrated memory consisting of a memory matrix. In the example of FIG. 3, the transistor TR1, whose gate is connected to the clock signal line φ31, couples the left and right divided digit lines 33 and 34 and the nodes N31 and N32, respectively. Both digital lines 33
and 34 are connected to memory cells 35 and 36, respectively, and memory information is input and output through address lines 37 and 38, respectively. Further, dummy cells 39 and 40 are connected to both digit lines. The dummy cell 39 includes a transistor TR2 whose gate is connected to the clock signal line φ32 and which couples the digit line 33 and the node N33, and a transistor TR3 whose gate is connected to the dummy address line 41 and which couples the digit line 33 and the node N33, and the node N.
It consists of a dummy capacitor C _R made at 33. Similarly, the dummy cell 40 includes a transistor TR4 whose gate is connected to the clock signal line φ32 and which couples the digit line 34 and the node N34, and a transistor TR5 whose gate is connected to the dummy address line 42 and which couples the digit line 34 and the node N34. Node N
It consists of a dummy capacitor C _R made at 34 mm. Transistors TR6 and TR7 are transistors whose drains are connected to nodes N31 and N32, respectively, and whose sources and gates are connected to clock signal line φ33.
Grounded via TR8. Transistors TR9 and TR10, whose gates are connected to clock signal line φ34, are connected to DC power supply VDD and nodes N31 and N
32 respectively. Transistor TR11
and TR12 are input/output gate transistors for transmitting information on the digit line read from the memory cell to the outside, and for writing information from the outside onto the digit line.

The circuit operation of FIG. 3 will be explained using the operation waveforms shown in FIG. 4 as follows. Since the feature of the integrated memory of the present invention lies in how to create an intermediate potential at the time of reset, we will start from the time of reset.

When the clock signal φ31 is changed from a low level to a high level at time t31, the digit lines 33 and 34 are short-circuited, and the potential of both digit lines, which were divided into high and low binary levels, becomes an intermediate potential, and this becomes the precharge potential of the digit line. becomes. When clock signal φ32 is set to high level at time t32, an intermediate potential equal to that of the digit line is stored at nodes N33 and N34 of dummy cells 39 and 40. Here, the clock signals φ31 and φ32 are treated as different clocks, but there is no problem in the circuit operation of the present invention even if they are used as equal signals. Next, when the memory operation is active, the clock signals φ31 and φ32 go low at time t33, and the address line goes high at time t34. For example, when the address line 37 becomes high level, the dummy address line 42 also becomes high level, a memory signal is read from the memory cell 35 to the digit line 33, and an intermediate potential is read from the dummy cell to the digit line 34. However,
Since the precharge potential of the digit line 4 is also at an intermediate potential, the potential of the digit line 4 does not substantially change. On the other hand, the potential of the digit line 33 changes depending on the high/low level of the memory signal of the memory cell 35, which is determined by the capacitance division between the parasitic capacitance C _B of the digit line and the memory cell capacitance C _S , and the potential changes between the nodes N31 and N32 occur. A slight potential difference occurs between them. Therefore,
When clock signal φ33 is set to high level at time t35 to activate the sense amplifier, the potential difference between nodes N31 and N32 and digit lines 33 and 34 is amplified, and at time t36, clock signal φ34 is set to high level and the digit line is set to high level. Amplification is completed by raising the side potential to a maximum high level. After that, the digit line selection address line 43 is set to high level, and the input/output transistor T11 is
and T12 are made conductive, the memory signal is transmitted to the outside, and the amplified signal is rewritten into the memory cell, thereby completing the reading of the memory cell. Writing to memory cells is performed using input/output transistors.
This is done by inputting a signal to the digit line and memory cell via TR11 and TR12.

When the address line 38 is selected, the dummy address line 41 is selected, a memory signal is read out to the digit line 34, a dummy signal is read out to the digit line 33, and the operation thereafter is exactly the same as described above. However, what must be noted here is that nodes N33 and N of dummy cells 39 and 40
The point is that C _R must be selected so that each of the 34 total parasitic capacitances (including C _R ) is equal to the memory cell capacitance C _S . By doing this, the sense
When the amplifier is activated, the capacitances of digit lines 3 and 4 become equal, making it difficult for malfunctions to occur.

As can be seen from the above circuit operation, the integrated memory of the present invention simply shorts the potentials of the digit lines divided into high and low levels to create an intermediate potential and stores it in the dummy cell. Therefore, there is an advantage that no special intermediate potential generation circuit is required. Furthermore, since the precharge level of the digit line is also at an intermediate potential, there is an advantage that no special DC voltage source or transistor is required for precharging the digit line.

Therefore, for example, even if the power supply voltage VDD is changed significantly, the dummy cell always stores a potential intermediate between the high and low binary levels of the memory cell, and the intermediate potential is determined by the power supply voltage or the threshold voltage of the transistor. This has the advantage of not varying from the intermediate potential of .

In the above embodiment, as shown in FIG. 3, the transistors supplying charges to the digit lines 33 and 34 were constructed of TRs 9 and 10, but there is no need to limit the transistors to this. It is also possible to adopt a configuration similar to that shown in the following.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional integrated memory, and FIG. 2 is an operational waveform diagram of the circuit shown in FIG. 1. In both figures, φ1, φ2, φ3 are clock signals, N1, N2 are nodes, T1, T2, T3, T
4, T5 is a transistor, 1 is an X decoder,
2 is a Y decoder, 3 and 4 are digit lines, 5,
6 is a memory cell, 7 and 8 are address lines, 9,
10 is a dummy cell, 11 and 12 are dummy address lines, and 13 is an input/output gate. FIG. 3 shows an embodiment of the present invention, and FIG. 4 is an operating waveform diagram of the circuit shown in FIG.
In both figures, φ31, φ32, φ33, φ34 are clock signals, N31, N32, N33, N34 are nodes, TR1, TR2, TR3, TR4, TR5,
TR6, TR7, TR8, TR9, TR10, TR1
1, TR12 is a transistor, 31 is an X decoder, 32 is a Y decoder, 33, 34 is a digit line, 35, 36 is a memory cell, 37, 3
8 is the address line, 39 and 40 are the dummy cells,
Dummy address lines are shown at 41 and 42, respectively.

Claims (1)

[Claims] 1 Memory cells arranged in a matrix,
A plurality of address lines connecting the selection gate transistors of the memory cells in the column direction, a plurality of pairs of digit lines divided into two that connect the digit terminals of the memory cells in the row direction, and a plurality of digit lines connecting the plurality of address lines. an X decoder that selects one of the digit lines; a Y decoder that selects one of the plurality of digit lines;
a plurality of sense amplifiers each connected to the plurality of pairs of digit lines; a drain connected to one of the pair of digit lines; a source connected to the other digit line; and a gate connected to the first clock line. a first transistor with a drain connected to a digit line and a gate connected to a second clock line,
a second transistor having a source connected to a storage capacitor, respectively; a third transistor having a drain connected to a digit line, a gate to a dummy address line, and a source connected to the storage capacitor and the source of the second transistor, respectively; , a dummy cell comprising the second and third transistors and a storage capacitor connected to each of the pair of digit lines, and a transistor supplying charge to each of the pair of digit lines, and after reading the previous memory cell information. means for rendering the first and second transistors conductive when resetting the memory cell; and rendering conductive a third transistor of a dummy cell connected to a digit line paired with a digit line connected to the read memory cell when reading memory cell information; and means for increasing the potential of the digit line on the high potential level side to a potential level higher than the intermediate potential by using transistors for supplying charge to each of the pair of digit lines.