JPH0550076B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an amplifier circuit, and in particular, an amplifier circuit used as an output preamplifier circuit in a dynamic metal oxide semiconductor random access memory (hereinafter referred to as MOS RAM). It is related to circuits.

[Prior Art] When reading data from a memory such as a dynamic MOS RAM, a data signal detected by a sense amplifier is amplified by an output preamplifier circuit and output after giving it a large driving capability. It is customary to adopt . A circuit conventionally used as such an output preamplifier circuit is shown in FIG. 1 along with its peripheral circuits.
Since the memory that most often utilizes this invention is an n-channel dynamic MOS RAM, Figure 1 shows an n-channel dynamic MOS RAM.
A conventional output preamplifier circuit used in RAM is shown.

In FIG. 1, I/O lines 3 and 4 are one set of many input/output lines (hereinafter referred to as I/O lines) connected to a memory array (not shown).
are shown, and an output preamplifier circuit 1 is connected between them. Output preamplifier circuit 1
10 metal oxide semiconductor transistors (MOS transistors, hereinafter simply referred to as transistors) Q
1 to Q10 and two capacitors C1 and C2 form a flip-flop circuit. Further, a sense amplifier 2 is connected between the I/O line 3 and the line 4. This sense amplifier 2 is one of many sense amplifiers, and Y
selected by a decoder circuit (not shown).
Furthermore, the write circuit 5 used when writing to the memory cell, via the write data line (D line) 6 and the inverted write data line (line) 7,
One transistor each Q11, Q12
After being connected to I/O line 3 and line 4. Transistors Q11 and Q12 are for transmitting D line 6 and line 7 to I/O line 3 and line 4, respectively.

Transistors Q1 and Q2 constituting output preamplifier circuit 1 are load transistors of a flip-flop, and transistors Q3 to Q5 are transistors that precharge nodes N1 and N2 to the same potential. Further, transistors Q6 and Q7 are transistors for discharging nodes N1 and N2, respectively, and transistors Q8 and Q9 are flip-flop driver transistors. Furthermore, Q10 is a transistor for discharging node N3.

Next, the connection relationship of the output preamplifier circuit 1 will be explained. First, the drains of each of the transistors Q1 to Q4 are connected to the power supply V _CC . The drain and source of transistor Q5 are each connected to node N.
1 and N2, and a clock _φ1 is applied to the gates of transistors Q3 to Q5. Also,
The sources of transistors Q3 and Q4 are at node N
1 and N2, respectively, and the drains of transistors Q6 and Q7 are also connected to these nodes N1 and N2, respectively. A clock φ ₃ is applied to nodes N1 and N2 via capacitors C1 and C2 for boosting the respective nodes. The source of transistor Q1, the source of Q6, the gate of Q7, and the gate of Q9 are connected to I/O line 3, while the source of transistor Q2, the source of Q7, the gate of Q6, and the gate of Q8 are connected to line 4. has been done. Furthermore, the sources of transistors Q8 and Q9 are connected to the drain of transistor Q10,
The source of this transistor Q10 is connected to ground level (=0V). Transistor Q1
A clock φ ₂ is applied to the gate 0.
Two transistors Q1 connected to write circuit 5
A clock _φ4 is applied to the gates of Q1 and Q12.

The operation of the conventional output preamplifier circuit 1 having such a configuration will be explained with reference to the timing diagram shown in FIG. 2.

Time _t1 At this point, clock _φ1 is at “H” level, so transistors Q3 to Q5 are
ON, nodes N1 and N2 are V _CC −V _TH
(V _TH is the threshold voltage of the transistor). Meanwhile, another precharge means, not shown, applies voltage from the power supply V _CC to I/O line 3 and line 4, both of which are
It is precharged to the level of V _CC . I/
By bringing the gates of transistors Q8 and Q9 connected to O line 3 and line 4 to V _CC , these two transistors are also turned on.
However, at this point, the clock _φ2 is at the “L” level of 0V, so the transistor Q10 is
OFF, so node N3 is also at V _CC
-V _TH is precharged to the level.

Time _t2 At this point, the clock _φ1 has transitioned to the 0V level. After this transition, one sense amplifier is selected by the Y decoder circuit (assuming that this selected sense amplifier is sense amplifier 2 in FIG. 1), and this sense amplifier 2
The data signal detected and amplified by
line 3 and line 4, and a potential difference begins to appear between I/O line 3 and line 4. In FIG. 2, a case is considered where the I/O line 3 goes to "H" level and the line 4 goes to "L" level.

At time _t8 , the clock _φ2 rises from the 0V level to the "H" level. This turns on transistor Q10, discharging node N3 from the level of V _CC -V _TH to 0V. transistor Q
The gates of 8 and Q9 are connected to line 4 and I/O line 3, respectively, so the I/O
The potential difference that was beginning to appear on lines 3 and 4 is rapidly amplified. As a result, the I/O line 3 goes to a level slightly lower than the "H" level, but the potential of the line 4 drops to 0V.
At this time, the gate of transistor Q6 is 0V, so transistor Q6 is OFF,
Node N1 remains at "H" level without being discharged. On the other hand, the gate of transistor Q7 is “H”
level, and the source is 0V, so
Transistor Q7 turns on and node N2
is discharged to 0V.

Time t ₄ At this point, clock _φ3 goes from 0V level to “H”
level. Therefore, node N1 has a capacity C
1 and reaches a level higher than the power supply voltage V _CC . Therefore, transistor Q1 is strongly
It turns on and I/O line 3 is charged to the level of V _CC . On the other hand, since the node N2 has already been discharged to 0V, even if the clock _φ8 goes from 0V to the "H" level, it is not boosted through the capacitor C2 and remains at 0V. Therefore, line 4 remains at 0V. By these operations, amplified data signals are output from I/O line 3 and line 4.

The operation of the output preamplifier circuit 1 during the time period t ₂ to _{t 4} described above is an operation when reading data, and there is no particular problem. However, in a dynamic MOS RAM, a read operation is sometimes followed by a write operation, and this is called a read-modify-write operation. In this operation, the output preamplifier circuit 1 shown in FIG. 1 has a major drawback, and this write operation will now be explained following the previous explanation.

At time _t5 , write clock _φ4 transitions from 0V to “H” level, and transistors Q11 and Q12 turn on.
It becomes ON. In conjunction with this, write circuit 5 operates and applies level changes to D line 6 and line 7 in accordance with the data to be written. Here, time t ₄
In this case, the I/O line 3 is at the "H" level and the line 4 is at the 0V level, but I/O line 3 is at the 0V level, and line 4 is at the "H" level. Assume that this is done. That is, consider writing in which the D line 6 changes from the "H" level to the 0V level, and the line 7 maintains the "H" level.

Time t ₆ With the start of the write operation, the I/O line 3 transitions to "0V" and the line 4 transitions to the "H" level, respectively, and writing to the memory cells connected to these is performed. , the write operation is completed. Along with this, node N1 is discharged to 0V, and node N2 is charged to the V _CC -V _TH level.

This is the timing of the read/modify/write operation, but if an attempt is made to write data opposite to the read data as shown here, the following problem will occur.

That is, from time _t5 to time _t6 , 0V is applied to I/O line 3, which was previously at "H" level.
A potential in the desired direction is applied from the D line 6 through the transistor Q11. However, node N1, to which the gate of transistor Q1 is connected, is boosted above V _CC (see Figure 2), and as a result, transistor Q1 is strongly
Since it is ON, I/O from the power supply V _CC
A voltage is applied to maintain line 3 at the "H" level. Therefore, competition occurs between the output impedance of the write circuit 5 and the impedance of the transistor Q1, and under this competition, the I/O line 3 goes from the "H" level to 0V. . Therefore, I/O line 3
It will take a long time for the voltage to transition from the "H" level to 0V. A similar thing occurs in I/O line 4, and the transistor Q12 is connected from line 7 to I/O line 4, which was at 0V.
While the potential is applied in the direction of "H" level through I/O line 3, which the gate of transistor Q9 is connected to, it does not reach 0V immediately, so transistor Q9 works to keep line 4 at 0V. . Therefore, the output impedance of the write circuit 5 and the transistor Q
Competition with the impedance of wire 9 occurs, and this competition increases the time required for wire 4 to go from the 0V level to the "H" level.

In this way, in conventional amplifier circuits that need to change the potential of the input/output line after amplifying and outputting by holding the potential of the input signal, the high speed of this potential change is hindered. It had the disadvantage of being exposed.

[Summary of the invention] Therefore, the main purpose of this invention is to amplify,
An object of the present invention is to provide an amplifier circuit that can quickly change the potential of an input/output node after an output operation is completed.

To summarize the first invention, first and second load transistors are connected between a power supply potential point and first and second input/output nodes, and the drains and gates of the transistors are connected alternately. After the drains of the first and second driver transistors are connected to the first and second input/output nodes, and a potential difference is generated between the first and second input/output nodes, the discharge transistor that is brought into conduction is connected to the first and second input/output nodes. 1st and 2nd
is connected between the commonly connected sources of the driver transistors of the first and second load transistors and the ground potential point, precharge means for precharging to a desired voltage is connected to the gates of the first and second load transistors, first and second transistors are connected between the gate of the load transistor and first and second input/output nodes, respectively;
Power is input to each gate.

The second invention is to write data to the gates of the first and second transistors in the first invention after amplification of the potentials of the first and second input/output nodes instead of the power supply is completed. write signal is given.

[Embodiment of the invention] As a first embodiment of the invention, an n-channel
An output preamplifier circuit equipped with MOS transistors and used in an n-channel dynamic MOS RAM is shown in FIG. 3 along with its peripheral circuits. Of the circuit shown in FIG. 3, description of the parts similar to those of the circuit shown in FIG. 1 will be omitted, and the description will focus on parts with a new configuration. The output preamplifier circuit 10 in FIG. 3 has transistors Q13 and Q14 connected in parallel to transistors Q6 and Q7, respectively. The gates of transistors Q13 and Q14 are connected to power supply V _CC . The other configurations are the same as the circuit shown in FIG.

Next, the operation of this output preamplifier circuit 10 will be explained with reference to the timing diagram of FIG. Among these, the state before reading at time t ₁ and the state before reading at time t ₂
The read operation at ~ _t4 is the same as the operation of the output preamplifier circuit 1 shown in FIG. 1 (FIG. 2). Among these, the problem caused by adding transistors Q13 and Q14 is the time
Regarding the operation at t ₄ , when node N1 is boosted through capacitor C1, this node N
Although the drain of the transistor Q13 connected to VCC1 is at a high level, the source of the transistor Q13 is also at the V _CC level, so the transistor Q13 is OFF. Further, although the transistor Q14 is turned on, since the node N2 is discharged at this point, this has no effect. Therefore, during reading, the operation of the output preamplifier circuit 10 shown in FIG. 3 is similar to that of the output preamplifier circuit 1 shown in FIG. 1.

Next, the operation during writing will be explained. When the clock _φ4 goes to the "H" level at time _t5 , the transistors Q11 and Q12 turn on, and the write signal from the write circuit 5 passes through the D line 6 and the line 7 to the I/O line 3 and the line 4. Each of them will be added to. As in the case of explaining the operation of the output preamplifier circuit 1 shown in FIG.
It is assumed that the level of
Assume that it works to bring the O line 3 to the 0V level and the line 4 to the "H" level. Since the gate of transistor Q13 is connected to the power supply V _CC , when the potential of I/O line 3 begins to fall at time t ₄ and decreases to V _CC −V _TH , transistor Q13 is turned ON in a short period of time. Then node N1
starts discharging, and the potential of the node N1 begins to follow the potential of the I/O line 3. Then, the gate voltage of transistor Q1 drops rapidly and the voltage on I/O line 3
The impedance of transistor Q1, which was working to keep it at the "H" level, rapidly increased.
The driving ability to maintain the I/O line 3 at the "H" level rapidly decreases. Therefore, there is almost no competition between the output impedance of the write circuit 5 and the impedance of the transistor Q1, and the "H" level of the I/O line 3 is quickly changed.
It is possible to write to 0V.

A similar operation is performed on line 4. In other words, when trying to bring the line 4, which was at 0V, to the "H" level through the transistor Q12, the I/O line 3 quickly becomes 0V, so
The impedance of the transistor Q9, which was working to hold the I/O line 4 at 0V, rapidly increases, making it possible to write the line 4 from 0V to the "H" level at high speed.

FIG. 5 is a diagram showing an output preamplifier circuit 20 and its peripheral circuits as a second embodiment of the invention, and in this circuit, transistors Q6 and Q7
Transistors Q15 and Q
16 is connected, and the gates of transistors Q15 and Q16 are connected to clock _φ4 . The other configurations are the same as the circuit shown in FIG. 1 or 3. The operation of the output preamplifier circuit 20 in this case has the same timing as in the timing diagram of FIG. That is, transistors Q15 and Q16
A clock _φ4 is applied to the gate of the transistor Q15 and Q16, and since the clock _φ4 is 0V during the time period _t1 to _t4 , the transistors Q15 and Q16 are OFF during this time period. This is because the output preamplifier circuit 20 uses transistors Q15 and Q16.
This means that the read operation is performed in the same way as if it were not included. At time t ₅ , clock φ ₄
When the clock becomes "H" level and the write operation begins, the two transistors Q1 are activated by this clock _φ4 .
5 and Q16 are turned on, and high-speed writing becomes possible by the same operation as that described in the first embodiment.

In the embodiment described above, an n-channel MOS transistor was taken as an example, but a p-channel MOS transistor is used as an example.
It goes without saying that it can also be constructed using transistors or other field effect transistors. Furthermore, although a memory output preamplifier circuit is considered here, the present invention can be applied to general amplifier circuits that require rapid changes in the potential of input/output lines after completing amplification and output.

[Effects of the Invention] As described above, according to the present invention, after the amplification and output operations are completed, the potential of the input/output node is changed by the first and second transistors to the potential of the first and second load transistors. Since it is made to follow the gate potential, the potential of the input/output node can be changed at high speed after amplification and output are completed. Moreover, it is only necessary to add the first and second transistors, and there is no need to significantly change the design of the conventional amplifier circuit, which is a great advantage when the amplifier circuit is constructed using an integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an output preamplifier circuit and its peripheral circuits as an example of a conventional amplifier circuit. FIG. 2 is a timing diagram showing the timing of the operation of the output preamplifier circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing an output preamplifier circuit and its peripheral circuits according to a first embodiment of the present invention. FIG. 4 is a timing diagram showing the timing of the operation of the output preamplifier circuit shown in FIG. 3. FIG. 5 is a circuit diagram showing an output preamplifier circuit and its peripheral circuits according to a second embodiment of the invention. In the figure, 1, 10 and 20 are output preamplifier circuits, 2 is a sense amplifier, 3 is an I/O line, and 4
is a line, 5 is a write circuit, 6 and 7 are write data lines, Q1 to Q16 are MOS transistors, C
1 and C2 represent capacitances, and N1 to N3 represent nodes, respectively. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. First and second load transistors provided between a power supply potential point and first and second input/output nodes, their respective drains and gates being alternately connected, and their sources being first and second driver transistors that are commonly connected, the drains of which are connected to the first and second input/output nodes, respectively; the commonly connected sources of the first and second driver transistors and ground; A discharge transistor is provided between potential points and is turned on after a potential difference is generated between the first and second input/output nodes, and the gates of the first and second load transistors are precharged to a desired voltage. a first transistor provided between the gate of the first load transistor and the first input/output node, the gate of which is connected to the power supply potential point; and a precharge means of the second load transistor. An amplifier circuit comprising: a second transistor provided between a gate and the second input/output node and having a gate connected to the power supply potential point. 2. first and second load transistors provided between a power supply potential point and the first and second input/output nodes, the drains and gates of each of which are alternately connected, and the sources of which are commonly connected; , first and second driver transistors whose drains are connected to the first and second input/output nodes, respectively; a transistor provided between the commonly connected sources of the first and second driver transistors and a ground potential point; a discharging transistor that is turned on after a potential difference is generated between the first and second input/output nodes; a precharging means for precharging the gates of the first and second load transistors to a desired voltage; provided between the gate of the first load transistor and the first input/output node;
and a first transistor whose gate is provided with a write signal for writing data after completion of amplification of the potential of the second input/output node; and the gate of the second load transistor and the second transistor. is provided between the input/output node of the first
and a second transistor whose gate is given a write signal for writing data after the amplification of the second input/output node is completed.
Amplification circuit.