JPS59203298A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain the reduction in power consumption of semiconductor memory and stable operation by precharging a bit line by a 1/2 power supply voltage and eliminating the generation of noise due to coupling between the bit line to common noise and between word line and coupling noise. CONSTITUTION:A couple of bit lines B, B' of parallel arrangement are inputted to one input of a sense amplifier SA, a memory cell M1 and a dummy cell DM1 are connected between the bit line B and a word line W1 orthogonal thereto and a dummy word line DW1 respectively and a memory cell M0 and a dummy cell DM0 are connected between the bit line B' and the word line W0 and between the B' and the dummy word line DW0 respectively. In turning on a transistor (TR) Q21, the bit lines B, B' are connected mutually and precharged to a 1/2 power supply voltage, and the power consumption is reduced in comparison with precharging the power supply voltage. On the other hand, the capacitance of the bit lines B, B' is balanced by the symmetrical connection, the word line coupling noise is prevented by the cancellation of the coupling capacity of bit line and common noise, allowing to attain stable operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to an integrated circuit random access memory, so-called semiconductor memory.

(Prior art) Recently, the progress in increasing the capacity of semiconductor memory has been remarkable64
256 bits are about to be put into practical use. The main problems with increasing the capacity are that the bit line capacitance and its imbalance increase, resulting in increased noise generation, increased memory malfunctions, and increased power consumption. . The present invention relates to solving precisely this problem.

FIG. 1 is a circuit diagram showing a main part of a conventional one-transistor type MIS (insulated gate field effect transistor) memory structure. A pair of bit doors pair B.

B is connected to the nodes ■ and ■ of the sense amplifier SA, respectively, and the word line WO and the dummy word 1 are connected orthogonally to the bit line B.
DWo is arranged, and a memory cell MO and a dummy cell DMO are arranged at each intersection. Similarly, on the bit line B, a word line W l and a dummy word line DWI are arranged perpendicularly to each other, and a memory cell Ml and a dummy cell DMl are arranged at each intersection. Note that the word line WO
, Wl are shown with one each for the sake of simplicity, but in reality, n pieces are arranged. Note that the memory cell and the dummy cell each include substantially the same cell capacitance Co and a selection transistor QO.

In this conventional circuit, when reading a memory cell MO, for example, all pulses are applied to the word line Wo and the dummy word line DWI at the same time, and the memory cell MO and the dummy word line DMI are
A minute differential signal appearing as a read signal from two pins B and BK is detected and amplified by operating the sense amplifier SAi with its latch lock tag.

It is completely determined whether the read data is "1ζ" or "0"'.

By the way, the voltage applied to the capacitor Co of the dummy cell D M 1 is generated by the reference voltage generating circuit Gref K.

Data "l" stored in the capacitor Co of the memory cell Mo
Since the voltage corresponding to “, 0” is set to the intermediate value of y, the readout of the dummy cell DMI causes the dipit #il
The voltage appearing on B is data “1”.

It is approximately an intermediate value between "0"'. Therefore, this intermediate value and
The read voltage “1” of the memory cell Mo appearing on the bit line B
The difference in voltage corresponding to `` or 0'' becomes a differential signal with different polarity.

This differential signal output voltage is divided by the charge due to the bit line capacitance! II, the difference between the voltage 1 corresponding to "1" and "0", for example, the intermediate value of 5V and 0, for example, 2.5V, is not simply ±2.5■, but a much smaller value, for example, approximately The value is ±0.3V, which is about 1/10. This differential signal output voltage ΔVB is approximately the voltage of arrows B and H, Vn,
Vn is the voltage of pin) iB, B before opening the word line,
Vs and V♂ are the voltages of the memory cell MO and dummy cell DMI before opening the word + [-, and 9B is the gate capacitance of the memory cell connected to the bit line and the diffusion capacitance with the substrate at each bit line location.

It consists of the human power capacitance of the sense amplifier and the coupling capacitance with other wiring, etc. 1 normal memory cell capacity iCo
This is approximately 10 times the value of This is the main factor that makes the differential signal amount voltage so small as described above.

Incidentally, a large number of bit lines are orthogonal to the hood line, and read signals from respective memory cells are generated on these bit lines. The me9 signal on these bit lines generates noise with respect to other bit lines due to capacitive coupling between the bit line and the word line or the substrate. Therefore,
Bit line pair B.

This causes an imbalance in the signal balance of B, and the direct pressure value of the differential signal that can be detected as a result is completely narrowed, leading to an erroneous determination by the sense amplifier.

In this way, in the conventional circuit shown in FIG.
There is a problem in that the stability of the EVA memory is hindered by the generation of pairwise coupling noise.

As a solution to this problem, a semiconductor memory called a so-called folded bit a method has been disclosed in Japanese Patent Publication No. 55-39073.

Components having the same functions as the circuit shown in FIG. 1 are given the same reference symbols.

This improved memory, as is clear from Figure 2,
In FIG. 1, a pair of bit lines B and Bi are arranged on both sides of the sense amplifier SA, and are arranged parallel to and close to one another on one side of the sense amplifier SA.

It is characterized in that all memory cells and dummy cells are arranged symmetrically at the intersections of the bit line and the word line.

By doing so, the bit a-pair combination noise that was a problem in the memory of FIG. 1 is substantially eliminated. According to this arrangement, the coupling capacitance between each word line and the beat line differs depending on the presence or absence of a memory cell, so when one memory cell is selected, all dummy cells to which one memory cell to be selected is not connected are simultaneously read. We try to prevent this imbalance from occurring.

However, in these two conventional techniques, since the bit line is precharged to the power supply voltage VDD, there is a problem in that power consumption cannot be reduced, which is another major problem with conventional memories.

As a method for completely reducing the power consumption of this memory, the precharge voltage of bit i is essentially set to vDD/2 to reduce the power consumption by half, and the dummy cells are completely unnecessary. Disclosed by. FIG. 3 is a circuit diagram showing the main part of this semiconductor memory configuration. Components with the same functions as before are given the same reference symbols.

A case in which memory cell MO is selected and all data is read out using this circuit will be briefly described.

The voltage of bit lines B and B is set in advance by clock φp.

By turning on transistors QIO and Qllk! ll A value approximately intermediate between the power supply voltage VDII and the ground potential (approximately VDD/2, but the following explanation uses VDD)
/2. ) is precharged. When the memory cell MO is selected, the voltage of the bit line B rises to a value between VDD and VDD/2 if the data written in the cell is "1"; If the data is "0", it drops to an intermediate value between VDD/2 and ground potential. , (in the following explanation, memory cell M
It is assumed that data "1"' is written in O.

) Next, when the clock φL is lowered from the high level to the low level, the sense amplifier SA is activated, and the voltage difference between both bit lines is detected and amplified by guiding the bit iB, which is at a low voltage, to the entire ground potential. Next, the bit line B is precharged to VDD by the pull-up circuit PUK, and data is rewritten. Both bit lines are then left floating, and then both bit lines are connected and their voltage is set to the original VDD.
/ Balances to an intermediate value of 2.

According to the above explanation and the circuit shown in Figure 3 of the first tube.

Dummy cells required for each bit line are not required.Since the precharge voltage of the bit line is substantially VDD/2, a semiconductor memory with a small chip area and half the power consumption can be obtained.

However, as is clear from the above description, this memory still has some problems.

First of all, the capacitance unbalance between the H pairs of bits, which was the problem in the beginning, was basically balanced between the memory cell and the dummy cell, but now it has become larger due to the elimination of the dummy cell. Furthermore, malfunctions due to noise may occur because there is no countermeasure against word line coupling noise based on the coupling capacitance between bit a and the word line. Second, due to the unbalanced capacitance of this bit line pair, the sense amplifier and
Transistors Qs and q9 cannot be connected directly to the gold wire.
For example, it requires a complex pull-a-tub circuit or a circuit connected via an e-way.

(Objective of the Invention) In view of the problems of the prior art, the object of the present invention is to solve the following problems in the VDD/2 system: Bit a vs. common noise due to unbalanced line capacitance, and word acid and bit line An object of the present invention is to provide an entire semiconductor memory that consumes low power and operates stably by eliminating the generation of word line coupling noise due to coupling capacitance.

(Structure of the Invention) The memory of the present invention includes (a) at least one pair of and/or line pairs, (b) a plurality of hood lines and a pair of dummy word lines orthogonal to the pair of bit lines, and a pair of dummy word lines. It is arranged near the intersection of the hood line and one of the trough and trough lines of the trough and trough line pair, and is set to a first voltage state or a second voltage state in response to a write signal.
a gate recell, (→a dummy cell having substantially the same configuration as the memory cell, connected to each bit line by 11 [ii, and normally connected to the bit line); (1) means for connecting all of the bit line pairs to each other at a predetermined timing to bring the balance to the third voltage state; and (c) after setting all of the bit line pairs to the third voltage state, -f: means for connecting the word line to the memory cell corresponding to c9 in response to atto Vs information for one of the above; (a) means for connecting all of the disconnected dummy cells to one of the bit line pairs after detecting the signals on the pair of bit lines; means for driving one Bi-Soto line to a fourth voltage state and the other Bi-Soto line to a fifth voltage state; The cell is completely equipped with means for cutting off the connection between the cell and the Bi-Sotho line.

The memory of the invention also comprises means for balancing said bit i pair to said third voltage state after receiving an access signal.

Furthermore, the memory of the present invention further comprises means for balancing the bit line pair to the third voltage state after disconnecting the memory cell from the bit line.

Furthermore, the memory of the present invention comprises means for connecting all the second terminals of the transistors of the dummy cells to each other in each dummy cell of the bi-soto pair.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 4 is a circuit diagram showing a main part of an embodiment of the present invention.

FIG. 5 is a circuit diagram of one embodiment of the sense amplifier SA. In principle, components having the same functions as those of the conventional example will be given the same reference symbols and detailed explanations will be omitted.

In the circuit of this example, a pair of bit lines B and B arranged approximately in parallel are inputted to one side of the sense amplifier SA, and word lines Wo and B are orthogonally connected to the bit line pair B and B, respectively. Wl
(Although only two are shown in the figure, n lines are arranged.) A pair of dummy word lines DWO and DWI are arranged. A memory cell MO consisting of a selection transistor QO and a memory capacitor CO is arranged near the intersection of the bit line B and the word θWO, and the transistor QO
Its drain is connected to the bit line B, and its gate is connected to the word line Wθ. Similarly, memory cell M1 is a bit @
The intersection of bit line B and word line Wl, dummy cell DMO is the intersection of bit line B and dummy word acid DWo, dummy cell D
Ml are arranged at the intersections of the bi-soto line B and the dummy word line DW1. In addition, dummy word cell DMO
, DMi are normally connected to bit lines B and BK, respectively, with transistor Qoi in an on state. Furthermore, a transistor Q21 is inserted between the bit lines B and B, and both bit lines B and B are connected to the clock φpo.
iConnect.

The sense amplifier shown in FIG. 5 is a typical known circuit, and the present invention is not limited by the circuit design of the sense amplifier.

Next, the operation of this embodiment will be explained with reference to the timing chart shown in FIG. In order to simplify the explanation, a case will be described in which data sound is read from a memory cell MO in which data "1" is being looked at.

Following the activation (low level) of the row address clocks R and A8, a clock φpok for balancing the Bi-Soto line pair is applied.As a result, the transistor Q21 is turned on, and the Bi-Soto line pair B and B become Q21. Since it is connected via f.

Based on charge sharing between the bit line B at the VDD level and the bit line B at the ground potential, both bit lines B.

The voltage of B is VDD / 2 (correctly approximately VDD /
2, but to simplify the explanation, it is assumed to be VDD/2. ). In this case, dummy cells DMO and DM
Since I is also connected to the bit line, it is precharged with a voltage of VDD/2. Next, the voltage of the selected dummy word line Dwo is lowered from the high level to the low level, and the connection between the dummy cell DMo and the bit line B is cut off. Next, by raising the voltage of the selected word line WO from the low level to the high level, the memory cell MO and the word line WO are connected to each other.
Fully connect with Soto line B.

As a result, the voltage on the bit line B becomes a voltage slightly higher than VDD/2 due to the sharing of the charge stored in the bit line capacitance and the charge stored in the cell capacitance CO. On the other hand, since there is no change in bit line B, its voltage is up to 1 of VDD/2. Thus the sense amplifier S
A voltage higher than the node ■ is input to the node ■ of A. Next, when the latch lock φLk is turned on, the transistor Q24 is activated.

When Q2B is turned on, the voltage on the bit line B increases to a value close to the ground voltage (in FIG. 6, it is expressed as ov for simplicity).

), the difference voltage between wires B and B is detected. Next, raise the voltage of the dummy hood line DWo that was lowered earlier, and connect the dummy cell DMoi pit green B again.
Connect to. When the pull-up lock φpe is turned on at about the same time, transistors Q251 and Q26 are turned on, and the voltage on the bit line B is raised to a level close to VDD or to the VDD level using a bootstrap circuit (not shown). What is the voltage of B? It is feedback amplified to a level close to the ground voltage. In this case, dummy cell DM
O is also charged by VDD. (In FIG. 6, the bit line B is expressed as VDD and the bit line BffiOV for simplicity.) Then, the originally stored high level is written to the memory cell MO, and the detected and amplified bit is written to the memory cell MO. Although the voltage difference between the two pairs is not shown, it is transmitted to the input/output circuit via each line, and the voltage state stored in the memory cell is transmitted to the main amplifier provided in the input/output circuit. It is determined, and the voltage state is taken out to the outside via the data line. Next, the word line W.

By lowering the voltage to a low level, the connection between memory cell MO and bit line B is severed, thus returning the memory to its original state and completing the read/write cycle.

In addition, when the data "0" is seen in the memory cell MO, as shown in the helical diagram at the bottom of FIG. 6, when the memory cell MO is selectively connected to the word line WO,
The voltage on bit line B is between VDD /2 and ground voltage,
The voltage is slightly lower than VDD/2 and 1 sense amplifier 8
By activating A, V approaches the ground voltage. Then, the bit line B is pulled up to VDD, and the bit line B is brought closer to the ground voltage, so that data is read as before.

As is clear from the above explanation, in this example,
VDD/';l In addition to using the precharge method.

It is designed so that the bit line capacitance is always balanced and word line coupling noise does not occur.

First, YDD/2 precharging is performed using a simple transistor switch (B = i) of the bit line pair B, which is held at the VDD level ground voltage, just before a read or write operation, which makes it possible to achieve accuracy using an extremely simple circuit. The bit line pair B, B is balanced to an intermediate voltage state of VDD/2 level. This is the third
As in the conventional example shown in the figure, in the present invention, even if the pit line pair B and Bi are connected in advance and held at the VDD/2 level, the memory operation remains unchanged.

(The waveform in that case is shown by the dotted line in Figure 6.) However,
In this case, it is quite difficult to maintain the VDD/2 level accurately for long periods of time. I mean,
This is because there is no way to maintain the level going down due to leakage. On the other hand, in the case of an unsaturated case, the VDD/2 level is set immediately before memory operation based on the VDD level and ground level that can be maintained accurately, so that level is accurately maintained for the required period. So,
This allows more accurate memory operation.

Note that in this embodiment, for the sake of simplicity, the clock φpk is held at a high level and the transistor Q25 f is held at a high level.
In order to reduce power consumption by keeping fi on, the bit line is connected to the power supply VDDVc with a high resistance, and the clock φP is connected to the bit line B as shown by the dotted line.
After raising k to the VDD level, it is better to lower the level and turn off transistor Q25.

Next, the balance of the bit line capacitance (CBo in equation (1) above) is sufficiently guaranteed as follows.

That is, at the time of initial VDD/2 precharge, the dummy cell DMO is connected to the bit line B, the dummy cell DM1 is connected to the bit line B, and the CBs of both bit lines are the same, and then the selection of the memory cell Mo is performed. Sometimes, the memory cell Mo is connected to the bit line B instead of the previous dummy cell DMo, and the dummy cell DMI is connected to the bit line B'! This is because Ca of both bits lJ is the same in this case since it is a case.

Furthermore, word line coupling noise can be completely prevented as follows. That is, in the case of this embodiment.

As in the case of the conventional example shown in FIG. 2, the coupling capacitance between the word line WO and the bit line B and the dummy word line DWI and the bit line B becomes a problem during memory operation. This is because they are approximately equal and the resulting noise is canceled out.

Furthermore, according to this example, the sense amplifier SA is directly connected to the bit line pair as shown in FIG. 5, and the sense amplifier SA is directly connected to the bit line pair as shown in FIG. This is because the bit line capacitance is kept balanced, and thus, according to the present invention, the memory can be operated regardless of the presence or absence of the transfer gate.

Furthermore, in this embodiment, since the dummy cells may have substantially the same configuration as the memory cells, 1, for example, the dummy capacitance *
It has an easy-to-make configuration that does not require special measures such as making it 1/2.

FIG. 7 is a circuit diagram showing a main part of another embodiment of the present invention. In this practical example, the present invention is applied to a case where a bit line pair is arranged on both sides of a sense amplifier SA (open bit line system). Components having the same functions as those in FIG. 4.5 are given the same reference symbols, and detailed explanation thereof will be omitted. In this embodiment, the transistor Q21 for connecting the bit line pair shown in FIG. i-, the crossed transistor Q2 of the sense amplifier 8A, and the transistor Q connected in parallel to Q23.
27, the only difference is that it has been changed to Q28,
The operation of this sister example is no different from the previous embodiment.

That is, according to the present invention, unlike the conventional example shown in FIG. Bit line pair connection transistors Q271 and Q28 can be used freely in any of the methods.
It is possible to use a dummy cell transistor as a substitute or an auxiliary means. That is, as shown in FIG. 8, the connection point between the cell capacitance CO of the selection transistor Qo connected to the dummy word line DWO and the dummy word line D
Cell capacitance C of the selection transistor QO connected to W l
The connection point with O is connected through a transistor Q29k. In the present invention, the dummy word line is normally at high level;
Since each selection transistor is on, the clock φPOk is set to high level and the transistor Q29 f
can be turned on and connected to bit lines B, B',
All bit line pairs can be balanced in a short time.

Further, in the above description, the circuit is limited to a circuit consisting of a pair of bits a, a dummy word line corresponding thereto, a dummy cell, two word lines and a memory cell corresponding thereto; Needless to say, this method can be applied to a memory with N columns.

Furthermore, regarding the clock system that operates the circuit according to the time chart of which one embodiment is shown in FIG.
2. Appropriate circuits can be easily fabricated using known techniques.

(Effects of the Invention) As explained in detail above, the memory of the present invention has the above-mentioned configuration, xv, rIR simple configuration achieves the VDD/2 precharge method @, and unbalanced bit a capacity. Since the word line coupling noise due to the coupling capacitance between the word line and pin 11 can be eliminated, the power consumption is lower than that of the conventional V
It is possible to obtain a highly stable semiconductor memory that is approximately 1/2 the cost of the DD precharge method and that does not malfunction due to noise, and the effect is outstanding.

[Brief explanation of drawings]

1, 2, and 3 are circuit diagrams showing the main parts of the conventional example, FIG. 4 is a circuit diagram showing the main parts of an embodiment of the present invention, and FIG. 5 is the circuit of FIG. 4. 6 is a time chart for explaining the operation of the circuit in FIG. 4, and FIGS. 7 and 8 are main points of other practical examples of the present invention. FIG. In the figure, B, B... bit line, WO
, Wl...word line, DWO, DWI...
...Dummy word line. MO, Ml...Memory cell, DMo, DMt・
・Dummy cell, Co---Cell capacity,
QO-,,Qll, Q21~Q27・Old・・Transistor, to S〇−1・Sense amplifier, Gref・・・・
・・Reference voltage generation circuit, PU・・Pull-up circuit,
φL, φP, φPO...Clock 't VD
D. Old power supply (power supply voltage). 4th ward 5 diagram

Claims (4)

[Claims] (1) (a) At least one bit line pair. (b) A plurality of word lines orthogonal to the pair of bits a and a pair of dummy word lines. (c) It is arranged near the intersection of each bit edge of the bit line pair and the word line, stores the first voltage state or the second voltage state in response to the presumption signal, and and the above-mentioned memory cell. ) with substantially the same configuration as the memory cell. and dummy cells that correspond to each of the bit lines and are normally connected to the bit lines. (a) means for interconnecting the bit e pair at a predetermined timing to balance the third voltage state; (f) After setting the bit line pair to the third voltage state,
and means for connecting one of the memory cells to the corresponding memory cell by the selected word line in response to address information. (g) means for dynamically detecting a signal cap on the bit line pair; Example: means for connecting the disconnected dummy cell to the bit line pair 10,000 after detecting a signal on the bit line pair; (1) Means for feedback amplifying the signals on the 11 pairs of pits and driving all the pit lines on one side to the fourth voltage state and the other bit lines to the fifth voltage state. and means for disconnecting the memory cell from the bit edge after amplifying the above signal. 2. The semiconductor memory according to claim 1, further comprising means for balancing said pair of bits a to said third voltage state after receiving an access signal. (3) A means for balancing the bit il pair to the third voltage state after cutting off the connection between the memory cell and the bit line.
) Semiconductor memory described in section 2. (4) Each dummy cell of the bit line pair has means for connecting the second terminals of the transistors of the dummy cells to each other. 3) Semiconductor memory described in section 3).