JPS54101228A - Mos memory circuit - Google Patents

Mos memory circuit

Info

Publication number
JPS54101228A
JPS54101228A JP797378A JP797378A JPS54101228A JP S54101228 A JPS54101228 A JP S54101228A JP 797378 A JP797378 A JP 797378A JP 797378 A JP797378 A JP 797378A JP S54101228 A JPS54101228 A JP S54101228A
Authority
JP
Japan
Prior art keywords
potential
line
gate
charge
driven
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP797378A
Other languages
Japanese (ja)
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP797378A priority Critical patent/JPS54101228A/en
Publication of JPS54101228A publication Critical patent/JPS54101228A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To establish the memory circuit of one transistor type MOS-RAM having a simple circuit constitution. CONSTITUTION:One transistor type memory cells 1 to 4 consisting of transistor TrQM and capacitive element CM are given at the cross point of the word lines W0 to W3 crossing with a pair of digit line D. A pair of lines D goes down the potential of the common source B of Tr 5,6 in cross connection in the sense amplifier through driving Tr7 and amplifies the potential difference of the node A at sense initiation. The gate of Tr7 is driven with the drive pulse phis, and the source is connected to the reference potential GND and the drain is to the common source of Tr5,6 in cross connection, constituting Tr5,6 into contact A. Further, the line D and the contact A are coupled with Tr8,9 of which gate is driven with the pulse phiT. The charge of the line D is made at the intermediate potential of about 2 V with the precharge transistors Tr10,11 before sensing, and is made with the charge up transistors Tr12,13 after sensing.
JP797378A 1978-01-26 1978-01-26 Mos memory circuit Pending JPS54101228A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP797378A JPS54101228A (en) 1978-01-26 1978-01-26 Mos memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP797378A JPS54101228A (en) 1978-01-26 1978-01-26 Mos memory circuit

Publications (1)

Publication Number Publication Date
JPS54101228A true JPS54101228A (en) 1979-08-09

Family

ID=11680394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP797378A Pending JPS54101228A (en) 1978-01-26 1978-01-26 Mos memory circuit

Country Status (1)

Country Link
JP (1) JPS54101228A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57501001A (en) * 1980-06-02 1982-06-03
JPS5965997A (en) * 1982-10-06 1984-04-14 Matsushita Electronics Corp Semiconductor storage device
JPS5965996A (en) * 1982-10-06 1984-04-14 Matsushita Electronics Corp Semiconductor storage device
JPS59151392A (en) * 1983-02-16 1984-08-29 Sharp Corp Semiconductor read only memory circuit
JPH03173996A (en) * 1989-11-29 1991-07-29 Mostek Corp Dynamic random access memory device
JPH05307886A (en) * 1992-04-01 1993-11-19 Mostek Corp Method for operating dynamic constant speed calling and storage device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57501001A (en) * 1980-06-02 1982-06-03
JPS5965997A (en) * 1982-10-06 1984-04-14 Matsushita Electronics Corp Semiconductor storage device
JPS5965996A (en) * 1982-10-06 1984-04-14 Matsushita Electronics Corp Semiconductor storage device
JPS59151392A (en) * 1983-02-16 1984-08-29 Sharp Corp Semiconductor read only memory circuit
JPH03173996A (en) * 1989-11-29 1991-07-29 Mostek Corp Dynamic random access memory device
JPH05307886A (en) * 1992-04-01 1993-11-19 Mostek Corp Method for operating dynamic constant speed calling and storage device

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