JPH05307886A - Method for operating dynamic constant speed calling and storage device - Google Patents

Abstract

PURPOSE: To discriminate a voltage state without a dummy cell by connecting a memory cell to a bit line, after driving it with an answering voltage, cutting the bit line off and connecting the lines to each other. CONSTITUTION: A row address bit selects a row decoder, such as the decoder 14 to start a row line 18. The row line 18 is connected to a dynamic memory cell 32, and drives the bit line having the lowest voltage to a low voltage state and drives another side bit line to a high voltage state. At this time, when one side bit line is made a grounded voltage, and the other side is made a supplied voltage, a data state in the cell 32 is stored again, and the row line 18 becomes the grounded potential, and separates charges in a memory capacitor 26. Then, a balanced signal is added to gate terminals of respective transistors 50, 52, and they are conducted, and the bit lines 30, 38 are connected through a latch connection part 46. At the time, the bit line is separated from the cell 32, and the bit lines 30, 38 are connected, and the charges in the capacitors 26 are shared with the cells 22, 32. Then, the voltage stored in the cell 32 is discriminated without the dummy cell with reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a constant-speed call storage device utilizing dynamic memory cells.

[0002]

2. Description of the Related Art The operation of a conventional dynamic constant-speed call storage device circuit is the same as that of a Christiane.
U.S. Pat. Nos. 3,588,844 and 3,514,765, invented by n), and Wallstrom (Wa).
Hlstrom) as inventor
No. 9,537 and Playbusting (Proebsti
No. 3,902,082 whose inventor is
And No. 3,969,706. Sense amplifiers are commonly used to sense the differential voltage on each bit line connecting each storage cell, as shown in the Wallstrom and Prebusting patent specifications. The connection of the memory cell to the bit line alters the previously generated voltage on this bit line to produce the desired data state as a differential voltage on each bit line. However, the change in the voltage of the bit line caused by the connection of the storage cell to the bit line is extremely small, and the detection of such a small change in voltage causes a serious problem in the structure of the dynamic constant-speed recall storage device. Yet another problem is that electrical noise is picked up by the bit lines and this electrical noise tends to cross the desired voltage offset caused by the storage cell. In addition, manufacturing tolerances in the integrated circuit cause unbalanced bit lines that interfere with reading the storage cells.

In response to these problems, conventional dummy cells have been made to cooperate with each bit line of a memory device. The dummy cells are precharged to a given voltage state and connected to unselected bit lines in each pair of bit lines during each memory cycle. However, providing a large number of dummy cells with their cooperating circuitry adds to the size of the integrated circuit and further complicates the circuit.

Because of the above-mentioned problems, it operates in such a dimension that it does not require a dummy cell for each bit line, while at the same time providing a reliable and identifiable movement of the voltage state stored in each storage cell. A constant speed call storage is needed.

[0005]

SUMMARY OF THE INVENTION The present invention provides a method of operating a dynamic constant velocity call storage device in the following steps. A high voltage state corresponding to the first data state or a low voltage state corresponding to the second data state is stored in the dynamic memory cell. This memory is then connected to one of these bit lines after setting the pair of bit lines to an intermediate voltage state. When a storage cell that stores a low voltage is connected to a bit line, the voltage on this bit line drops.
When a storage cell that stores a high voltage is connected to a bit line, the voltage of this bit line rises. When the voltage state of one bit line is changed by the connection of the storage cell to this bit line, the other bit line of the pair of bit lines is substantially maintained at the set intermediate voltage state. Be drunk After connecting the storage cell to one of the bit lines, the bit line with the lowest voltage is driven to the low voltage state and the other bit line is driven to the high voltage state. The storage cell is disconnected from the corresponding bit line after driving the corresponding bit line to a low voltage state or a high voltage state. After disconnecting this memory cell from the corresponding bit line, the bit lines are connected to each other and brought to an intermediate voltage state in preparation for a new cycle.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENT A dynamic constant velocity call storage device according to the present invention is illustrated in FIG. A storage address is sent to the storage device 10 via a group of address lines 12. Address line 12 is provided in each of a plurality of row decoders such as row decoder 14.
Each address line 12 is connected to a plurality of column decoders, such as decoders 16 and 17. The address bits for the selected row line are provided in parallel through each line 12 once during the store cycle. Also, the address bits for the selected column are delayed through each line during the store cycle. This is because the address waveform A _o shown in FIG.
˜A _n .

The row address bits select a row decoder, such as decoder 14, to activate row line 18. Line 1
8 is connected to a dynamic storage cell 22 with an access transistor 24 and a storage capacitor 26. The gate terminal of access transistor 24 is connected to row line 18, and the source terminal of access transistor 24 is connected to the first terminal of storage capacitor 26. The remaining terminals of the storage capacitor 26 are connected to the ground connection node 2
8 is connected. The drain terminal of access transistor 24 is connected to bit line 30.

The row line 20 is charged by the row decoder 21 and connected to the dynamic memory cell 32. The dynamic storage cell 32 comprises an access transistor 34 and a storage capacitor 36. access·
The gate terminal of transistor 34 is connected to line 20, and its source terminal is connected to the first terminal of storage capacitor 36. The remaining terminals of the storage capacitor 36 are connected to the ground connection 28. The drain terminal of access transistor 34 is connected to bit line 38.

When the row line 18 is driven to a high voltage state,
The corresponding access transistor 24 is activated,
A conductive path is formed between the bit line 30 and the storage capacitor 26. The voltage on the row line selected by the row decoder is illustrated by the timing signal 40 shown in FIG. The sense amplifier 44 is activated in response to a latch signal transmitted via the latch connection 46. Latch signal L is illustrated as waveform 48 in FIG.

The memory device 10 includes transistors 50 and 52.
Equipped with a balanced circuit with. The source and drain terminals of transistor 50 are connected between bit line 30 and latch connection 46, and the source and drain terminals of transistor 52 are connected between bit line 38 and latch connection 46. Each transistor 50,
The gate terminal of 52 is connected to a connection 54 that receives the balanced signal E. Balanced signal E is illustrated as waveform 56 in FIG. When the balanced signal E is set to a high voltage state, each transistor 50, 52 is turned on, connecting each bit line 30, 38 to the connection 46.

Pull-up circuit 60 is connected to bit line 30 via line 62. The pull-up circuit 60 operates in response to the precharge signals illustrated as waveforms 63, 64 and 66 in FIG. 2 and P ₀ and P ₁ , respectively. A similar pull-up circuit 68 is connected to bit line 38 via line 70. Each pull-up circuit 60, 68 detects when the voltage of the corresponding bit line is higher than the previously set voltage level, and when receiving the precharge signal, pulls up the bit line to the supply voltage as described below. ..

Each bit line is provided with a column transistor which sends the data state within each memory cell and from these memory cells. The source terminal and the drain terminal of the column transistor 74 are connected between the bit line 30 and the input / output line 76. The gate terminal of the column transistor 74 is connected to the column decoder 16. Similarly, the drain terminal and the source terminal of the column transistor 80 are connected between the bit line 38 and the input / output line 82. The gate terminal of the column transistor 80 is connected to the column decoder 17 which responds to the same column address signal as the column decoder 16. Each column decoder 16, 17 is responsive to a column address bit received on address line 12 to activate a selected column transistor and transmit a data state to and from the addressed storage cell.

Input / output lines 76 and 82 are connected to an input / output circuit 84 which serves to transfer the data states written in and read from each storage cell.
Data effects are received from external circuitry via data input terminal 86 and transmitted to external circuitry via data output terminal 87.

Next, the dynamic constant velocity call storage device 1 according to the present invention.
The operation of 0 will be described with reference to FIGS. 1, 2, 3, and 4. This circuit is assumed to operate with a 5.0V power supply. The memory cycle is the row address strobe (RA
S) signal 90. The RAS signal 90 is activated when it transitions from a high level to a low level. Row address bits are provided at the row at frame 14 as shown by waveform 92a. The row address bits are received immediately after the RAS signal goes active. Row decoder 14
Sends a row enable signal 40 to the selected row line.

When the row enable signal 40 goes to the 5V level, the access transistor 24 in the storage cell 22 is reached.
Becomes conductive, and the storage capacitor 26 is connected to the bit line 30.
Connect to. Bit lines 30 and 38 are pre-balanced to a voltage level of about 2.0V, as shown by waveform 96. If the storage capacitor 26 had previously been charged to the stored level of 5.0V, the bit line 30 would have the waveform 96a of FIG. 2 due to the charge sharing between the storage capacitor 26 and the bit line 30. Is driven to about 2.3V. However, if the storage capacitor 26 had previously been discharged to ground potential, the bit line 30 will be about 1.8V, as shown by waveform 96b.

After connecting the memory cell 22 to the bit line 30, the latch signal L shown as waveform 48 is at ground potential. Sense amplifier 44 responds to the latch signal by bringing one bit line connected to it at the lower voltage to ground. If the capacitor 26 was previously discharged, the voltage on the bit line 30 will be as shown by waveform 96b when this voltage is brought to ground. However, if storage capacitor 26 is charged to the stored high voltage level as shown by waveform 96a, bit line 30 is unaffected by the operation of sense amplifier 44. However, if bit line 30 is ramping up to the voltage shown by waveform 96a, then bit line 30 is shown as waveform 98 by bit line 38.
Voltage is exceeded and the bit line 38 is at ground potential as shown by waveform 98a. However, if the voltage on bit line 30 is pulled down by storage capacitor 26, the balanced voltage on bit line 38 will not be affected by sense amplifier 44. This state is shown by waveform 98b.

After the sense amplifier 44 pulls down one of the bit lines to the ground potential, and after precharging the pull-up circuits 60 and 68 with the precharge signal P, the precharge signals P ₀ and P ₁ are received and pulled. Up circuit 60,
68 is activated. Each pull-up circuit 60, 68 detects which one of each bit line has a higher voltage than the previously set voltage. Bit line 1
One is at ground potential and the other bit line is at equilibrium voltage or at elevated pressure caused by connecting a high voltage to a storage capacitor. Bit lines with high voltage are pulled up to the supply voltage. For a bit line that receives a strong charge from a memory cell, this state
It is indicated by a. Waveforms 98b are shown for bit lines that have been balanced. At this time, the storage capacitor connected to the bit line has returned to its original voltage.

When one of the bit lines is driven to the supply voltage and the other bit line is set to the ground potential, the column transistors 74,
80 is turned on to connect the bit lines 30 and 38 to the input / output lines 76 and 82, respectively. The voltage state of each bit line is transmitted to the input / output circuit 84 via each input / output line.
The input / output circuit 84 includes a sense amplifier so as to detect a differential voltage between the input / output lines 76 and 82. The sense amplifier in the input / output circuit measures the voltage state stored in the memory cell and transmits this voltage state via the data output line 87.

After bringing one of the bit lines to ground potential and the other bit line to the supply voltage, the data state in the storage cell is stored again. And the line 18 returns to the ground potential,
Separates the charge on the storage capacitor. These bit lines are then left floating. Then the balanced signal 56
In addition to the gate terminals of the transistors 50 and 52, the transistors 50 and 52 are turned on to connect the bit line 30 to the bit line 38 via the latch connection portion 46. This connection shares charge with each bit line and balances these bit lines to a voltage approximately midway between the supply voltage and ground potential. This is illustrated by both waveforms 96 and 98. In this case, each of the waveforms 96 and 98 returns to the balanced voltage of 2V.

A representative circuit for the sense amplifier 44 shown in FIG. 1 is illustrated in FIG. The source and drain terminals of pass transistor 104 are connected to bit line 3
0 and the connection unit 106. The source and drain terminals of the second pass transistor 108 are connected between the bit line 38 and the connection 110. The gate terminals of both transistors 104, 108 are connected to a high voltage source, such as the supply voltage _Vcc . Each transistor 104, 108 is always conducting and acts as a resistor. The drain terminal of the transistor 112 is connected to the connecting portion 106, the source terminal is connected to the connecting portion 46, and the gate terminal is connected to the connecting portion 106.

Sense amplifier operation occurs after the storage cell is connected to one of the bit lines, either line 30 or line 38. One of the bit lines will then be at a higher voltage than the other bit line. For example, assume that the bit line 30 has the higher voltage. Connection part 46 by the latch signal
Is gradually brought to the ground potential, the bias from the gate to the source of the transistor 114 is larger than the bias from the gate to the source of the transistor 112, so that the transistor 114 is turned on before the transistor 112. When the transistor 114 conducts,
The connection 110 is discharged to the latch connection 46 via the transistor 114.
When the connection part 110 is discharged, the gate bias of the transistor 112 is lowered so that the transistor 112 does not become conductive. When the latch signal is pulled down to ground potential, the transistor 11
4 continues the conduction state. Because the bit line 30
And the connection portion 106 remains in the previous high charge state. When the connection portion 110 is discharged, the bit 38 is discharged due to the conduction of the transistor 108. That is, after the latch signal is completely at ground potential, the bit line 38 is also at ground potential.

When the storage cell is connected to one of the bit lines and the line 38 goes to the higher voltage, the transistor 112 becomes conductive, discharging the connection 106 and bringing the bit line to ground potential.

A fourth circuit diagram of the pull-up circuits 60 and 68 is shown.
It is illustrated in the figure. The drain terminal of transistor 120 is connected to the V _cc power supply, the source terminal is connected to connection 122, and the gate terminal is connected to receive precharge signal P. The drain terminal of the transistor 124 is connected to the connection portion 122, the source terminal is connected to the bit line 30, and the gate terminal is connected to receive the precharge signal P ₀ .

The drain terminal of the transistor 126 is connected to receive the precharge signal P ₁ , the gate terminal is connected to the connecting portion 122, and the source terminal is connected to the gate terminal of the transistor 128. The drain terminal of transistor 128 is connected to the V _cc power supply and the source terminal is connected to bit line 30.

When receiving the precharge signal P, the transistor 120 is rendered conductive and precharges the connection 122 to a high voltage state. When the precharge signal returns to the low voltage level, the connection 122 remains floating in the high voltage state. Precharge signal P ₀ is about 2V
Then, if the bit line 30 is in a sufficiently low voltage state, the transistor 124 becomes conductive and the transistor 1
There is at least one transistor threshold voltage between the 24 gate and source terminals. Transistor 12
When 4 is conducted, the connection portion 122 is discharged to the bit line 30.

However, if the charge on the bit line is sufficiently high and there is a transistor threshold voltage of 1 or less between the gate terminal and the source terminal of the transistor 124, the transistor 124 does not become conductive due to the precharge signal P _0. The connection 122 is left floating at the high voltage level. The P signal is then applied to the drain terminal of transistor 126. When the connection 122 is at a high voltage, the transistor 126 conducts and the transistor 126
Source follows a signal P ₁ above V _cc . This bootstraps connection 122 to a high voltage level due to the channel capacitance of transistor 126. Due to the total voltage level of the bootstrapped precharge signal P ₁ applied to the gate terminal of the transistor 128, the total supply voltage V _cc is applied to the bit line 30 to bring the bit line to the voltage state of V _cc. ..
That is, if the voltage on the bit line 30 is above the pre-set level, the bit line is precharged by the precharge circuit 6
A zero operation raises the supply voltage, but if the voltage on bit line 30 is below a previously set level, precharge circuit 60 does not affect bit line 30.

[0027]

In summary, the present invention resides in a dynamic constant velocity recall storage device that balances each bit line to about half the supply voltage before connecting the storage cell to that bit line. The sense amplifier detects the voltage difference on the bit line caused by connecting the storage capacitor to one of the bit lines, and brings the bit line having the lower voltage to the ground potential. The pull-up circuit brings the bit line having the higher voltage to the high voltage. After transferring the voltage state through the input / output line and after separating the memory cells,
Each bit line is left floating and connected to each other via a latch connection so that these bit lines are returned to their equilibrium voltage by charge transfer between these bit lines.

More specifically, the function and effect of the pull-up circuit will be described. Each pull-up circuit (60, 68) detects the voltage on the bit line connected to it and performs one of the following two kinds of functions. That is, when the voltage on the connected bit line is higher than a predetermined level, the voltage on the bit line is raised to the supply voltage _Vcc . On the other hand, when the voltage on the connected bit line is lower than a predetermined level, it has no effect on the voltage on the bit line. The pull-up circuit is suitable for writing a maximum voltage to the storage capacitor at the end of the read cycle, in addition to providing a sufficient voltage difference between the bit lines for sensing by the sense amplifier in the input / output circuit. Has the important effect of pulling the appropriate bit line to V _cc . The operation of this pull-up circuit is obtained by the transistor shown in FIG. First
The precharge signal P of is supplied to the transistor 120, and this transistor becomes conductive. The precharge connection part 122 is in a high voltage state. The first precharge signal is then removed and the precharge connection 122 is left floating. Then, if the second precharge signal P ₀ is supplied to the transistor 124 and the bit line 30 is in the low voltage state, the transistor 124 becomes conductive and the precharge connection 122 discharges to the bit line, thus the pull-up circuit. Has no effect on the voltage on the bit line. However, if the bit line 30 is in the high voltage state, the transistor 124 will not become conductive even by the second precharge signal.
Next, the third precharge signal P ₁ is applied to the transistor 126.
Is supplied to. Since the precharge connection 122 is in a floating state, the third precharge signal P ₁ can bootstrap the precharge connection 122 so that the total voltage level of the third precharge signal P ₁ is at the transistor 126. Is applied to the gate terminal of the transistor 128. Therefore, the total supply voltage _Vcc is equal to the bit line 30.
And the voltage on the bit line is pulled up to V _cc . This pull-up circuit requires substantially only enough charge to charge the bit line to a high voltage state. That is, there is no direct current path between V _cc and ground in this pull-up circuit at any time. This pull-up circuit acts to directly turn off the bit line. And it is not necessary to detect the potential difference between both bit lines in order to determine which of the both bit lines is pulled up to _Vcc . This allows the pull-up circuit to be located at the end of the bit line rather than between the bit lines where the sense amplifier is located. By arranging the pull-up circuit at the end of the bit line, the effect of shortening the memory access time can be obtained. This is because the input / output circuit connected near the end portion of the bit line, that is, the pull-up circuit does not have to wait for the pull-up voltage to propagate along the bit line (the bit line is relatively high. Since it has a capacitance, a voltage delay applied to one end of the voltage pulse causes a considerable delay before reaching the other end). That is, when the potential difference between all bit lines is applied to the input / output circuit, and therefore the pull-up circuit is enabled, the human power / output circuit can be enabled immediately thereafter, so that the speed can be increased.

Although one embodiment of the present invention has been illustrated and described in detail in the accompanying drawings, the present invention is not limited to the above-mentioned embodiments, and various changes and modifications can be made without departing from the scope of the present invention. Of course.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a dynamic constant velocity call storage device according to the present invention.

2 is a timing diagram of various signals generated in the dynamic constant velocity call storage device illustrated in FIG. 1. FIG.

FIG. 3 is a circuit diagram of the sense amplifier shown in FIG.

FIG. 4 is a circuit diagram of the pull-up circuit shown in FIG.

[Explanation of symbols]

 10 memory device 22, 32 dynamic memory cell 30, 38 bit line 44 sense amplifier 60, 68 pull-up circuit 84 input / output circuit

Claims (4)

[Claims] 1. (a) A first corresponding to a first data state.
The second voltage state corresponding to the second voltage state or the second voltage state of the bit line is stored in the dynamic memory cell, and (b) the pair of bit lines is set to the third voltage state, and When the dynamic memory cell is connected to one side and the first voltage state is stored in the memory cell, the bit line connected to the memory cell is driven to a fourth voltage state, or When the second voltage state is stored in the memory cell, the bit line connected to the memory cell is driven to a fifth voltage state, but the other bit line of the pair of bit lines is Substantially maintaining the third voltage state, and (c) detecting a relative voltage state difference between the bit lines in a sense amplifier directly connected to the bit lines during operation, (d) After connecting the memory cell to the one bit line, A bit line having a lower voltage among the two bit lines is driven to a lower voltage state, and (e) the memory cell is connected to the one bit line, and then the other bit line of the bit lines is driven to a high voltage state. Driving the storage cell to the low voltage state or the high voltage state of the corresponding bit line,
Disconnecting from the corresponding bit line, (g) transmitting the voltage state of at least the bit line previously connected to the storage cell to the input / output circuit, (h) of both bit lines of the pair One of the bit lines is driven to the low voltage state and the other bit line is driven to the high voltage state, and then the both bit lines are connected to each other, and the third voltage state is the first voltage state. And the second voltage state, and the third voltage state is between the fourth voltage state and the fifth voltage state, the voltage of both bit lines is A method of operating a dynamic constant velocity call store without dummy cells, comprising balancing to a third voltage state. 2. After driving one of the bit lines to a low voltage state and driving the other bit line to a high voltage state,
The operating method according to claim 1, wherein each bit line is floated. 3. In connecting the bit lines to each other, a charge is shared between the bit lines so that the bit lines are balanced to a third voltage state.
The operating method according to claim 1, wherein the voltage state is substantially in the middle between the high voltage state and the low voltage state. 4. The step of driving one of the bit lines having the lowest voltage to a low voltage state is performed before the step of driving the other bit line to a high voltage state. The operation method according to claim 1.