JPS54141532A - Mos transistor circuit - Google Patents

Mos transistor circuit

Info

Publication number
JPS54141532A
JPS54141532A JP5031378A JP5031378A JPS54141532A JP S54141532 A JPS54141532 A JP S54141532A JP 5031378 A JP5031378 A JP 5031378A JP 5031378 A JP5031378 A JP 5031378A JP S54141532 A JPS54141532 A JP S54141532A
Authority
JP
Japan
Prior art keywords
mos
memory
potential
mos transistor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5031378A
Other languages
Japanese (ja)
Other versions
JPS6118280B2 (en
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5031378A priority Critical patent/JPS54141532A/en
Publication of JPS54141532A publication Critical patent/JPS54141532A/en
Publication of JPS6118280B2 publication Critical patent/JPS6118280B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To simplify the pattern design of MOS memory device and to realize the MOS memory of high integration, by a pair of sense amplifier MOS transistors in cross connection. CONSTITUTION:The potential of the digit lines D and -D of a pair in memory activation causes a potential difference depending on the information of the MOS transistor QM and capacitor Cm composing the memory cell. When the sense clock phis is inputted to the transistor Q4 connected to the common source of the MOS transistor in cross connection, the MOS transistors Q1 and Q2 in common connection are activated and the information on the digit lines is amplified. In this case, the digit line potential to be held at high potential depending on the resistance value of the resistors R1 and R2 is fallen down. The refresh signal is increased equivalently and the memory operation is made stable, and the pattern of minimized pitch is realized with this circuit arrangement.
JP5031378A 1978-04-26 1978-04-26 Mos transistor circuit Granted JPS54141532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5031378A JPS54141532A (en) 1978-04-26 1978-04-26 Mos transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5031378A JPS54141532A (en) 1978-04-26 1978-04-26 Mos transistor circuit

Publications (2)

Publication Number Publication Date
JPS54141532A true JPS54141532A (en) 1979-11-02
JPS6118280B2 JPS6118280B2 (en) 1986-05-12

Family

ID=12855394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5031378A Granted JPS54141532A (en) 1978-04-26 1978-04-26 Mos transistor circuit

Country Status (1)

Country Link
JP (1) JPS54141532A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443868A (en) * 1980-11-04 1984-04-17 Fujitsu Limited Semiconductor memory device
JPS63113999A (en) * 1986-10-31 1988-05-18 Mitsubishi Electric Corp Dynamic random access memory
JPS63197093A (en) * 1987-02-12 1988-08-15 Mitsubishi Electric Corp Dynamic random access memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443868A (en) * 1980-11-04 1984-04-17 Fujitsu Limited Semiconductor memory device
JPS63113999A (en) * 1986-10-31 1988-05-18 Mitsubishi Electric Corp Dynamic random access memory
JPS63197093A (en) * 1987-02-12 1988-08-15 Mitsubishi Electric Corp Dynamic random access memory

Also Published As

Publication number Publication date
JPS6118280B2 (en) 1986-05-12

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