JPS52155927A - Mos random access memory - Google Patents
Mos random access memoryInfo
- Publication number
- JPS52155927A JPS52155927A JP7290976A JP7290976A JPS52155927A JP S52155927 A JPS52155927 A JP S52155927A JP 7290976 A JP7290976 A JP 7290976A JP 7290976 A JP7290976 A JP 7290976A JP S52155927 A JPS52155927 A JP S52155927A
- Authority
- JP
- Japan
- Prior art keywords
- random access
- access memory
- mos random
- memory cell
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To decrease the number of elements of the memory cell and to enable high integration and high speed readout, by reading out the information of one memory cell with the latch circuit via one digit line, in CMOS RAM of 5 transistors one cell constitution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51072909A JPS595986B2 (en) | 1976-06-21 | 1976-06-21 | MOS random access memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP51072909A JPS595986B2 (en) | 1976-06-21 | 1976-06-21 | MOS random access memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS52155927A true JPS52155927A (en) | 1977-12-24 |
JPS595986B2 JPS595986B2 (en) | 1984-02-08 |
Family
ID=13502936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51072909A Expired JPS595986B2 (en) | 1976-06-21 | 1976-06-21 | MOS random access memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS595986B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04132083A (en) * | 1990-09-20 | 1992-05-06 | Mitsubishi Electric Corp | Semiconductor logic circuit device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62177767U (en) * | 1986-05-01 | 1987-11-11 | ||
JP2573392B2 (en) * | 1990-03-30 | 1997-01-22 | 株式会社東芝 | Semiconductor storage device |
-
1976
- 1976-06-21 JP JP51072909A patent/JPS595986B2/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04132083A (en) * | 1990-09-20 | 1992-05-06 | Mitsubishi Electric Corp | Semiconductor logic circuit device |
JP2796644B2 (en) * | 1990-09-20 | 1998-09-10 | 三菱電機株式会社 | Semiconductor logic circuit device |
Also Published As
Publication number | Publication date |
---|---|
JPS595986B2 (en) | 1984-02-08 |
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