JPS5441027A - Memory output circuit - Google Patents

Memory output circuit

Info

Publication number
JPS5441027A
JPS5441027A JP10767677A JP10767677A JPS5441027A JP S5441027 A JPS5441027 A JP S5441027A JP 10767677 A JP10767677 A JP 10767677A JP 10767677 A JP10767677 A JP 10767677A JP S5441027 A JPS5441027 A JP S5441027A
Authority
JP
Japan
Prior art keywords
output circuit
memory output
make
gates
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10767677A
Other languages
Japanese (ja)
Other versions
JPS5723352B2 (en
Inventor
Masahiro Akitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10767677A priority Critical patent/JPS5441027A/en
Publication of JPS5441027A publication Critical patent/JPS5441027A/en
Publication of JPS5723352B2 publication Critical patent/JPS5723352B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make a circuit high-speed and high-integration with reducing the number of elements and logic stages and make the ensuring of stable operation possible by connecting both gates of a pair of transistors, which are connected in series, to both drain edges of a memory array.
JP10767677A 1977-09-07 1977-09-07 Memory output circuit Granted JPS5441027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10767677A JPS5441027A (en) 1977-09-07 1977-09-07 Memory output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10767677A JPS5441027A (en) 1977-09-07 1977-09-07 Memory output circuit

Publications (2)

Publication Number Publication Date
JPS5441027A true JPS5441027A (en) 1979-03-31
JPS5723352B2 JPS5723352B2 (en) 1982-05-18

Family

ID=14465154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10767677A Granted JPS5441027A (en) 1977-09-07 1977-09-07 Memory output circuit

Country Status (1)

Country Link
JP (1) JPS5441027A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0318080A2 (en) * 1987-11-21 1989-05-31 Koninklijke Philips Electronics N.V. Circuit arrangement for a double bus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0626564B2 (en) * 1986-04-10 1994-04-13 塩谷ヱムヱス株式会社 Synthetic resin gator suspension

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0318080A2 (en) * 1987-11-21 1989-05-31 Koninklijke Philips Electronics N.V. Circuit arrangement for a double bus

Also Published As

Publication number Publication date
JPS5723352B2 (en) 1982-05-18

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