JPS54136240A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS54136240A
JPS54136240A JP4450678A JP4450678A JPS54136240A JP S54136240 A JPS54136240 A JP S54136240A JP 4450678 A JP4450678 A JP 4450678A JP 4450678 A JP4450678 A JP 4450678A JP S54136240 A JPS54136240 A JP S54136240A
Authority
JP
Japan
Prior art keywords
potential
signals
making
high potential
difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4450678A
Other languages
Japanese (ja)
Other versions
JPS622395B2 (en
Inventor
Mitsuru Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4450678A priority Critical patent/JPS54136240A/en
Publication of JPS54136240A publication Critical patent/JPS54136240A/en
Publication of JPS622395B2 publication Critical patent/JPS622395B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To establish the high sensitivity sense amplifying circuit which can correspond to the descaling of the memory cell, by providing the variable resistor means placed in series between the node of FF circuit consisting of FET and the power supply, and making different the resistance value with the potential of the node. CONSTITUTION:After precharging the bit lines B1 and B2 and the sense amplifier of FF circuit constitution by making high potential the clock signals phip and phic and turning on MOSFETQ4, Q5 and Q6, FETQ4 to Q6 are turned off by making the signals phip and phic at lower potential. Further, by making the signals phiw1 and phiw2 at high potential, the signal of the memory cell D is picked up on the bit line B1 to make conductive the dummy cell S and the bit line B2. Further, while keeping the signals phiW1 and phiW2 at high potential, when the clock signals phiL and phiE are made at high potential, the potential D0 and -D0 of the bit lines B1 and B2 which was slight difference, become greater potential difference gamma through the difference of current via the MOSFETQ11 and Q12 to enable to read out the information and to obtain the sense amplifier of high sensitivity.
JP4450678A 1978-04-14 1978-04-14 Semiconductor integrated circuit Granted JPS54136240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4450678A JPS54136240A (en) 1978-04-14 1978-04-14 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4450678A JPS54136240A (en) 1978-04-14 1978-04-14 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS54136240A true JPS54136240A (en) 1979-10-23
JPS622395B2 JPS622395B2 (en) 1987-01-19

Family

ID=12693427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4450678A Granted JPS54136240A (en) 1978-04-14 1978-04-14 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS54136240A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150185A (en) * 1981-03-09 1982-09-16 Fujitsu Ltd Memory circuit
JPS6284487A (en) * 1985-10-09 1987-04-17 Nec Corp Differential amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150185A (en) * 1981-03-09 1982-09-16 Fujitsu Ltd Memory circuit
JPS6284487A (en) * 1985-10-09 1987-04-17 Nec Corp Differential amplifier

Also Published As

Publication number Publication date
JPS622395B2 (en) 1987-01-19

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