JPS5545188A - Dynamic random access memory unit - Google Patents

Dynamic random access memory unit

Info

Publication number
JPS5545188A
JPS5545188A JP11962578A JP11962578A JPS5545188A JP S5545188 A JPS5545188 A JP S5545188A JP 11962578 A JP11962578 A JP 11962578A JP 11962578 A JP11962578 A JP 11962578A JP S5545188 A JPS5545188 A JP S5545188A
Authority
JP
Japan
Prior art keywords
potential vdd
nodes
sense amplifier
memory cell
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11962578A
Other languages
Japanese (ja)
Inventor
Akira Osami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11962578A priority Critical patent/JPS5545188A/en
Publication of JPS5545188A publication Critical patent/JPS5545188A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To obtain a memory cell available for stable refreshment by increasing the sensitivity of a sense amplifier by previously amplifying a signal from a memory cell until activation. CONSTITUTION:To digit lines connected to nodes 3 and 4 at the side of memory and dummy cells of a sense amplifier forming FF by NMOS transistors Q4 and Q5, NMOS transistors, and capacitors Q13 and Q14, and Q8A, Q15, Q16, and Q9A are connected to hold nodes 1, 5, 3, 4, 8, and 9 at power potential VDD is a precharge period. When clocks P1 and P2 are grounded and clocks (phi1) and (phi2) exceed potential VDD in an activation period, transistors 13-16 turn off. Further, when clock (phi3) decreases above potential VDD, nodes 8 and 9 are held at more than potential VDD through capacitor C8A because transistors Q13 and Q14 are high in impedance. Consequently, the signal of the memory at node 2 is pre-amplified until activation to increase the sensitivity of the sense amplifier, so that a memory cell available for stable refreshment can be obtained.
JP11962578A 1978-09-27 1978-09-27 Dynamic random access memory unit Pending JPS5545188A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11962578A JPS5545188A (en) 1978-09-27 1978-09-27 Dynamic random access memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11962578A JPS5545188A (en) 1978-09-27 1978-09-27 Dynamic random access memory unit

Publications (1)

Publication Number Publication Date
JPS5545188A true JPS5545188A (en) 1980-03-29

Family

ID=14766067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11962578A Pending JPS5545188A (en) 1978-09-27 1978-09-27 Dynamic random access memory unit

Country Status (1)

Country Link
JP (1) JPS5545188A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916194A (en) * 1982-07-19 1984-01-27 Nippon Telegr & Teleph Corp <Ntt> Sense circuit system
JPS6057593A (en) * 1983-09-07 1985-04-03 Hitachi Ltd Semiconductor device
JPS6190396A (en) * 1984-10-09 1986-05-08 Nec Corp Dynamic mos memory circuit
JPH03278392A (en) * 1990-03-27 1991-12-10 Nec Corp Control method for semiconductor memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119943A (en) * 1974-07-23 1976-02-17 Ibm
JPS5287328A (en) * 1975-12-29 1977-07-21 Mostek Corp Dynamic random access memory
JPS53108737A (en) * 1977-03-04 1978-09-21 Nec Corp Memory circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5119943A (en) * 1974-07-23 1976-02-17 Ibm
JPS5287328A (en) * 1975-12-29 1977-07-21 Mostek Corp Dynamic random access memory
JPS53108737A (en) * 1977-03-04 1978-09-21 Nec Corp Memory circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916194A (en) * 1982-07-19 1984-01-27 Nippon Telegr & Teleph Corp <Ntt> Sense circuit system
JPH0237634B2 (en) * 1982-07-19 1990-08-27 Nippon Telegraph & Telephone
JPS6057593A (en) * 1983-09-07 1985-04-03 Hitachi Ltd Semiconductor device
JPS6190396A (en) * 1984-10-09 1986-05-08 Nec Corp Dynamic mos memory circuit
JPH047037B2 (en) * 1984-10-09 1992-02-07 Nippon Electric Co
JPH03278392A (en) * 1990-03-27 1991-12-10 Nec Corp Control method for semiconductor memory device

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