JPS63113999A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To enlarge the allowance to an internal noise by providing a transistor to make a bit line pair and an SA driving signal into the same potential at a sense amplifier SA part and further, supplying the precharging potential of a bit line through the wiring of an SA driving signal. CONSTITUTION:When an SA pull-up signal BH goes to a high level, an N channel SA driving signal phiN is precharged through FETQj10 and Qj11 to 1/2VCC. Further, a precharging signal PR goes to a high level, a bit line precharging potential (VBL) generating circuit 10 is connected to a P channel SA driving signal phiP and the potential of both phiN and phiP are made equal to the VBL. At this time, the potential of bit lines BLj and the inverse of Blj goes to the VBL through the FETQj10 and Qj11. Consequently, in this condition, even when the noise of the different phase is overlapped to a bit line pair and the potential is changed, the bit line pair potential and the SA driving signal go to the same potential by the FETQj10 and Qj11 provided for respective bit line pairs, and therefore, the too early action starting of the SA and the sensitivity deterioration can be cancelled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to dynamic random access memory (hereinafter referred to as DRAM), and in particular, to a dynamic random access memory (hereinafter referred to as DRAM),
1/2) CMO3D using vcc precharge method
It is related to RAM.

(Prior art) Figure 5 shows, for example, the International Solid State Circuit Conference (ISSCC'85)
) Digest on Technical Papers p. 2
This figure shows the configuration of the conventional DRAM B/ ) lines and sense amplifiers shown in 52 to 253, and only the main parts of bits '4IABL3 and BLj are shown in the figure. In the figure, Qj, , QJ□ and Qj
,,Qj, are each N-channel sense amplifier N
N constituting SA and P channel sense amplifier PSA
Channel MO5FET and P channel MOS F
ET, the bit line BLj is connected to the drains of the FETs Qj and QJ3, and the FETQJz
A bit line BLj is connected to the drain of Q j 4. Further, bit line BLj is connected to the gates of FET QJ and Q j 3, and FET Q=z
A bit line BLj is connected to the gate of QJ4. Further, a sense amplifier drive signal φ8 is connected to the sources of the FETs Q and QJz, and a sense amplifier drive signal φ2 is connected to the sources of the FETs Q, :l and QJ4.

N-channel MOS FETQS for driving sense amplifier
The sense amplifier driver 2JJ signal φ9 is connected to the drain of H, the sense trigger signal SN is connected to the gate, and the source is connected to the ground potential VSS.

In addition, P-channel MOSFETQ for driving the sense amplifier,
, has a drain connected to a sense amplifier drive signal ψ2, a gate connected to a sense trigger signal SP, and a source connected to a power supply potential ■Cc. Further, WL is a word line, C3, and C1ej are memory cells Mij
These are the FETs and capacitors that make up the circuit. QJ is an equalization MOSFET that equalizes bit &9BLj and BLj, Qc and Qj? is the bit line BLj and ■
Q ; 5 , Q i
An equalization signal EQ is applied to the gates of b and Qj, respectively.
is connected. Here, the bit line precharge potential ■
1 is the normal power supply potential VCC and the ground potential V. is selected to be between (1/2) VCC and VCC. Yj is a column address selection signal, QJ8 and Qj are transfer FETs, and the selected bit lines BLj and BLj and the input/output line I
10 and Ilo.

Next, the operation of the dynamic random access memory configured as described above will be explained with reference to FIG. This will be explained with reference to FIG. Here, it is assumed that the stored content of the □ capacitor Cs ij is "1°."

External π71 signal (hereinafter Ext, RA S
The DRAM enters the active state when the signal (referred to as "signal") falls. When the active state is entered, the external row address signal is latched into the chip by the fall of the Ext and RAS signals. Next, the equalize signal EQ becomes low level,
Equalization between bit lines BLj and BLj is stopped, and at the same time, bit line precharge potential VIIL and bit line B
Lj and BLj are disconnected.

Next, the word line selected according to the row address latched inside the chip becomes high level.

In FIG. 5, it is assumed that WL is selected. Word line WL,
When becomes high level, FETQ, 1. is turned on, the charges stored in the capacitors C8, . Next, the sense trigger signal SN is set to high level, and S,
By lowering the level of FETQ, , 4 and Q,
P is turned on, the sense amplifier drive signal φ8 becomes low level, and φ.

becomes high level. As a result, the N-channel sense amplifier (first sense amplifier) NSA and the P-channel sense amplifier (second sense amplifier) PSA operate, and the potential difference between vABLj and BLT is amplified, and the bit line BLj The stored content "1" of the capacitor C* i j is read out.

Next, the column address selection signal goes high. When bit lines BLj and BLj are selected, column address signal Yj becomes high level, and bit lines BLj and B
Data on Lj is transferred to input/output lines I10 and T700 through transfer FETs Q and Qj.

Next, due to the rising edge of the Ext and RA S signals, the DRAM
When the word line WLi enters an inactive state, the Ext and RAS signals go high, and then the selected word line WLi goes low, turning off FETQ-ii. Next, the sense amplifier trigger signal S8 becomes low level, and SI becomes high level. Next, as the equalize signal EQ becomes high level, the sense amplifier drive signal φ8 changes from a low level to an intermediate level, and φ.

goes from high level to intermediate level. φ8 and φ.

In this example, the intermediate level of is equal to the bit line precharge potential ■1 by a circuit not shown. Furthermore, as the equalize signal EQ becomes high level, the power supply potential ■ during the read operation. , and ground potential VS
The bit lines BLj and BLj, which had been set to 9, are equalized to (1/2)v, cc potential, and at the same time, the bit lines BLj and BLj are connected to the bit line precharge potential ■1. The potential of BLj is (1/2
) Make IIL almost equal to Vcc.

As mentioned above, in a conventional DRAM CMOS dynamic sense amplifier, the bit line is set to the bit line precharge potential VaL in order to prevent the bit line precharge potential from fluctuating due to leakage current etc. in the inactive state of the DRAM. connected to prevent potential fluctuations. In the above conventional example, the N-channel and P-channel sense amplifier drive signals φ8 and φ2 are set to the bit line precharge potential V by a sense amplifier drive signal holding means (not shown).
I try to keep it at IIL. This is intended to keep the bit line and the sense amplifier drive signal at the same potential.

However, as shown in the configuration of a conventional DRAM in FIG. 7, a large number of pin wires, sense amplifiers, etc. are arranged in a DRAM chip, and a sense amplifier drive signal φ8 with a bit line precharge potential VI1 is provided. and φ2 are shared by a large number of bit line materials and sense amplifiers, so the wiring length of the bit line precharge potential VIIL and sense amplifier drive signal becomes long. Therefore, as described above, the bit lines BLj and BLj and the sense amplifier drive signals φ8 and φ are set to the bit line precharge level Vat outside the part where a large number of bit lines, sense amplifiers, etc. are arranged (hereinafter referred to as the array part). When connected to the bit line precharge potential VEIL and the sense amplifier drive signals φ8 and φ, the number of wires that intersect with the wires of the bit line precharge potential VEIL and the sense amplifier drive signals φ8 and φ increases, and it is easy to receive noise due to capacitive cambling with these wires. Become.

In particular, as shown in FIG. 7, the bit line precharge potential VI
If the wirings for IL and the sense amplifier drive signals ψN and φP are placed apart from each other, the proportion of these wirings receiving out-of-phase noise increases.

Due to such noise, if the N-channel sense amplifier drive signal φ8 becomes lower than the potential that is lower than the precharge potential of the bit line by the threshold voltage of the N-channel FET, or if the P-channel sense amplifier drive signal φ is For example, if the potential is higher than the absolute threshold voltage of the P-channel FET with respect to the precharge potential of
7th Annual National Conference of the Institute of Electronics and Communication Engineers Lecture Paper No. 439
As shown in FIG. 2, there are problems in that the activation of the sense amplifier is unnecessarily accelerated, and the sensitivity of the sense amplifier tends to deteriorate due to variations in the characteristics of the transistors constituting the sense amplifier.

As a method to solve some of these problems, for example, there is a method shown in Japanese Patent Application Laid-Open No. 54-8430,
This is shown in FIG. The figure shows a sense amplifier section consisting only of N-channel transistors, and in addition to FETs QI and Q2 that constitute the sense amplifier, an FET is connected between the bit line BL and the sense amplifier drive signal φ8.
E T Q3 and Q4 are provided. This allows the bit NM B to be used in the inactive state of the DRAM.
Since the L and π ends and the sense amplifier drive signal φ9 are brought to the same potential in the immediate vicinity of the sense amplifier, the problem of the sense amplifier being activated too quickly as described above is avoided. In FIG. 8, Q, , , Q are sense amplifier activation FETs, Q7 . Q is a precharge FET.

By the way, when the sense amplifier section is composed of only N-channel transistors as in the example shown in FIG. 8, the bit line is normally at the power supply potential ■. . will be precharged. Precharge FETs Qw and Q6 are usually provided for each sense amplifier, so they are necessarily at the power supply potential ■. , are wired within the array section. However, in the case of a CMOS sense amplifier, it is necessary to wire the bit line precharge potential VIIL within the array section by some method as described above.

However, in this case, if the wires are wired as shown in FIG. 5, the above-mentioned problem will occur due to noise.

[Problem that the invention seeks to solve]

The present invention has been made in order to solve the above-mentioned problems, and its purpose is to obtain a dynamic random access memory having a highly sensitive CMOS sense amplifier and bit line that is not affected by manufacturing process variations or internal noise. do.

[Means for solving problems]

The dynamic random access memory according to the present invention includes:
A means is provided to make the bit line and the ORM type sense amplifier drive signal the same potential in the sense amplifier section, and furthermore, the precharge potential of the bit line is provided within the relay section through the wiring for the N-channel and P-channel sense amplifier drive signals. It was designed to be supplied.

[Effect]

In the present invention, in the sense amplifier portion of one conductivity type, the bit line and the sense amplifier drive signal are set to the same potential, and the precharge potential of the bit line is further passed through the wiring for the N-channel and P-channel sense amplifier drive signals. Since the voltage is supplied to the inside of the array section, even if the precharge potential of the bit line is affected by noise, malfunction of the sense amplifier is prevented and its high sensitivity is guaranteed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the structure of a DRAM bit line and a CMOS sense amplifier according to an embodiment of the present invention. In the figure, Qj, ,Q, and QJ3. Q and 4 are an N-channel MOS FET and a P-channel MOS FET that constitute an N-channel sense amplifier NSA and a P-channel sense amplifier PSA, and the FET
A bit line BLj is connected to the drains of QJl and QJ3, and a bit line BLj is connected to the drains of FETs Q, 2 and Q44.

Further, a bit line BLj is connected to the gates of FETQ, QJ, and J, and FETQ j2 and QJ4
A bit line BLj is connected to the gate of the bit line BLj. Also,
A sense amplifier drive signal φ9 is connected to the sources of FETs QJ and QJ, and a sense amplifier drive signal φ2 is connected to the sources of FETs QJ3 and QJ4.

In addition, N-channel MO3F E for driving the sense amplifier
The sense amplifier drive signal φ is connected to the drain of TQss.
8, the sense trigger signal SS is connected to the gate, and the source is at the ground potential ■. It is connected to the.

P-channel MOS FETQ for driving sense amplifier,
The sense amplifier drive signal φ2 is connected to the drain of P, the sense trigger signal SP is connected to the gate, and the source is connected to the power supply potential ■cc.

N channel MOS FET Q JIo and Q
", is an N-channel MOS FET for making the bit line potential and the sense amplifier drive signal the same potential, and F
A bit line BLj is connected to the drain of ETQJ+o, and a bit line BLj is connected to the drain of FETQ=++. F E T Q = +. and Q4. .

Its source is connected to the sense amplifier drive signal φ8, and its gate is connected to the sense amplifier pull-up signal (first signal) BH.

WLi is the word line, Q t t i and Cz t
J is an FET and a capacitor that constitute the memory cell M port. QjS is a FET that equalizes bit lines BLj and BLj, and an equalization signal E is applied to its gate.
Q is connected. Yj is a column address selection signal, Qj, and Q4. is a transfer EET and performs switching between selected bit lines BLj and 100Lj and input/output lines I10 and Ilo. FETQ
RM and QIF are bit line precharge potential generation circuit 1
This is a FET (first switching means) that performs switching between 0 and N-channel sense amplifier drive signal φ8, and a precharge signal PR is connected to its gate.

Next, the operation of the dynamic sense amplifier configured as described above will be explained using the capacitor Cs i of the memory cell shown in FIG.
The case of reading out the memory contents of j will be explained with reference to FIG. 1 and FIG. 2 which is an operation waveform diagram thereof. Here, capacitor Cs! Suppose that the stored content of j is 1''.

Due to the fall of the Ext and RA S signals shown in Figure 2,
DRAM enters the active state. When it enters the active state, E
xt, RAS The external row address signal is launched into the chip by the fall of the RAS signal. Next, the equalize signal EQ, sense amplifier pull-up signal BH, and precharge signal PR become low level. Next, the word line selected according to the row address latched inside the chip becomes high level. In FIG. 1, it is assumed that WLi is selected. When the word line WLi becomes high level, FET Qsz= is turned on and the charges stored in the capacitors C3,1 are transferred to the bit line BLj, and the potential of the bit line BLj becomes equal to the bit line potential at the time of equalization, that is, the bit line pre-amplifier. It becomes higher than the charge potential VBL. Next, sense trigger signal S8
FE by making it a high level and making SP a low level.
TQ, Q, and P are turned on, and the sense amplifier drive signal φ becomes low level.

becomes high level. As a result, the N-channel and P-channel sense amplifier drive signals φN and ψP operate, the potential difference between the bit lines BLj and BLj is amplified, and the potential of the bit line BLj becomes V ((, bit line BLj
The potential becomes ■, 3, and the capacitor C is connected to the bit line BLj.
The sth memory content "1" is read out.

Next, the column address selection signal goes high. When the bit lines BLj and Wr] are selected, the column address signal Yj goes high and the bit lines &? IBLj and 100T] is transferred to input/output lines I10 and r70 through transfer FETs Q, 8, and Ql.

Next, due to the rising edge of the Ext and RA S signals, the DRAM
When FETQ enters the inactive state, the Ext, RAS signal goes high, and then the selected word line WLi goes low, turning off FETQ, . Next, the sense amplifier trigger signal S8 goes low, S goes high, and the equalize signal EQ goes high, so that the bit lines BLj and BLj are equalized and their potentials are reduced to (1/2). ) VCC. At this time, the N-channel sense amplifier drive signal φ8 is precharged to (1/2) Vcc VroH through FETQ and Q4□, and the P-channel sense amplifier drive signal φ is precharged to (1/2) through FETQ7i and Q4. Vcc+
l Precharged to Vt-1. Here, V TO
N and VfMP are the threshold voltages of the N-channel and P-channel FETs, respectively.

Next, when the sense amplifier pull-up signal BH becomes high level, the N-channel sense amplifier drive signal φ is applied to the FET.
It is precharged to (1/2) Vcc through Q, , and QJ, . Further, the precharge signal PR becomes high level, and the bit line precharge potential generation circuit 10 becomes N
It is connected to the channel sense amplifier drive signal φ8 and the P channel sense amplifier drive signal φ, and makes the potentials of both φ8 and φ equal to VIIL. At this time, FET
Q, ++.

The potentials of the bit lines BLj and BLj also become ■1 through QJI□.

Therefore, in this state, even if out-of-phase noise is superimposed on the bit line and its potential fluctuates, the transistors Q, . Qj,.

As a result, the potential of the focus wire and the sense amplifier drive signal become the same potential, so that problems with conventional devices such as premature start of operation of the sense amplifier and deterioration of sensitivity can be solved without increasing the chip size.

In the above embodiment, the precharge potential of the P channel sense amplifier drive signal φ is (1/2)Vcc+l
Although we have explained the case where VA is 1, as shown in FIG.
By providing channel MOSFETs (potential setting means) Qj+z and Qj13 and applying an inverted signal (second signal) BH of the sense amplifier pull-up signal BH to their gates, the precharge potential of the P channel sense amplifier drive signal φ is set. may be made equal to VIIL.

Note that in the above embodiment, the N-channel sense amplifier section has M which makes the bit line and the sense amplifier drive signal the same potential.
Although we have explained the case where an OSFET is provided, as shown in FIG.
Even if it is provided, the same effect as in the above embodiment can be obtained. However, in this case, it is necessary to appropriately select the voltage waveform of the sense amplifier pull-up signal depending on the conductivity type of the provided MOS FET.

Furthermore, in the above embodiment, a case has been described in which switching of the N-channel sense amplifier drive signal φ8, the P-channel sense amplifier drive signal φ, and the bit line precharge potential generation circuit are both performed by the N-channel MOSFET. As shown in the figure, by appropriately selecting the signal applied to the gate, these switching MOSFETs may be configured with MOSFETs of different conductivity types, and the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, a transistor is provided in the sense amplifier portion to make the bit line material and the sense amplifier drive signal the same potential, and the precharge potential of the bit line is further supplied through the wiring for the sense amplifier drive signal. As a result, a DRAM having a CMOS sense amplifier with a large margin against internal noise can be obtained, and at the same time, there is no need to arrange additional wiring for supplying a bit line precharge potential, and an increase in chip size can be suppressed. effective.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a bit line and a CMOS sense amplifier of a dynamic random access memory according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram showing the operation of FIG. 1, and FIG. FIG. 4 is a block diagram showing still another embodiment of the present invention; FIG. 5 is a diagram showing the structure of the bit line and CMOS sense amplifier of a conventional dynamic random access memory; 6 is an operation waveform diagram showing the operation of FIG. 5, FIG. 7 is a diagram showing the configuration of the array section of a conventional dynamic random access memory, and FIG. 8 is a diagram showing the bit line and N of another conventional dynamic random access memory. FIG. 3 is a diagram showing the configuration of an MOS sense amplifier. WLi...Word line, BLj, πb3...Bit wire, Mth...Memory cell, Q...MO3F ET for equalization-Q=I...First MOS FET
, QJ2...2nd (7) MOSFETS
Qj* - third MOSFET. QJ4...4th MOS FET, QJI.・・・
・Fourth MO3FET, QJI. r QJ...
...Fifth MOSFET. φ8...First sense amplifier drive signal, φ,...Second sense amplifier drive signal, BH...First signal, 100H...Second signal, ■cc...Power supply Potential, vo...
・Ground potential, Q, , Qll, ... 1st. Second switching means, 10... Bit line precharge potential generation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (8)

[Claims] (1) A plurality of word lines, a plurality of bit wires, and an equalizing MOSFE provided for each bit wire.
T, a memory cell provided at each intersection of a word line and a bit line, and an N-channel memory cell provided for each bit line and amplifying the stored information of the memory cell read to the bit line. 1. A first sense amplifier consisting of a second MOSFET, a second sense amplifier consisting of third and fourth P-channel MOSFETs, and a drive signal for the first sense amplifier set between a power supply potential and a ground potential. and a second switching means that connects the drive signal of the second sense amplifier to a potential intermediate between the power supply potential and the ground potential. , an N channel provided for each bit line, whose drain and source are connected to the drains and sources of the first and second MOSFETs, respectively, and whose gate is connected to the first signal, or for each bit line. fifth and sixth P-channel MOSFETs, each having a drain and a source connected to the drain and source of the third and fourth MOSFETs, respectively, and a gate connected to the second signal;
A dynamic random access memory characterized by comprising a T. (2) The dynamic random access memory according to claim 1, wherein the intermediate potential between the power supply potential and the ground potential is equal to a precharge potential of the plurality of bit lines. (3) The dynamic random access memory according to claim 1 or 2, wherein the first and second switching means are N-channel MOSFETs. (4) The dynamic random access memory according to claim 3, wherein the first and second switching means are turned on by the same signal. (5) The first switching means is an N-channel MO
3. The dynamic random access memory according to claim 1, wherein the second switching means is a P-channel MOSFET. (6) The dynamic random access memory according to claim 5, wherein the second signal is an inverted signal of the first signal. (7) The dynamic random access memory according to claim 1 or 2, wherein the timing at which the fifth MOSFET is made conductive is later than the timing at which the equalizing MOSFET is made conductive. . (8) The dynamic random access memory according to claim 1 or 2, wherein the timing at which the switching means is turned on is later than the timing at which the fifth MOSFET is turned on.