JPH09260505A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a cell area by using a latch-up-free structure to make a element isolation distance smaller. SOLUTION: A PMOS transistor 3 and an NMOS transistor 4 constructing a CMOS type cell 5 are formed in an N well region 7 and a P well region 8 formed in a substrate 2, respectively, and a pulled out low resistance region 13 is formed contiguously to the P source region 9 of the PMOS transistor 3 in the N well region 7. A buried low resistance region 13 to be a power supply path is formed contiguously to the N well region 7 in which the pulled out low resistance region 13, and a pulled out low resistance region 14 is formed contiguously to the N source region 11 of the NMOS transistor 4 in the P well region 8. Further, a buried low resistance region 16 to be a power supply path is formed in the substrate 2 contiguously to the P well region 8 in which this pulled out low resistance region 14 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to a CMO on a semiconductor substrate.
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device that prevents a latch-up phenomenon when S-type cells are integrated.

[0002]

2. Description of the Related Art Complementary MIS (Comp
elemental Metal Insulator
A CMOS LSI in which a complementary MO (Oxide) S element, which is a representative of Semiconductor elements, a so-called CMOS element (hereinafter simply referred to as CMOS) is integrated as a cell on a semiconductor substrate (hereinafter simply referred to as substrate) to form an LSI is Widely used. CMOS
Is suitable for high integration due to its structure, and has the advantage that the power consumption is extremely small in terms of operating principle,
For example, SRAM (Static Random Acc
ess Memory).

However, a plurality of CMOS memory cells are integrated so as to correspond to each bit, and S
When applied to a memory array such as a RAM, a parasitic element is formed due to a parasitic effect peculiar to the CMOS structure.
Latch-up phenomenon (hereinafter, simply referred to as latch-up)
Has the drawback that it is inevitable. In order to prevent this latch-up, that is, to improve the latch-up resistance, a P (P conductivity type) MOS that constitutes a CMOS in the substrate is used.
A transistor (hereinafter simply referred to as PMOS) and N (N
The element isolation distance from a (conductivity type) MOS transistor (hereinafter, simply referred to as NMOS) may be increased.

However, if the element separation distance is set too large, the memory cell area increases and the number of memory arrays obtained is limited, so that the degree of integration is reduced. Therefore, the element separation distance is determined by the latch-up resistance.

A brief description of latch-up will be given. A PMOS including an N-well region and a P-well region formed in a substrate and including a P-source region and a drain region in the N-well region.
And an NMOS including an N source region and a drain region is formed in the P well,
The N-well region is used as a base for the element isolation region of
Parasitic PNP bipolar transistors (BiTr) Tr1 and Tr2 having PMOS source and drain regions as emitters and P-well regions as collectors, together with P-well regions as bases, NMOS source and drain regions as emitters, and N-well regions as collectors Parasitic NPN B
iTr · Tr3 and Tr4 are formed.

Power is supplied to the MOS well region, which is the base of the parasitic BiTr, from the outside of the memory cell, while power is supplied to the MOS source region, which is the emitter of the parasitic BiTr, by the VDD wiring and the Vss wiring between the cells. . Also, by the power supply from the MOS well power supply terminal,
A parasitic well resistance (VDD-
A base resistance (rw) of the parasitic PNP-BiTr) and a substrate resistance (Vss-base resistance of the parasitic NPN-BiTr) rs are formed.

A trigger is required to start the latch-up, and the displacement current due to the fluctuation of the power supply voltage, the substrate current, the leak current, the generation of electrons due to the incidence of α rays, etc. are the trigger. As an example, it is assumed that the NMOS-PMOS connection node increases due to the voltage fluctuation, and the active region of the parasitic BiTr · Tr2 is in the forward direction. The emitter current of Tr2 is a trigger and the collector current is Vss terminal and parasitic Bi.
The substrate resistance rs flows between the bases of Tr and Tr4, and the parasitic Bi
When the potential of the active region of Tr / Tr4 becomes forward, the parasitic B
The collector current of iTr · Tr4 flows. When the collector current flows through the well resistance rw between the VDD terminal and the base of the parasitic BiTr.Tr1 and reaches the amount to turn on the parasitic BiTr.Tr1, latchup occurs.

Many techniques have been reported for improving the latch-up resistance. For example, the following six technologies are described in "Ultra High Speed Digital Device Series 2" Ultra High Speed MOS Device ", published by Baifukan Co., Ltd., P54 to P57. (1) Use of guard ring, (2) Double well, (3) Retrograded well, (4) Epitaxial wafer, (5) Trench isolation, (6) Schottky MOSFET.

(1) In each well region, a guard ring made of a high impurity concentration region is provided so as to surround the source region and the drain region, and the well resistance rw and the substrate resistance rs are effectively reduced, so that the parasitic BiTr is formed. It is designed to increase the trigger current that turns on.
(2) raises the impurity concentration of the substrate to the level of the well region,
By reducing the substrate resistance rs, the substrate injection trigger current and the holding current that cause the latch-up operation are increased. In (3), the well region having a high impurity concentration is formed sufficiently deeper than the surface by high-energy ion implantation to reduce the well resistance rw. In (4), an epitaxial wafer layer is formed on a high impurity concentration substrate to reduce the substrate resistance rs. In (5), the element isolation region is separated by a deep insulating layer to prevent the formation of a parasitic BiTr, thereby forming a latch-up free structure. (6) replaces the MOS source / drain junction with a Schottky junction to significantly reduce the current amplification factor of the parasitic BiTr to prevent the latch-up operation.

[0010]

By the way, each of the above-mentioned conventional techniques has the following problems.

In the technique (1), it is necessary to provide a high impurity concentration region in each well region so as to surround the source region and the drain region, so that the degree of integration is lowered.

The techniques (2), (3) and (4) are all designed to increase the trigger current by reducing the well resistance rw and the substrate resistance rs. , Will cause latch-up. In addition, the distance between the power supply position to the well region and the substrate in the memory array and the source power supply position of each bit increases as the memory integration increases.
The well resistance rw and the substrate resistance rs increase. There is a countermeasure to provide a cell for power supply to the well region and the substrate at a rate of one for several tens of bits, but this causes a problem that the area of the memory array increases.

The technique (5) has a latch-up free structure because the parasitic BiTr is not formed. However, a process for forming a trench is required, and a defect caused by the trench formation lowers the isolation yield. become.

The technique (6) is based on the Schottky MOSFE.
T is difficult to form an excellent Schottky junction in a miniaturized CMOS.

It is an object of the present invention to provide a technique capable of reducing the element isolation distance and the cell area by adopting the latch-up free structure.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

(1) In the semiconductor integrated circuit device of the present invention, a PMOS transistor to which a power supply voltage on the high potential side is applied and an NMOS transistor to which a power supply voltage on the low potential side is applied are connected in series, and one of them is selectively connected to the other. A semiconductor integrated circuit device having a CMOS type cell configured to drive a PMOS transistor and an NMOS.
The transistors are formed in an N well region and a P well region, respectively, which are formed in a semiconductor substrate, and a lead low resistance region is formed adjacent to the source region of the MOS transistor in at least one of the well regions. A buried low resistance region serving as a power supply path is formed in the semiconductor substrate so as to contact the well region in which the region is formed.

(2) In the method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a buried low resistance region to be a power supply path at a desired position using a semiconductor substrate of an arbitrary conductivity type,
Forming a semiconductor layer of an arbitrary conductivity type on the semiconductor substrate; forming an N well region and a P well region adjacent to the semiconductor layer; and forming a P source region and a drain region in the N well region. The method includes a forming step, an N source area and a drain area in the P well area, and a lead low resistance area adjacent to the source area of at least one of the well areas.

According to the above-mentioned means (1), the semiconductor integrated circuit device of the present invention is a PM which constitutes a CMOS type cell.
The OS transistor and the NMOS transistor are formed in an N well region and a P well region, respectively, which are formed on the semiconductor substrate, and a lead low resistance region is formed adjacent to the source region of the MOS transistor in at least one well region. Since a buried low resistance region serving as a power supply path is formed in the semiconductor substrate so as to contact the well region in which the lead low resistance region is formed, PM
Power is supplied to the OS transistor, the NMOS transistor, or both of them from the buried low resistance region serving as the power supply path to any of the well regions and the adjacent source region through the drawn low resistance region formed therein. .

With this power supply structure, both the parasitic PNP and NPN.BiTr formed in the element isolation region are prevented from being turned on by the trigger. Therefore, the structure is latch-up free, and the element separation distance can be reduced, so that the cell area can be reduced.

According to the above-mentioned means (2), in the method for manufacturing a semiconductor integrated circuit device of the present invention, first, an embedded low resistance region to be a power supply path is formed at a desired position using a semiconductor substrate of an arbitrary conductivity type. After the formation, a semiconductor layer of an arbitrary conductivity type is formed on the semiconductor substrate. Next, N is added to the semiconductor layer.
After forming a well region and a P well region adjacent to each other, a P source region and a drain region are formed in the N well region, and an N source region and a drain region are similarly formed in the P well region. Then, a lead low resistance region is formed adjacent to the source region of at least one of the well regions. As a result, power is supplied to the PMOS transistor, the NMOS transistor, or both from the buried low resistance region serving as the power supply path to any of the well regions and the adjacent source region through the lead low resistance region formed therein. The semiconductor integrated circuit device thus manufactured can be manufactured.

With this power feeding structure, both the parasitic PNP and NPN.BiTr formed in the element isolation region are prevented from being turned on by the trigger. Therefore, the structure is latch-up free, and the element separation distance can be reduced, so that the cell area can be reduced.

The present invention will be described in detail below with reference to the drawings along with the embodiments.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) FIG. 1 is a plan view showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. 3 is a sectional view taken along line BB of FIG. 4 is a sectional view taken along the line CC of FIG. The semiconductor integrated circuit device (CMOS LSI) 1 according to the first embodiment includes, for example, a PMOS transistor (hereinafter, simply referred to as PMO) formed adjacently on a Si substrate 2.
A plurality of CMOS cells 5 each including an S transistor 3 and an NMOS transistor (hereinafter, simply referred to as an NMOS) 4 are integrated to form a memory array such as an SRAM. In FIG. 1 to FIG.
Only one CMOS cell 5 is shown.

A P or N semiconductor layer 6 is formed on the substrate 2 by, for example, an epitaxial growth method, and the N well region 7 and the P well region 8 are adjacent to the semiconductor layer 6.
Are formed. A high impurity concentration P source region 9 and a drain region 10 are formed in the N well region 7, and a high impurity concentration N source region 11 and an N drain region 12 are formed in the P well region 8.

Adjacent to the P source region 9 of the N well region 7, a lead low resistance region 1 made of an N high impurity concentration region.
3 is formed, and a lead low resistance region 14 made of a P high impurity region is formed adjacent to the N source region 11 of the P well region 8. The impurity concentration of each of the lead-out low resistance regions 13 and 14 is, for example, 10 ¹⁹ to
It is set to 10 ²⁰ / cm ³ .

A buried low resistance region 15 made of an N high impurity concentration region is formed on the substrate 2 so as to come into contact with the bottom of the N well region 7, and a P high region comes into contact with the bottom of the P well region 8. A buried low resistance region 16 formed of an impurity concentration region is formed, and each of these buried low resistance regions 15 and 16 functions as a power supply path. The impurity concentration of each of the buried low resistance regions 15 and 16 is 10 as an example.
It is set to ¹⁹ to 10 ²⁰ / cm ³ .

A gate metal 17 is formed between the P source region 9 and the P drain region 10 on the surface of the N well region 7, and the N source region 1 on the surface of the P well region 8 is formed.
A gate metal 18 is formed between the 1 and the N drain region 12.

The lead low resistance region 13 formed in the N well region 7 and the P source region 9 adjacent to the lead low resistance region 13 are made of, for example, TiSi ₂ (titanium silicide), PtSi (platinum silicide), W, Mo or the like. The lead low resistance region 14 formed in the P well region 8 and the N source region 11 adjacent to the lead low resistance region 14 are connected by the same low resistance conductive layer 19 while being connected by the conductive layer 19. The same low resistance conductive layer 19 is formed on the surfaces of the P source region 9 and the drain region 10 of the N well region 7 and the N source region 11 and the drain region 12 of the P well region 8.
Are formed. By forming the lead low resistance regions 13 and 14 adjacent to the source regions 9 and 11, respectively, the memory cell area can be reduced.

As a result, the high-potential-side power supply voltage (VDD) is supplied to the P source region 9 of the PMOS 3 from the embedded low resistance region 15 through the N well region 7 and the lead low resistance region 13 formed therein. The power supply voltage (Vss) on the low high potential side is supplied to the N source region 11 of the NMOS 4 from the buried low resistance region 16 to the P well region 8 and the extraction low resistance region 14 formed therein. It is supposed to be done through.

Here, power supply to the N well region 7 or the P well region 8 of each bit constituted by a plurality of CMOS type cells 5 may be performed to either one of the PMOS 3 and the NMOS 4. It is the parasitic PNP / BiTr and parasitic NPN / that cause the latch-up.
This is because it is necessary that both of the BiTrs are turned on, and it is sufficient to prevent one of the parasitic BiTrs from being turned on.

Reference numeral 20 is a protective film made of an oxide film (SiO ₂ ) or the like, and 21 is a similar interlayer insulating film. Interlayer insulating film 21
A contact window 22 is formed at a desired position of the wiring, and a wiring 23 is drawn from the P drain region 10 of the N well region 7 and the N drain region 12 of the P well region 8. As a result, the PMOS 3 and the NMOS 4 are formed. P
The wiring 23 from the P drain region 10 of the MOS3 is an NMO.
While being connected to the N drain region 12 of S4, PM
Gate metal 17 of OS3 and gate metal 18 of NMOS4
And are directly connected to form the CMOS cell 5.

FIG. 5 is a connection diagram showing an SRAM memory array configured by the semiconductor integrated circuit device 1 according to the first embodiment. A 1-bit memory cell 24 is configured by an FF (Flip Flop) in which a pair of CMOS type cells 5 are combined. In the P source region 9 of the PMOS 3 of the pair of CMOS type cells 5 forming each bit, the V formed by the embedded low resistance region 15 is formed.
VDD is supplied by the DD wiring 25 through the N well region 7 and the lead low resistance region 13 formed therein. Similarly, a pair of CMs constituting each bit
Vss is supplied to the N source region 11 of the NMOS 4 of the OS cell 5 by the Vss wiring 26 constituted by the embedded low resistance region 16 through the P well region 8 and the extraction low resistance region 14 formed therein. . 27 is a gate transistor, 28 is a word line, and 29 is a bit line.

FIG. 6 is a sectional view for explaining latch-up of the CMOS type cell 5 in the semiconductor integrated circuit device 1 according to the first embodiment, and FIG. 7 is an equivalent circuit of FIG. In FIG. 6, N is formed in the element isolation region of PMOS3 and NMOS4.
The well region 7 is used as the base, the PMOS source region 9 and the drain region 10 are used as the emitters, and the P well region 8 is used as the collector, together with parasitic PNPs, BiTrs, Tr1 and Tr2, and P
Parasitic NPN-BiTr-Tr3 and Tr4 are formed using the well region 8 as a base, the NMOS source region 11 and the drain region 12 as an emitter, and the N well region 7 as a collector.

In addition, a parasitic well resistance rw is formed between the buried low resistance region 15 serving as the VDD wiring and the base of the parasitic PNP / BiTr / Tr1. Similarly, Vss
Embedded low resistance region 16 to be wiring and parasitic NPN / Bi
A parasitic substrate resistance rs is formed between the base of Tr and Tr4. Further, as understood from FIG. 7, connection resistances r1 and r2 are formed between the well regions 7 and 8 and the source regions 9 and 11, respectively.

That is, VDD is supplied through the N well region 7 and the lead low resistance region 13 and Vss is supplied through the P well region 8 and the lead low resistance region 14, and a trigger current flows in each parasitic resistance. In this case, since the base and emitter of the parasitic BiTr are reversely biased, latch-up does not occur.

Here, the value of each resistance of these parasitics is P
A low resistance region 13 extending to the N well region 7 of the MOS 3 is formed adjacent to the P source region 9, and N
Since the low resistance region 14 extending to the P well region 8 of the MOS 4 is formed adjacent to the N source region 11, the resistance value is sufficiently smaller than the conventional parasitic resistance values.

According to the CMOS type cell 5 obtained in the first embodiment, when the power supply voltage VDD is 2.5 V, the element separation distance is 1.8 μm to 1.2 μm.
Could be reduced to.

It is desirable that the impurity concentration of each of the buried low resistance regions 15 and 16 serving as a power source path formed in contact with the N well region 7 and the P well region 8 be as high as possible in order to reduce the wiring resistance. The formation of such buried low resistance regions 15 and 16 can be easily realized by applying an impurity ion implantation technique.

When the wiring resistance increases, the source potential of the memory cell decreases, so that the memory operation margin decreases. A countermeasure can be taken by forming the buried low resistance regions 15 and 16 in which the impurity concentration is set to be high and the width is made sufficient as in the first embodiment.

According to the first embodiment as described above, the following effects can be obtained.

The PMOS transistor 3 and the NMOS transistor 4 forming the CMOS type cell 5 are formed in the N well region 7 and the P well region 8 formed in the substrate 2, respectively, and the P source region of the PMOS transistor 3 in the N well region 7 is formed. An extraction low resistance region 13 is formed adjacent to the substrate 9, and an embedded low resistance region 15 serving as a power supply path is formed in the substrate 2 so as to contact the N well region 7 in which the extraction low resistance region 13 is formed. , P-well region 8
A low resistance region 14 is formed adjacent to the N source region 11 of the NMOS transistor 4 and the P well region 8 in which the low resistance region 14 is formed.
Since the embedded low resistance region 16 serving as a power supply path is formed on the substrate 2 so as to contact with, the power supply to the PMOS transistor 3 is performed from the embedded low resistance region 15 to the extraction low resistance region formed in the N well region 7. 13 to the P source region 9, and N
The power supply to the MOS transistor 4 is embedded in the low resistance region 1
From 6 to the N source region 11 through the lead low resistance region 14 formed in the P well region 8, a latch-up free structure is obtained, and the element separation distance can be shortened. The cell area can be reduced.

(Embodiment 2) FIGS. 8 to 13 are sectional views showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention, showing a method of manufacturing a semiconductor integrated circuit device according to the first embodiment. The steps will be described below in the order of steps with reference to the drawings.

First, as shown in FIG. 8, a low resistance region 15 is formed by implanting N impurity ions at a desired position using, for example, a P or NSi substrate 2, and a low resistance is produced by implanting P impurity ions. Area 1
6 is formed. Each region 15, 16 has, for example, 10 ¹⁹ to 1
It is set to a high impurity concentration of 0 ²⁰ / cm ³ . By applying the impurity ion implantation technique, it is possible to easily form a high impurity concentration region having a small wiring resistance.

Next, as shown in FIG. 9, a P or N semiconductor layer 6 is formed on the substrate 2 by, for example, an epitaxial growth method. As a result, the low resistance regions 15 and 16 are embedded in the semiconductor layer 6.

Subsequently, as shown in FIG.
With the unnecessary portion masked with the photoresist 30,
By implanting N impurity ions and P impurity ions alternately in the necessary portions, N well region 7 and P well region 8 are formed adjacent to each other so as to contact buried low resistance regions 15 and 16, respectively. The N well region 7 becomes a region where a PMOS should be formed, and the P well region 8 becomes a region where an NMOS should be formed.

Next, as shown in FIG. 11, a P source region 9 and a drain region 10 are formed by implanting P impurity ions into the N well region 7, and at the same time, for example, 10 ¹⁹ to 10 10 are formed in the P well region 8. An extraction low resistance region 14 having a high impurity concentration of ²⁰ / cm ³ is formed.

Similarly, as shown in FIG. 12, the N source region 11 and the drain region 12 are formed by implanting N impurity ions into the P well region 8, and at the same time, for example, 10 ¹⁹ to 10 ¹⁹ An extraction low resistance region 13 having a high impurity concentration of 10 ²⁰ / cm ³ is formed. When forming each region by the impurity ion implantation in FIGS. 11 and 12, the unnecessary portion is masked with the photoresist 30 as in the above process.

Subsequently, as shown in FIG. 13, after the gate metals 17 and 18 and the low resistance conductive layer 19 are formed, the whole is covered with an interlayer insulating film 21 made of, for example, an oxide film.
Next, as shown in FIG. 2, a contact window 22 is formed at a desired position in the interlayer insulating film 21, and then a desired wiring process is performed, so that the semiconductor integrated circuit as shown in FIGS. The device 1 is manufactured.

According to the second embodiment as described above, the following effects can be obtained.

First, an embedded low resistance region 15 serving as a power source path is formed at a desired position using a substrate 2 of an arbitrary conductivity type, and then a semiconductor layer 6 of an arbitrary conductivity type is formed on the substrate 2.
Next, an N well region 7 and a P well region 8 are formed adjacent to each other in the semiconductor layer 6, and then a P source region 9 and a drain region 10 are formed in the N well region 7, and similarly, the P well region is formed. 8, an N source region 11 and a drain region 12 are formed, and subsequently, the well regions 7 and 8 are adjacent to the source regions 9 and 11, respectively, and are respectively drawn out to have a low resistance region 1.
Since the transistors 3 and 14 are formed, power is supplied to the PMOS transistor 3 from the buried low resistance region 15 to the P source region 9 through the lead low resistance region 13 formed in the N well region 7. In addition, power is supplied to the NMOS transistor 4 from the embedded low resistance region 16,
Lead-out low resistance region 1 formed in the P well region 8
Since it is possible to manufacture the semiconductor integrated circuit device performed on the N source region 11 through 4, the structure becomes a latch-up free structure and the element separation distance can be shortened, so that the cell area can be reduced.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the invention.

For example, although the above embodiment has been described by taking the example applied to the memory array of SRAM, the present invention is not limited to the memory as long as it is configured by combining the CMOS type cells, and may be applied to other uses such as logic. it can.

Further, the specific material used for the low resistance conductive layer is not limited to those exemplified in the above embodiment, but other materials such as poly Si may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor integrated circuit device which is the field of application which is the background of the invention has been described, but the invention is not limited thereto. The present invention is at least CM
It can be applied to a device that requires the combination of OS type cells to form an electronic device.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

The PMOS transistor and the NMOS transistor which form the CMOS type cell are respectively formed in the N well region and the P well region formed in the semiconductor substrate, and are drawn adjacent to the source region of the MOS transistor in at least one well region. Since the low resistance region is formed and the embedded low resistance region serving as a power supply path is formed in the semiconductor substrate so as to contact the well region in which the extraction low resistance region is formed, the PMOS transistor or the NMOS transistor or both of them are formed. Since the power is supplied to the source region adjacent to the well region and the low resistance region formed in the well region from the embedded low resistance region serving as the power supply path, a latch-up free structure is provided. And reduce the element separation distance Since bets can, it is possible to reduce the cell area.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a sectional view taken along line CC of FIG.

FIG. 5 is a connection diagram showing an SRAM memory array configured by the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating latch-up of a CMOS cell in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is an equivalent circuit of FIG.

FIG. 8 is a sectional view showing a step of the method of manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 9 is a sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view showing another step of the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor integrated circuit device (CMOS LSI), 2 ... Substrate, 3 ... PMOS transistor, 4 ... NMOS transistor, 5 ... CMOS type cell, 6 ... Semiconductor layer, 7 ... N well region, 8 ... P well region, 9 ... P Source area, 10 ...
P drain region, 11 ... N source region, 12 ... N drain region, 13, 14 ... Lead-out low resistance region, 15, 16
... Embedded low resistance region, 17, 18 ... Gate metal, 19
... low-resistance conductive layer, 20 ... protective film, 21 ... interlayer insulating film, 2
2 ... Contact window, 23 ... Wiring, 24 ... Memory cell, 2
5 ... VDD wiring, 26 ... Vss wiring, 27 ... Transfer gate, 28 ... Word line, 29 ... Bit line, 30 ... Photoresist.

Claims (7)

[Claims] 1. A PMO to which a power supply voltage on the high potential side is applied.
S transistor and N to which the power supply voltage on the low potential side is applied
What is claimed is: 1. A semiconductor integrated circuit device having a CMOS cell in which MOS transistors are connected in series and one of which selectively drives the other, wherein the PMOS transistor and the NMOS transistor are formed on a semiconductor substrate. A lead low resistance region is formed adjacent to the source region of the MOS transistor in at least one of the well regions and the P well region, and is in contact with the well region in which the lead low resistance region is formed. In the semiconductor integrated circuit device, an embedded low resistance region serving as a power supply path is formed in the semiconductor substrate. 2. The semiconductor integrated circuit device according to claim 1, wherein the lead-out low resistance region formed in the well region comprises a high impurity concentration region of the same conductivity type as the well region. 3. The semiconductor integrated circuit according to claim 1, wherein the lead low resistance region formed in the well region and the source region adjacent to the lead low resistance region are connected by a low resistance conductive layer. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the embedded low resistance region formed on the semiconductor substrate is formed of a high impurity concentration region. 5. A step of forming a buried low resistance region to be a power supply path at a desired position using a semiconductor substrate of an arbitrary conductivity type, and a step of forming a semiconductor layer of an arbitrary conductivity type on the semiconductor substrate, Forming an N well region and a P well region adjacent to each other in the semiconductor layer, forming a P source region and a drain region in the N well region, and forming an N source region and a drain region in the P well region. And a step of forming a lead low resistance region adjacent to the source region of at least one well region, the method of manufacturing a semiconductor integrated circuit device. 6. The semiconductor integrated circuit according to claim 5, wherein the step of forming the buried low resistance region serving as the power supply path includes the step of implanting arbitrary impurity ions into a desired position of the semiconductor substrate. Device manufacturing method. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the step of forming the semiconductor layer comprises an epitaxial growth step.