JP2523506B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to semiconductor device technology, and further to a bipolar-MOS semiconductor integrated circuit in which a bipolar element and a MOS element are formed together in the same semiconductor substrate. The present invention relates to a technique effectively applied to a device, for example, a technique effectively applied to a high-speed and highly-integrated bipolar-CMOS S-RAM (static RAM).

[Prior Art] Recently, as described in, for example, "Nikkei Electronics, March 10, 1986 (no.390)", pages 199 to 217, published by Nikkei McGraw-Hill, a bipolar device and a CMOS are formed in the same semiconductor substrate. By forming a (complementary MOS) device together, a bipolar-CMOS type S-RAM has been developed which has both low power consumption and high speed.

FIG. 7 partially shows the device structure of the bipolar-CMOS type S-RAM studied by the present inventors.

The S-RAM shown in the figure is a p-type silicon semiconductor substrate (p
-Sub) 1 is used. In the p-type silicon semiconductor substrate 2, a p-conductivity type semiconductor region in which a p-type isolation diffusion layer (p-iso) 2 and a p-type well diffusion layer (p-well) 4 are vertically stacked, and an n + type buried layer. An (n-BL) 3 and an n-conductivity type semiconductor region in which an n-type well diffusion layer (n-well) 5 is vertically stacked are formed.

In the p-conductivity type semiconductor region, the n + type drain diffusion layer 9d,
The n + type source diffusion layer 9s, the gate electrode 11, and the like form n-channel MOS transistors Mn1 and Mn2. The n-channel MOS transistors Mn1 and M
A static memory circuit m is configured by using two n2 each. That is, the sources of the two MOS transistors Mn1 and Mn2 are commonly connected to the negative power supply V _EE side, and the drains of the two MOS transistors Mn1 and Mn2 are connected to the positive power supply V _CC through the load resistors R1 and R2, respectively.
Connect to. Further, by alternately connecting the drains and gates of both MOS transistors Mn1 and Mn2, a so-called set / reset type flip-flop circuit is configured. In this case, the resistance value of the load resistors R1 and R2 is
It is set to a very high value, for example, several giga Ω, in order to minimize the current that is constantly consumed. The storage unit (storage mat) 100 of the S-RAM is formed by arranging a large number of such storage circuits m.

On the other hand, in the n-conductivity type semiconductor region, the bipolar transistor Q for forming the peripheral circuit section 110 such as a decoder is formed.
1 and p-channel MOS transistors Mp1 and the like are formed.

The bipolar transistor Q1 is formed of an n + type collector current collecting diffusion layer (CN) 6, ap type base diffusion layer 7, an n + type emitter diffusion layer 8 and the like. C is a collector, B is a base, and E is an emitter. The bipolar transistor Q1 is used to form an output stage of a so-called bipolar-CMOS type logic circuit in which a bipolar element and a MOS element are combined.

The p-channel MOS transistor Mp1 includes a p + type drain diffusion layer 10d, a p + type source diffusion layer 10s, and a gate electrode.
Formed by 11 and so on. The p-channel MOS transistor Mp1 is used to form the logic portion and the preceding stage side of the bipolar-CMOS type logic circuit.

Bipolar-CMOS type S-RA partially shown in FIG.
In M, the memory unit 100 is composed of MOS transistors Mn1 and Mn2 which are excellent in low power consumption and suitability for high integration, while the peripheral circuit unit 100 is a bipolar-CMOS which is excellent in drivability.
Low power consumption and high speed can be achieved at the same time by using a positive logic circuit.

[Problems to be Solved by the Invention] However, the present inventor has clarified that the above-described technique has the following problems.

That is, for example, the S-RAM partially shown in FIG.
If the bipolar transistor Q1 of the peripheral circuit section 110 is saturated, the carriers may be injected into the p-type silicon semiconductor substrate 1. When this carrier injection occurs, part i of the carrier strays through the semiconductor substrate 1 and reaches the inside of the storage unit 100.
It acts to draw the leak current Ir from the n + type drain diffusion layer 9d of the n-channel MOS transistor Mn1 in 00.

From another perspective, as shown by the broken line in the figure, the potential in any of the n-conductivity type regions may relatively decrease due to the saturation operation of the bipolar transistor Q1. A parasitic npn bipolar transistor in which the n-conductivity type region in which the potential is lowered is used as the emitter, the substrate 1 is used as the base, and the n + -type drain diffusion layer 9d in the H (high level) state in the storage unit 100 is used as the collector. -Transistors Qs1, Qs2, Qs3 occur. If any one of these parasitic npn bipolar transistors Qs1, Qs2, Qs3 may occur, this causes the leak current Ir to flow out from the drain diffusion layer 9d in the H (high level) state. turn into.

Here, when the leak current Ir described above flows out from the drain of the n-channel MOS transistor Mn1 forming the memory circuit m, even if the leak current Ir that flows out is small, the H (high level) state of the drain is set. Sufficient to pull down to the L (low level) state. This is because its drain is connected to the positive power supply V _CC through extremely high resistance loads R1 and R2, for example, several giga Ω, as described above. Therefore, the drain thereof is easily pulled down from H (high level) to L (low level) even with a very small leak current Ir. As a result, the stored information held by the high and low drain potentials of the two n-channel MOS transistors Mn1 and Mn2 is easily destroyed.

As described above, for example, in the S-RAM shown in FIG. 7, the peripheral circuit section 110 to the storage section 100 are provided through the substrate 1.
It has been made clear by the present inventors that there is a problem that the stored information in the storage unit 100 may be partially destroyed by a stray carrier that reaches inside.

An object of the present invention is to provide a technique capable of reliably preventing the malfunction caused by the above-mentioned stray carrier.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is briefly described as follows.

That is, a separation region is formed that separates the entire semiconductor region, which is a portion where a circuit is apt to malfunction or destroy information by stray carriers in the semiconductor substrate, into two directions, lateral and downward. .

[Operation] According to the above-described means, even if the stray carrier is injected into the substrate, the stray carrier is restricted from moving into a certain region by the separation region. This achieves the purpose of surely preventing information destruction or malfunction in the storage section using MOS transistors.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor integrated circuit device to which the technique according to the present invention is applied.

The semiconductor integrated circuit device partially shown in the figure is basically an S-RAM similar to that shown in FIG.
The silicon semiconductor substrate (p-sub) 1 is used.

On the p-type silicon semiconductor substrate 1, a p-conductivity type semiconductor region in which a p-type isolation diffusion layer (p-iso) 2 and a p-type well diffusion layer (p-well) 4 are vertically stacked, and an n-type buried layer. (N-B
L) 3 and an n-type well diffusion layer (n-well) 5 are vertically stacked to form an n-conductivity type semiconductor region.

In the p-conductivity type semiconductor region, the n + type drain diffusion layer 9d,
The n + type source diffusion layer 9s, the gate electrode 11, and the like form n-channel MOS transistors Mn1 and Mn2. The n-channel MOS transistors Mn1 and M
A static memory circuit m is configured by using two n2 each. That is, the sources of the two MOS transistors Mn1 and Mn2 are commonly connected to the negative power supply V _EE side, and the drains of the two MOS transistors Mn1 and Mn2 are connected to the positive power supply V _CC through the load resistors R1 and R2, respectively.
Connect to. Further, by alternately connecting the drains and gates of both MOS transistors Mn1 and Mn2, a so-called set / reset type flip-flop circuit is configured. In this case, the resistance value of the load resistors R1 and R2 is
It is set to a very high value, for example, several giga Ω, in order to minimize the current that is constantly consumed. The storage unit (storage mat) 100 of the S-RAM is formed by arranging a large number of such storage circuits m.

On the other hand, in the n-conductivity type semiconductor region, the bipolar transistor Q for forming the peripheral circuit section 110 such as a decoder is formed.
1 and p-channel MOS transistors Mp1 and the like are formed.

The bipolar transistor Q1 is formed of an n-type collector current collecting diffusion layer (CN) 6, a p-type base diffusion layer 7, an n + -type emitter diffusion layer 8, and the like. C is a collector, B is a base, and E is an emitter. The bipolar transistor Q1 is used to form an output stage of a so-called bipolar-CMOS type logic circuit in which a bipolar element and a MOS element are combined.

The p-channel MOS transistor Mp1 includes a p + type drain diffusion layer 10d, a p + type source diffusion layer 10s, and a gate electrode.
Formed by 11 and so on. The p-channel MOS transistor Mp1 is used to form the logic portion and the preceding stage side of the bipolar-CMOS type logic circuit.

As described above, the memory unit 100 is composed of the MOS transistors Mn1 and Mn2 which are excellent in low power consumption and high integration suitability, while the peripheral circuit unit 100 is formed of a bipolar-CMOS type logic circuit which is excellent in drivability. By configuring, a bipolar-CMOS type S-RAM having both low power consumption and high speed is configured.

Here, in the S-RAM of the embodiment shown in FIG. 1, in addition to the configuration described above, a storage section in which the storage circuit m is formed.
A separation region 20 is formed that three-dimensionally separates the entire 100 from below and from the sides. The separation region 20 is composed of two first and second separation regions 21 and 22 formed so as to be connected to each other. The first isolation region 21 is formed so as to close the bottom of the storage unit 100 from below, thereby electrically isolating the storage unit 100 from the semiconductor substrate 1. The second isolation region 22 is formed so as to surround the side of the storage unit 100, thereby electrically isolating the storage unit 100 from the peripheral circuit unit 110. Further, in the embodiment, each of the first and second isolation regions 21 and 22 is formed of an n-conductivity type diffusion layer opposite to the p-conductivity type semiconductor region which is the semiconductor base of the memory section 100. ing. The diffusion layer forming the isolation region 20 (21, 22) is kept at a constant potential by being connected to the positive power source V _CC .

In the S-RAM configured as described above, carriers are injected into the substrate 1 due to, for example, the saturation operation of the bipolar transistor Q1 and some of the injected carriers are wandered in the substrate 1 to cause a memory portion. Even if an attempt is made to enter the inside of 100, the above-mentioned separation area 20 blocks the path of the entry from both lateral and downward directions.

Or, from a different point of view, even if a parasitic bipolar transistor Qs1 based on the substrate 1 is formed by the saturation operation of the bipolar transistor Q1 of the peripheral circuit section 110, etc.
The collector of the transistor Qs1 is formed not in the n + type drain diffusion layer 9d in the memory section 100 but in the isolation region 20 thereof.

In either case, the MOS transistor M that forms the memory circuit m
No leakage current Ir is drawn from the drain diffusion layers 9d of n1 and Mn1. In this way, information destruction or malfunction in the storage unit 100 using the MOS transistors Mn1 and Mn2 can be reliably prevented.

Next, an embodiment of a method of manufacturing the semiconductor integrated circuit device having the above structure will be described.

FIGS. 2A to 2E show the first embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of its main steps.

In FIG. 2A, in FIG. 2A, a silicon step 23 is formed by oxidizing a p-type silicon semiconductor substrate (p-sub) 1 using a pattern of a nitride film (not shown) as a mask. It shows a state in which phosphorus P, which is an n-conductivity imparting substance, is doped by ion implantation after the film is removed. The silicon step 23 serves as a mark when aligning the photoresist pattern in the next process and thereafter with the isolation region 23. As a result, the first isolation region 21 of the n-type diffusion layer is formed.

After the oxide film 12 is completely removed, a mask pattern composed of the oxide film 12 'and the nitride film 13 is formed as shown in FIG.

Then, as shown in (c), the n + type buried layer 3 is selectively diffused / formed.

Next, as shown in (d), the p-type isolation diffusion layer 3 is selectively formed by ion-implanting boron B, which is a p-type conductivity imparting substance, using the partial oxide film 12 as a mask.

Then, as shown in (e), the p-type well diffusion layer (p
-Well) 4 and an n-type well diffusion layer (n-well) 5 are formed. In the p-type well diffusion layer 4, an n-channel MOS transistor Mn1 is formed by the n + -type drain diffusion layer 9d and the n + -type source diffusion layer 9s. In the n-type well diffusion layer 5, an npn bipolar transistor Q1 is formed by the p-type base diffusion layer 7, the n + type emitter diffusion layer 8, the collector current collecting n + type diffusion layer (CN) and the like. Further, in the n-type well diffusion layer 5, a p-channel MOS transistor Mp1 is formed by the p + -type drain diffusion layer 10d and the p + -type source diffusion layer 10s. 14 indicates an electrode made of polycrystalline silicon or the like.

The p-type well diffusion layer of the n-channel MOS transistor is formed by connecting the collector current collection diffusion layer (CN) and the n + type buried layer (NBL) to the n-type isolation region (N-iso). It can be separated from other p-type regions.

By the steps as described above, the first isolation region 21 formed of the n-type isolation diffusion layer and the second isolation region 22 formed of the n + type buried layer 3 and the collector current collecting n + type diffusion layer 6 are formed. The semiconductor integrated circuit device shown is formed.

FIGS. 3A to 3E show a second embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of its main steps.

In FIG. 3, as shown in (a), a photoresist 15 is formed on the p-type silicon semiconductor substrate (p-sub) 1.
Using the nitride film 13 as a mask, phosphorus P, which is an n-conductivity imparting substance, is selectively doped by ion implantation. As a result, the first isolation region 21 of the n-type diffusion layer is formed.

After this, oxidation is performed to form a silicon step 23 that indicates the position of the isolation region 21, and thereafter, in (b) to (e), the same steps as those in FIGS. 2 (b) to (e) are performed.

According to the manufacturing method shown in FIGS. 3 (a) to 3 (e), as shown in FIG. 3 (c), the silicon step difference 24 generated when the buried layer (NBL) is formed is the n-type isolation region. (N-is
n) an n-type isolation region (N
-Iso) is formed so as to compensate for the subsidence.

Therefore, there is an advantage that the step difference between the n-channel MOS transistor Mn1 and the bipolar transistor Q1 and the p-channel MOS transistor Mp1 can be made smaller, and the processing variations of the gate and the like in the subsequent photoresist process can be reduced.

FIGS. 4A to 4F show a third embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of its main steps.

In FIG. 4, as shown in (a), a thick oxide film 1 is formed on a p-type silicon semiconductor substrate (p-sub) 1.
After 2 is selectively removed by a photoresist process, the oxide film 12 is used as a mask to selectively dope the phosphorus P which is an n-conductivity imparting substance by ion implantation. This allows
The first isolation region 21 is formed by the n-type diffusion layer.

After that, as shown in (b), the oxide film 12 on the surface is grown. Then, n forming the first isolation region 21
Due to the growth of the oxide film 12, the semiconductor surface of the mold diffusion layer forms a silicon step 23 indicating the position of the isolation region 21 in a direction receding downward from the periphery thereof. Then, next, the oxide film 12 is frontally removed.

After this, in (c) to (f), the same steps as in FIGS. 2 (b) to (e) are performed.

In the manufacturing method shown in FIGS. 3A and 3B, in the step (d), boron is doped using the oxide film on the buried layer (NBL) as a mask to form the p-type isolation region (p-iso).
Must be self-aligned with the buried layer (NBL) pattern. Therefore, the n-type isolation region (N-is
o) The oxide thickness above should be less than half of the oxide thickness above the buried layer (NBL). As a result, the silicon step 23 is
It can be formed in less than half of the silicon step 24.

However, according to the manufacturing method shown in FIGS. 4A to 4F, the size of the silicon step 23 can be determined regardless of the silicon step 24.

Therefore, similar to the embodiment shown in FIG. 3, the step difference between the n-channel MOS transistor Mn1 and the bipolar transistor Q1 and the p-channel MOS transistor Mp1 is further reduced, and the processing variations in the subsequent photoresist process are performed. The advantage of being able to prevent is obtained.

FIGS. 5A to 5F show a fourth embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of its main steps.

In FIG. 5, as shown in (a), a photoresist 15 is formed on the p-type silicon semiconductor substrate (p-sub) 1.
Using the nitride film 13 as a mask, phosphorus P, which is an n-conductivity imparting substance, is selectively doped by ion implantation. As a result, the first isolation region 21 of the n-type diffusion layer is formed.

After that, as shown in (b), the oxide film 12 on the surface is grown. Then, n forming the first isolation region 21
Due to the growth of the oxide film 12, the semiconductor surface of the mold diffusion layer forms a silicon step 23 indicating the position of the isolation region 21 in a direction receding downward from the periphery thereof.

After removing the oxide film on the front side, in (c) to (f),
The same steps as those in FIGS. 2B to 2E are performed.

In the manufacturing method shown in FIGS. 3A to 3E, in the step (d), boron P is doped using the oxide film on the buried layer (NBL) as a mask, so that the p-type isolation region (p -Iso) region must be formed, so n
The oxide film thickness on the mold separation region (N-iso) is the same as the buried layer (NBL).
Must be less than half of the above oxide thickness. For this reason, the silicon step difference 23 can be formed only to less than half of the silicon step difference 24.

However, in the manufacturing method shown in FIG. 5, since the oxide film 12 is frontally removed after the step (b), the silicon step 23
Can be determined regardless of the silicon step 24.

Therefore, there is an advantage that the step difference between the n-channel MOS transistor Mn1 and the bipolar transistor Q1 and the p-channel MOS transistor Mp1 can be reduced to prevent the processing variation in the subsequent photoresist process. .

FIGS. 6A to 6C show a fourth embodiment of the semiconductor integrated circuit manufacturing method according to the present invention in the order of its main steps.

In the manufacturing method shown in FIG. 6, first, as shown in FIG. 6A, the p-type isolation diffusion layer 2 and the n + type buried layer 3 are formed in predetermined regions on the p-type silicon semiconductor substrate 1.

Next, as shown in (b), using the photoresist 15 as a mask, only the p-type isolation diffusion layer 2 in which the n-channel MOS transistor Mn1 is formed is selectively ionized with arsenic As, which is an n-conductivity imparting substance. Type in.

Thereafter, as shown in FIG. 7C, the p-type isolation diffusion layer 2 and the n + type buried layer 3 are doped with the p-type well diffusion layer (p-well) 4 and the n-type well diffusion layer (n −we
ll), when it is stretched and diffused, the diffusion coefficient of arsenic As ion-implanted in the p-type separation diffusion layer 2 is smaller than that of boron B, which is the conductivity imparting substance of the p-type separation diffusion layer 2. As a result, the n-type diffusion region forming the first isolation region 21 is formed in the p-type isolation diffusion layer 2.

As a result, in the embodiment shown in FIG. 6, the semiconductor integrated circuit device having the structure shown in FIG. 1 can be obtained without increasing the number of steps.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Not even. For example, the second isolation region 22 may be formed by a groove.

In the above description, the invention made by the present inventor is a field of application which is the background of the invention, and is bipolar-CMOS.
However, the present invention is not limited to this. For example, a pure MOS type S-RAM is used.
Alternatively, it can be applied to logic semiconductor integrated circuit devices other than S-RAM.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the stray carrier in the substrate is provisionally constructed by separating the entire semiconductor region of the portion where the circuit is apt to be erroneously operated or information is destroyed by the carrier straying in the semiconductor substrate from the lateral and lower directions. Even if the data is injected, it is possible to reliably prevent information destruction or malfunction in the circuit.

[Brief description of drawings]

1 is a partially exaggerated sectional view showing an embodiment of a main part of a semiconductor integrated circuit device to which the technique according to the present invention is applied, and FIGS. 2 (a) to 2 (e) show the configuration shown in FIG. FIG. 3 is a diagram showing a first embodiment of a method of manufacturing a semiconductor integrated circuit device having the same, and FIGS. FIGS. 4A to 4F are diagrams showing an example of the order of steps, and FIGS. 4A to 5F are diagrams showing the step of the third embodiment of the method for manufacturing a semiconductor integrated circuit device having the configuration shown in FIG. ) To (f) are views showing a fourth embodiment of the method of manufacturing the semiconductor integrated circuit device having the structure shown in FIG. 1 in the order of steps, and FIGS. 6 (a) to (c) are shown in FIG. FIG. 7 is a diagram showing a fifth embodiment of a method of manufacturing a semiconductor integrated circuit device having a structure in the order of steps, and FIG. 7 is a semiconductor examined prior to the present invention It is a partial cross-sectional view of a NAND circuit device. 1 ... p-type silicon semiconductor substrate, 2 ... p-type isolation diffusion layer (p-iso), 3 ... n + type buried layer (n-BL), 4 ...
... p-type well diffusion layer (p-well), n-type well diffusion layer (n-well), 6 ... n + type collector current collection type diffusion layer (CN), 20 ... storage unit 100 and peripheral circuit unit 110 From the three-dimensional separation region, 21 ... First isolation region (n-type diffusion layer), 22 ... Second isolation region (n-type diffusion layer), Mn1, Mn2
... n-channel MOS transistor forming the memory circuit m, Q1 ... bipolar transistor formed in the peripheral circuit section 100, Mp1 ... p-channel MOS transistor formed in the peripheral circuit section 110.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Osamu Saito 4026 Kujimachi, Hitachi, Hitachi, Ibaraki Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Tetsuya Tsurumaru 111, Yokoyokocho, Takasaki, Gunma Prefecture Hitachi Ltd. Takasaki Factory (56) References JP-A-58-7860 (JP, A) JP-A-58-225666 (JP, A)

Claims (1)

(57) [Claims] 1. A semiconductor substrate of the first conductivity type is provided with a first well of the first conductivity type and second and third wells of the second conductivity type having a conductivity type opposite to the first conductivity type. A bipolar transistor is formed in the second well, a second conductivity type channel MOS transistor forming a memory cell is formed in the first well, and a first conductivity type channel MOS transistor is formed in the third well. A first conductive isolation layer of the same conductivity type as that of the first well is formed at the bottom of the first well, and a second conductive type first isolation layer is formed under the first conductive isolation layer. And a second conductive type second separation layer in contact with the first separation layer is formed so as to surround the first well and the first conductive separation layer together with the first separation layer. Characteristic semiconductor device.