JPH02201952A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit being minute and having high-speed as well as high reliability by providing an n-channel MOSFET wherein a drain is connected to a base of a pnp type bipolar transistor, a source is connected to a second power supply end, further a gate is connected to an input end respectively. CONSTITUTION:An n-channel MOSFET T2, wherein a drain 5 is connected to a base 8 of a pnp-type bipolar transistor Q2, a source 6 is connected to a second power supply end and a gate 2 is connected to an input end A of a signal, is provided. Accordingly, the n-channel MOSFET T2, becomes a source- grounded type for being not influenced by base potential so as to be sufficiently driven while speeding up a function. Further, by replacing a bipolar transistor for load driving to be connected to this n-channel MOSFET T2 with a pnp-type bipolar transistor Q2, electrical separation can be made by pn junction for being miniaturized even without forming an element isolation region. Thereby, a semiconductor integrated circuit being minute having high-speed operation and high reliability can be obtained.

Description

[Detailed Description of the Invention] CObject of the Invention] (Industrial Application Field) The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and particularly relates to a semiconductor integrated circuit and a method for manufacturing the same, and in particular to an npn-type and pnp-type bipolar transistor, an n-channel, and a p-channel. The present invention relates to a semiconductor integrated circuit in which MOSFETs are mixed on the same chip, and a method for manufacturing the same.

(Prior Art) Hereinafter, an inverter gate circuit composed of a conventional CMO 8 and an npn type bipolar transistor will be described with reference to FIG.

FIG. 4 is a circuit diagram of a typical conventional inverter gate composed of a CMO3 and an npn type bipolar transistor.

As shown in FIG. 4, this inverter gate circuit consists of an npn bipolar transistor Q101 for driving the load.
The emitter 105 of the npn bipolar transistor Q102 and the collector 106 of the npn bipolar transistor Q102 are each of a totem pole type connected at a node d. Also, the base 101 of the npn bipolar transistor QIOI is p
It is connected to the drain 1o3 of channel MOSFET, T101, and is a p-channel MOSFET.

Driven by T101. Conventionally, four transistors, T101 and Tl, constitute this inverter gate circuit.
O2, Q101, Q102 i, t were formed in independent element regions on the semiconductor substrate. As a result, the element isolation region has increased, and the area occupied on the semiconductor chip in such an inverter gate circuit has increased. Also, n-channel MOSFET, TlO2
is a source current supply type, and is influenced by the base potential VB of the npn bipolar transistor Q102 during operation. That is, an n-channel MOSFET.

The effective gate potential of TlO2 is the difference between the input potential VIN input to the gate and the base potential VB of the npn bipolar transistor Q102. For this reason, the n-channel MOSFET TlO2 has the disadvantage that it cannot be driven sufficiently. This n-channel MOSFE
T.

If TlO2 is not driven sufficiently, the collector current of npn bipolar transistor Q102 becomes small,
The operation of the inverter gate circuit becomes slow. This drawback becomes especially noticeable at low power supply voltages. Furthermore, since the collector 106 of the npn bipolar transistor Q102 is connected to the node d,
Its collector potential varies depending on the input/output level. From this, the collector 106 is connected to the other transistor Q10.
1. Must be electrically isolated from TlOI and TlO2. That is, although they have the same conductivity type, they cannot share the collector region with Q101, which is the same npn bipolar transistor. Therefore, it is necessary to isolate the elements, and as a result, the element isolation area has increased.
This made it difficult to miniaturize the inverter gate circuit.

(Problem to be solved by the invention) This invention was made in view of the above points, so
Conventionally, in a semiconductor integrated circuit such as an inverter gate circuit composed of an O5 and a bipolar transistor, each transistor is formed in an independent element region, and especially in a bipolar transistor, the collector potential changes depending on the input/output level. To improve the problem that an element isolation region was required due to fluctuations in the voltage, and that the n-channel MOSFET, which is a source current supply type, could not be driven sufficiently due to the influence of the base potential of the npn bipolar transistor. The purpose of the present invention is to provide a semiconductor integrated circuit that is fine, operates at high speed, and has high reliability, and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) According to the semiconductor integrated circuit according to the present invention, the source is the first
a p-channel MOSFET whose gate is connected to the first power supply end of the p-channel MOSFET, whose gate is connected to the signal input end; whose base is connected to the drain of this p-channel MOSFET, whose collector is connected to the first power supply end, and whose emitter is connected to the signal input end; a pnp bipolar transistor whose emitter is connected to the output terminal of the signal and whose collector is connected to the second power supply terminal; n-channel M connected to the base of the transistor, the source connected to the second power supply terminal, and the gate connected to the input terminal of the signal
It is characterized by comprising an OSFET.

(Function) In the semiconductor integrated circuit as described above, the n-channel MOSFET is conventionally of the source current supply type, and is influenced by the base potential of the npn bipolar transistor.
The point where it could not be driven sufficiently becomes a common source type and is no longer affected by the base potential, so it can be driven sufficiently and the operation becomes faster. Also, this n-channel MOS
By replacing the load driving bipolar transistor connected to the FET with a pnp bipolar transistor, the collectors, which were conventionally of the same conductivity type, were electrically separated by forming an element isolation region. Since these are of opposite conductivity types, they can be electrically isolated by pn junction isolation without forming an element isolation region, resulting in miniaturization. Furthermore, p-channel MO8, which is of the same conductivity type,
By integrating the drain of a FET and the base of an npn bipolar transistor, and by integrating the drain of an n-channel MOSFET and the base of a pnp bipolar transistor, it becomes possible to miniaturize the -layer, making it possible to The number can also be reduced.

Furthermore, the number of contacts can be further reduced by integrally forming the emitter electrodes of npn type and pnp type bipolar transistors, and by integrally forming the gate electrodes of n channel and n channel MOSFET. If these layout measures are taken, further miniaturization will be achieved, operation will be faster, reliability will be improved, and manufacturing yield will also be improved.

(Embodiment) Hereinafter, a semiconductor integrated circuit and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an inverter gate circuit according to an embodiment of the present invention, FIG. 2 is a plan view of the inverter gate circuit, and FIGS. 3(a) to 3(e) are FIG. 3 is a cross-sectional view showing the order of manufacturing steps of the inverter gate circuit.

First, in the inverter gate circuit shown in FIG. 1, the input voltage VIN is supplied to the input terminal A.

This input terminal A is connected to node a. This node a is connected to the gate 1 of the p-channel MOSFET, TI,
It is connected to the gate 2 of the n-channel MOSFET T2. Of these two MOSFETs, TI, T2, source 3 of the p-channel MO5FET, TI, is connected to node b. This node b is connected to the power supply voltage supply terminal C. This power supply voltage supply terminal C has 1
j: & Original voltage VDD is supplied. Also, p channel M
The drain 4 of the OSFET Tl is connected to the base 7 of an npn-type or dipolar transistor Q1. On the other hand, an n-channel type MOS FET.

The source 5 of T2 is connected to the base 8 of a pnp bipolar transistor Q2.

Further, the source 6 is grounded. MOSF based
Among the two bipolar transistors Q1 and Q2 to which the drains of ET, TI, and T2 are connected, the collector 9 of the npn bipolar transistor Q1 is connected to the power supply voltage VD.
It is connected to node b, which is supplied with D. Further, the emitter 10 is connected to the node C. This node C
is connected to output terminal B. The output terminal B has an output voltage V. UT is supplied. On the other hand, pnp bipolar
The emitter 8 of transistor Q2 is also connected to node C. Further, the collector 12 is grounded.

According to such an inverter gate circuit, the source 6 of the n-channel MOSFET T2 is directly grounded. Therefore, the drop in gate potential that conventionally occurs due to the base of the npn bipolar transistor being connected to the source of the n-channel MOSFET is eliminated.

Further, by using a pnp type bipolar transistor Q2 instead of the conventional npn type, inverter operation is possible even without a source current supply type transistor. By preventing the source current supply type in this way, the effective input potential of the gate of n-channel MOSFET T2 is
It becomes the input voltage VIN itself. From this, a larger base current can be supplied to the base 11 of the pnp bipolar transistor Q2 connected to the drain of the n-channel MOSFET T2.

Therefore, the pnp type bipolar transistor Q2 can drive a larger collector current, and the operation speed of the inverter gate circuit can be further increased. Conventionally, since the collector potential fluctuates depending on the input/output level, the npn bipolar transistor Q102
electrically connects the collector 106 of Q10 to another transistor Q10.
1. TlO2 must be separated from TlO2, i.e. npn bipolar transistor Q101
, they cannot share a collector region of the same conductivity type. Therefore, the need for an element isolation area also
As shown in FIG. 1, since the collector of the pnp bipolar transistor and the collector of the npn bipolar transistor are of opposite conductivity types, pn junction isolation becomes possible and there is no need to form an element isolation region.

For these reasons, the operation of the inverter gate circuit can be increased in speed and miniaturized.

Further, according to an embodiment of the present invention, in order to achieve higher speed and miniaturization of the operation of the - layer inverter gate circuit, the layout of the semiconductor element is devised.

Hereinafter, the layout of this inverter gate circuit will be explained with reference to the plan view of FIG. 2, and the manufacturing method of the inverter gate circuit will be explained with reference to FIGS. 3(a) to 3(e). explain.

FIG. 2 and FIGS. 3(a) to 3(e) show an inverter gate circuit formed on the surface of a p-type semiconductor substrate with an improved layout. The inverter gate circuit with this layout design may be formed on the surface of an n-type semiconductor substrate of the opposite conductivity type.

First, in Fig. 2, Fig. 3(a) to Fig. 3(e)
Although shown in the figure, a high concentration n-type buried diffusion layer and a high-concentration p-type buried diffusion layer are formed in a region of the p-type semiconductor substrate not shown in the figure. Furthermore, a p-type epitaxial layer 20 is formed on the p-type semiconductor substrate. In this p-type epitaxial layer 20, an n-type well region 21 is formed on and in contact with the high concentration n+ type buried diffusion layer (not shown). Similarly,
A p-type well region 22 is formed on and in contact with the high concentration p-type buried diffusion layer (not shown). Among these well regions, first, in the n-type well region 21, a high-concentration n+ type collector compensation diffusion layer 23 is formed so as to penetrate into the high-concentration n+ type buried diffusion layer (not shown). has been done. A contact hole 24 is opened in this high concentration n+ type collector compensation diffusion layer 23 through an oxide film not shown in the figure.

In this contact hole 24, a collector electrode (not shown) is formed in contact with the highly doped n+ type collector compensation diffusion layer 23. This high concentration n÷ type collector compensation diffusion layer 23
, the high-concentration n-type buried diffusion layer, and a region of the n-well region 21 form the collector region of the npn-type bipolar transistor.

The reason why this is referred to as one region of the n-well region 21 is because a p-channel MO8FET is further formed within this n-well region 21, as will be described later. Further, in the n-type well region 21, a heavily doped p÷-type source diffusion region 25 of the opposite conductivity type is formed. A contact hole 29 is opened in this heavily doped p-type source diffusion region 25 through an oxide film not shown in the figure. In this contact hole 29, a source electrode (not shown) is formed in contact with the highly doped p÷ type source diffusion region 25. Furthermore, in the n-type well region 21, there is a high concentration p of the opposite conductivity type.
A ten type drain diffusion region 26 and a low concentration p- type base diffusion region 27 which is integrated with the high concentration p ten type drain diffusion region 26 are formed. The boundary between the high concentration p÷ type drain diffusion region 26 and the low concentration p− type base diffusion region 27 is shown as a boundary line 42. Among these, a high concentration n+ type emitter diffusion region 28 is formed in the low concentration p'' type base diffusion region 27. This high concentration n+
A contact hole 30 is formed in the type emitter diffusion region 28 through an oxide film not shown in the figure.

In this contact hole 30, an emitter electrode 31 made of n-type polysilicon is formed in contact with the heavily doped n+ type emitter diffusion region 28. This emitter electrode 31 is formed integrally with an emitter electrode 41 made of p-type polysilicon of a pnp-type bipolar transistor formed in the p-type well region 22, as will be described later. That is, the emitter electrode is located in the n-type well region 2.
an npn bipolar transistor formed in 1;
This is common to a pnp type bipolar transistor formed in a p type well region. A contact hole 32 is formed in the emitter electrode 44 through an oxide film not shown in the figure. An emitter extraction electrode (not shown in the figure) is formed in this contact hole 32 in contact with an emitter electrode 44 .

On the other hand, in the p-type well region 22, a high-concentration p-type collector compensation diffusion layer 33 is formed so as to penetrate into the high-concentration p-type buried diffusion layer (not shown). A contact hole 34 is formed in this highly doped p-type collector compensation diffusion layer 33 through an oxide film (not shown in the figure). A collector electrode (not shown) is formed in this contact hole 34 in contact with the highly doped p-type collector compensation diffusion layer 33 . The highly doped p-type collector compensation diffusion layer 33, the highly doped p-type buried diffusion layer, and a region of the p-well region 22 form the collector region of the pnp-type bipolar transistor. Here, the region mentioned as one region of the p-well region 22 is described later, but this p-well region 2
This is because an n-channel MOSFET is further formed within 2. Further, in the p-type well region 22, a high concentration n-sized small source diffusion region 35 of the opposite conductivity type is formed. A contact hole 39 is opened in this high concentration n small source diffusion region 35 through an oxide film not shown in the figure. In these three contact holes, source electrodes (not shown) are formed in contact with the high concentration n small source diffusion region 35. Furthermore, within the p-type well region 22, there is a highly doped p-type drain diffusion region 36 of the opposite conductivity type, and a low-concentration p-type base diffusion region 37 that is integrated with the high-concentration n0-type drain diffusion region 36. is formed. The boundary between the high concentration n-type drain diffusion region 36 and the low concentration p-type base diffusion region 37 is shown as a boundary line 43. Of these, the low concentration n-type base diffusion region 37
A heavily doped p+ type emitter diffusion region 38 is formed therein. In this high concentration p-type emitter diffusion region 38,
A contact hole 40 is opened through the oxide film, which is not shown in the figure. This contact hole 4o has p
An emitter electrode 41 made of type polysilicon is formed in contact with the high-4 degree p-type emitter diffusion region 38 . As described above, this emitter electrode 41 is formed integrally with the emitter electrode 31 made of n-type polysilicon of the npn-type bipolar transistor formed in the n-type well region 21. Also, M.O.
The gate electrode 45 of SFET is a p-channel part
This is common to SFET and n-channel MO5FET. This common gate electrode 45 is provided with a channel portion formed between the source diffusion region 25 and drain diffusion region 26 of each p-channel MO5FET via a gate oxide film (not shown).
p-channel NfOsFET gate electrode section 45' and n
An n-channel MOSFET gate electrode section 45' is provided between the source diffusion region 35 and drain diffusion region 36 of the channel MO8FET so that a channel portion is formed through a gate oxide film (not shown). ing. In the common gate electrode 45 where these two gate electrode parts are provided, 158 contact holes 46 are formed through an oxide film (not shown). A gate lead-out electrode (not shown) is formed in this contact hole 46 so as to be in contact with the common gate electrode 45 .

In this way, in the n-type well region 21, the n-channel M
The drain 26 of the OSFET and the base 27 of the npn bipolar transistor are formed integrally. On the other hand, in the p-type well region 22, there is an n-channel MOSFET.
The drain of the pnp bipolar transistor and the base of the pnp bipolar transistor are formed integrally. Furthermore, as described above, since the collector region is of the opposite conductivity type, pn junction isolation is possible without requiring an element isolation region.

Furthermore, these two well regions 21 and 22,
By symmetrically arranging the respective elements formed, the emitter electrodes of the npn bipolar transistor and pnp bipolar transistor can be integrated at the shortest distance, and the n-channel MOSFET and n-channel MOSFET can be integrated. The gate electrode of ET can be formed integrally. That is, since the interconnections between the regions are made at the shortest distance, the elements can be further miniaturized, and the number of contacts can be reduced, so that the operation speed of the - layer can be increased. Furthermore, the yield is also improved.

In the layout shown in FIG. 2 as described above, the input end A shown in FIG. 1 is connected to the gate electrode through the contact hole 46, the output end B is connected to the emitter 28, 38 through the contact hole 32, and the power supply voltage The supply end C is connected to the collector 23 through the contact hole 24 . This power supply voltage supply end C is connected to the source 25 through the contact hole 29.
is also connected to. A ground potential is connected to collector 33 through contact hole 34 , and this ground potential is also connected to source 35 through contact hole 39 . Also, n
Even if the source 35 of the channel MOSFET is not connected to the power supply voltage supply terminal C, it is also possible to connect it to the second ground potential, that is, for example, a minus number of V, and take out a potential different from that of the collector 23. With such a connection means, the back gate bias can be applied to the n-channel MOSFET.
can be applied to reduce the capacitance, making it possible to further increase the speed of operation and improve reliability. Furthermore, 9M
The source 25 of the OSFET is also set to the second ground potential, that is, higher than the collector 33 by a positive number of V.
It is also possible to take out a potential different from that of 3, and similarly, it is possible to speed up the operation of the - layer and improve reliability.

Next, referring to FIGS. 3(a) to 3(e), the second
A method of manufacturing the inverter gate circuit shown in the figure will be described. In FIGS. 3(a) to 3(e), the reference numerals correspond to each other.

First, as shown in FIG. 3(a), a p-type semiconductor substrate 17
A high concentration n+ type buried diffusion layer 18 is formed at a predetermined location by, for example, solid phase diffusion of antimony (Sb). At this time, the surface concentration is 1018-1020cI1
It is desirable that the sheet resistance is about 1-3, and the sheet resistance is 100Ω/hole or less. Next, a high concentration p-type buried diffusion layer 19 is formed by, for example, boron (B) ion implantation and thermal diffusion. At this time, the surface concentration is 1017~1020c1
It is controlled so that it becomes 1-3. Next, a pu, r-bitaxial layer 20 is formed by, for example, a CVD method. At this time, the concentration is preferably about 1015 to 1017cIII-3, and the thickness is preferably 31 or less.

Next, as shown in FIG. 3(b), the epitaxial layer 2
A low concentration n-type well region 21 is formed on the surface of the substrate 0 by ion implantation and thermal diffusion so as to overlap the high concentration n-type buried diffusion layer 18.

Next, similarly, a high concentration p-type buried diffusion layer 1 is formed on the surface of the epitaxial layer 2o by ion implantation and thermal diffusion.
A low concentration p-type well region 22 is formed so as to overlap with 9. When forming these well regions 21 and 22, it is better to shorten the time of the thermal diffusion process as much as possible. This is to prevent sagging due to diffusion of the n<0> type buried diffusion layer 18 and the p<0> type buried diffusion layer 19. Alternatively, the p type epitaxial layer 20 may be used without forming the p'' type well region.

Next, as shown in FIG. 3(C), the epitaxial layer 2
LO at a predetermined location on the 0 surface using, for example, a selective oxidation method.
A field oxide film 47 is formed as an element isolation region by the CO5 method. Next, a collector compensation diffusion layer 23 is formed at a predetermined location in the n-type well region 21 by ion implantation and thermal diffusion so as to penetrate into the n+ type buried diffusion layer 18. Next, by ion implantation and thermal diffusion, p÷
A collector compensation diffusion layer 33 is formed so as to pierce the mold-buried diffusion layer 19. Next, a thin oxide film that will later become a gate oxide film is formed over the entire surface by, for example, thermal oxidation.

Next, through this oxide film, ions are implanted to control the threshold values of the MOSFETs.
The method is applied to at least the channel region of the nMOSFET formed in the first embodiment. Next, a gate material such as polysilicon is deposited over the entire surface by, for example, a CVD method. Next, a photoresist (not shown) is applied to the entire surface. Then, the photoresist is developed into a predetermined shape by photolithography, and using the photoresist as a mask, the polysilicon layer and the thin oxide film are sequentially etched to form the gate electrode 45' of the pMOSFET and its gate oxide film 48. , and a gate electrode 45' of the nMOS FET and its gate oxide film 48' are formed.

In addition to the above-mentioned polysilicon, gate materials include
Silicide, metal, or the like may be used. next,
For example, arsenic (
A source diffusion region 35 and a drain diffusion region 36 are formed by selectively performing ion implantation of As). At this time, since the drain diffusion region 36 also serves as the base diffusion region 37 of the pnp type bipolar transistor, in order to reduce the number of steps, the base diffusion region 37 may also be formed at the same time in a -degree ion implantation step. is desirable. At this time, the final impurity profile is the base diffusion region 37
It is better to make it desirable. n M OS F E
The impurity profile of the drain region 36 of T is 1 to
Although the concentration is lowered by about two orders of magnitude, this disadvantage is not large. This is because the drain resistance does not affect the characteristics of the MOSFET, and because the impurity concentration is lowered and the impurity profile becomes sloppy, the local concentration of the drain electric field is alleviated and more reliable nMOS FET
This is because it brings about Further, the source diffusion region 35 and the drain diffusion region 36 may be formed simultaneously.

In this case, it is necessary to form the base diffusion region 37 in a separate ion implantation process. Next, ions of boron (B) or boron fluoride (BF2), for example, are selectively implanted into predetermined source and drain locations of the 2MO5FET in the n'' type well region 21. , and a drain diffusion region 26. At this time, since the drain diffusion region 26 also serves as the base diffusion region 27 of the npn type bipolar transistor, the base diffusion region 27 is
At the same time, it is desirable to form the ion implantation step by a second ion implantation process. At this time, it is preferable that the final impurity profile is desired for the base diffusion region 27. 9MOSFE
The impurity profile of the drain region 26 of T is 1 to 2.
Although the concentration is lowered by an order of magnitude, this disadvantage is not large.

This is because the drain resistance does not affect the characteristics of the MOSFET, and because the impurity concentration is lowered and the impurity profile is sloping, local concentration of the drain electric field is alleviated, resulting in a more reliable MOSFET. It is empty. In addition, the Sos diffusion region 25 and the drain diffusion region 26
may be formed at the same time. In this case, it is necessary to form the base diffusion region 27 in a separate ion implantation process.

Next, as shown in FIG. 3(d), for example, CV
An insulating film 49 such as an oxide film is formed by method D. next,
Contact holes 30 and 4o are formed in predetermined emitter formation regions in the n-type well region 21 and the p-type well region 22 by, for example, photolithography using photoresist. Next, a conductive material for the emitter common electrode, usually polysilicon, is deposited over the entire surface by, for example, CVD. For example, arsenic (As) is ion-implanted into the npn-type bipolar transistor formation region formed in the polysilicon n-type well region 21, and thermally diffused (from polysilicon) into the p-type base diffusion region 27. (solid phase diffusion) to form a high concentration n+ type emitter diffusion region 28. Next, a pnp bipolar transistor formation region formed in this polysilicon p-type well region 22 is filled with, for example, boron (B).
) or ion implantation of boron fluoride (FB2),
By thermally diffusing (solid-phase diffusion from polysilicon) into the n-type base diffusion region 37, a high concentration p-type emitter diffusion region 38 is formed. Thermal diffusion steps for forming these emitter diffusion regions 28 and 38 are preferably performed at the same time. Furthermore, instead of diffusion from polysilicon, at least one may be formed directly by ion implantation and thermal diffusion. In addition to polysilicon, conductive materials include metal, polycide, silicide, and even MBE technology (Molecular
Beava Epltaxy) may also be used. Among these, in the case of metal, particularly aluminum (AI), it is necessary to perform hayon implantation directly into the base diffusion regions 27 and 37 when forming the emitter diffusion regions 28 and 38. Of course, both or one of pn, pSn, and pn may be made of aluminum. Next, the polysilicon is buttered into a predetermined shape by photolithography using photoresist, for example, and
An emitter common electrode 44 is formed. As described above, this emitter common electrode 44 has n-type impurities ion-implanted onto the n''-type well region 21 and p-type impurities into the p-type well region 22. Roughly at the top of each region, an n-type polysilicon emitter electrode 31 and a p-type polysilicon emitter electrode 41 are formed.

Next, as shown in FIG. 3(e), for example, CV
An insulating film 50, such as a BPSG film, is deposited by the D method and planarized by reflowing. Next, through this insulating film, by photolithography using, for example, photoresist, collector contact holes 24 and 34, source contact holes 10 and 32, emitter contact holes 32, and the like shown in FIG. Figures 3(a) to 3rd
A gate contact hole (not shown in FIG. 3(e)) is formed. Next, the circuit connections shown in FIG. 1 are formed by depositing and patterning a metal material, usually aluminum (AI), on the entire surface by sputtering, for example. First, the VDD wiring for the power supply voltage is connected to the electrode 51 in the figure. The voUT wiring is connected to electrode 5 in the same figure.
Connected to 2. The ground wire is connected to electrode 51'. Here, the electrode (gate electrode) to which the VIN wiring is connected
is not shown.

Note that the p-type or n+ type buried diffusion layer 18 and 1
In the formation of the epitaxial layer 20, either one of them, for example, the p-type buried diffusion layer, may be formed after the epitaxial layer 20 is formed. By carrying out this process in a later step, the p-type buried diffusion layer can be prevented from sagging due to the thermal process. - An example is after forming the isolation region 47.

Boron (B) is applied after forming a thick mask material in a predetermined area.
ion implantation. At this time, to the specified depth,
The ion accelerating voltage is chosen. Generally, when the depth is 1.5-, an acceleration voltage on the order of Mev is required. Further, the ion implantation region is activated by the subsequent heat treatment. In addition, in the case of an n÷ type buried diffusion layer, phosphorus (P)
, or use arsenic (As).

By such a manufacturing method, an inverter gate circuit with an improved layout according to an embodiment of the present invention is manufactured.

In the above embodiment, the npn type and pnp type bipolar transistors are formed as vertical bipolar transistors, but at least one of them may be formed as a horizontal bipolar transistor. Further, the emitter common electrode 44 is formed so as to straddle both the emitter 28 of the npn type bipolar transistor and the emitter 38 of the pnp type bipolar transistor.

By forming it in this way, the number of contact holes 32 can be reduced, and at the same time, the number of contact holes 32 can be reduced.
and the p-type emitter electrode 41, but contact holes are formed separately in the n-type emitter electrode 41 and the p-type emitter electrode 31, and emitter electrodes are formed separately. You may. The same is true for the gate electrodes; contact holes are formed separately in the gate electrode 45' for the n-channel MOSFET and the gate electrode 45' for the p-channel MOSFET, and the gate electrodes are formed separately. You can. Further, an electrode 51 is formed to straddle the collector 23 and source 25 of the npn bipolar transistor, and the emitter 33 and source 35 of the pnp bipolar transistor
Similarly, contact holes may be formed separately for the electrode 51', which is formed so as to straddle the two, and separate emitter electrodes and collector electrodes may be formed.

[Effects of the Invention] As explained above, according to the present invention, element separation due to the source current supply type of the conventional inverter gate circuit and the collector of the load driving bipolar transistor having to be electrically isolated is achieved. This solves the problem of increasing the M area, and provides a semiconductor integrated circuit that is fine and operates at high speed. Furthermore, since the source is grounded, the operating margin at low power supply voltages is also improved. Furthermore, since the base of the bipolar transistor and the drain of the MOSFET are formed in the same diffusion region, both the pnp type and npn type bipolar transistors can be miniaturized, and the number of contacts can also be reduced. For these reasons, it is possible to provide a semiconductor integrated circuit that is smaller, operates at higher speed, has higher reliability, and has a higher manufacturing yield, and a method for manufacturing the same.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an inverter gate circuit according to an embodiment of the present invention, FIG. 2 is a plan view of an inverter gate circuit according to an embodiment of the present invention, and FIGS. (e) is a sectional view showing the manufacturing steps of an inverter gate circuit according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional inverter gate circuit. 1.2...gate, 3...source, 4.5...drain, 6...source, 7,8...base, 9...
・Collector, 1'0.11-...Emitter, 12...
Collector, 17...p-type semiconductor substrate, 18...n-type buried diffusion layer, 19...p-type buried diffusion layer, 20...
- p type epitaxial layer, 21... n- type well region, 22... p'''' type groove head region, 23... n+ type collector compensation diffusion layer, 24... contact hole, 25...
・P type source diffusion region, 26...p type drain diffusion region, 27...n type base diffusion region, 28...n+ type emitter diffusion region, 29...contact hole, 30.
...Contact hole, 31-...N-type emitter electrode, 32
... Contact hole, 33... P-type collector compensation diffusion layer, 34... Contact hole, 35... N-type source diffusion region, 36... N-type drain diffusion region, 37...
- N type base diffusion region, 38... P upper type emitter diffusion region, 39... Contact hole, 40... Contact hole, 41... N type emitter electrode, 42... Base,
Drain boundary line, 43...Base, drain boundary line,
44... Common emitter electrode, 45... Common gate electrode, 45'... Gate electrode for p-channel MOSFET, 46'... Gate electrode for n-channel MOSFET,
46... Contact hole, 47... Field oxide film, 48.48''... Gate oxide film, 49... Insulating film, 50... Insulating film, 51°51... Electrode, 52...
...Emitter extraction electrode, Ql...npn type bipolar transistor, Q2...pnp type bipolar transistor, T1...p channel MOSFET, T2
...n-channel MOSFET, A...input end, B...
... Output end, C... Power supply voltage supply end, 101, 102
...Base, 103...Drain, 104...Source, 105...Emitter, 106...Collector,
107...Gate, Q101...npn type bipolar transistor, Q102...npn type bipolar transistor, T101...p channel MOSFE
T, TlO2...n channel MOET0

Claims (6)

[Claims] (1) A p-channel MOSFET whose source is connected to a first power supply terminal and whose gate is connected to an input terminal, whose base is connected to the drain of this p-channel MOSFET and whose collector is connected to the first power supply terminal. an npn bipolar transistor whose emitter is connected to the output terminal; a pnp bipolar transistor whose emitter is connected to the output terminal and whose collector is connected to the second power supply terminal; and a pnp bipolar transistor whose drain is connected to the pnp an n-channel MOSF connected to the base of a type bipolar transistor, whose source is connected to the second power supply terminal, and whose gate is connected to the input terminal.
A semiconductor integrated circuit characterized by comprising: ET. (2) A semiconductor substrate of a first conductivity type, a first buried diffusion layer of the first conductivity type formed on the surface of the semiconductor substrate of the first conductivity type, and a second buried diffusion layer of the second conductivity type. an epitaxial layer formed on a semiconductor substrate of a first conductivity type on which the first and second buried diffusion layers are formed; a first well region of a first conductivity type formed in the epitaxial layer; a first collector compensation diffusion layer of the first conductivity type having a higher impurity concentration than the first well region;
a second conductivity type second well region formed in contact with the buried diffusion layer of the second conductivity type, and a second conductivity type second collector compensation diffusion layer having a higher impurity concentration than the second well region; a first source diffusion region of a second conductivity type formed in the first well region; a first drain and base common diffusion region of the second conductivity type; and a common first drain and base diffusion region. a first emitter diffusion region of a first conductivity type formed in the well region, a second source diffusion region of a first conductivity type formed in the second well region, and a second source diffusion region of a first conductivity type formed in the second well region. a common drain and base diffusion region; a second emitter diffusion region of a second conductivity type formed within the second drain and base common diffusion region; the first source diffusion region and the first drain; , a first gate electrode formed via a first gate insulating film on a channel region between a common base diffusion region, a second source diffusion region, a second drain, and a base common diffusion region; A second gate insulating film is formed on the channel region between the second gate insulating film and the second gate insulating film.
a first emitter electrode formed on the first emitter diffusion region, a second emitter electrode formed on the second emitter diffusion region, and the first source diffusion region. a first source electrode formed on the second source diffusion region, a second source electrode formed on the second source diffusion region, and a first collector electrode formed on the first collector compensation diffusion layer. , and a second collector electrode formed on the second collector compensation diffusion layer. (3) The first and second gate electrodes, the first and second emitter electrodes, the first collector electrode and the first source electrode, and the second collector electrode and the second source electrode are integrally formed. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is formed as follows. (4) The semiconductor integrated circuit according to any one of claims (2) and (3), wherein the second well region of the second conductivity type is an epitaxial layer. (5) On the surface of the semiconductor substrate of the first conductivity type, the first conductivity type
and a second buried diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type on which the first and second buried layers are formed. forming an epitaxial layer, forming a first well region of a first conductivity type in contact with the first buried diffusion layer in the epitaxial layer, and forming a first well region in the epitaxial layer in contact with the first buried diffusion layer;
forming a second well region of a second conductivity type in contact with the buried diffusion layer; forming a field insulating film as an element isolation region;
forming a first collector compensation diffusion layer of a first conductivity type having a higher impurity concentration than the first well region in contact with the second buried diffusion layer in this epitaxial layer; a step of forming a second collector compensation diffusion layer of a second conductivity type with a higher impurity concentration than the second well region in contact with the second well region; a step of forming a first insulating film on the entire surface; and a step of forming a first conductor on the entire surface. a step of forming a layer; a step of patterning this first conductor layer to form a predetermined gate electrode;
selectively forming a first source diffusion region of a second conductivity type and a first drain and base common diffusion region of a second conductivity type in the first well region;
a second source diffusion region of the first conductivity type in the well region;
and a step of selectively forming a common first drain and base diffusion region of the first conductivity type, a step of forming a second insulating film on the entire surface, and a step of forming the first and second emitters through this insulating film. By forming a contact hole in the region, forming a second conductive layer over the entire surface, and diffusing impurities from the second conductive layer, the first drain and base common diffusion regions are formed. forming a first emitter diffusion region of a first conductivity type within the second conductivity type, and forming a second emitter diffusion region of a second conductivity type within the common second drain and base diffusion region; A step of patterning a second conductor layer to form a predetermined emitter electrode, a step of forming a third insulating film on the entire surface, and a contact hole is opened to the emitter electrode through the third insulating film. and forming contact holes through the third and second insulating films to the gate electrode, the first and second source diffusion regions, and the first and second collector compensation diffusion layers; A step of forming a third conductor layer on the entire surface, and patterning the third conductor layer to form a predetermined gate electrode,
1. A method for manufacturing a semiconductor integrated circuit, comprising the steps of forming a source electrode, a collector electrode, and an emitter extraction electrode. (6) In forming at least one of the first and second buried diffusion layers, after the step of forming the epitaxial layer, an ion implantation step of implanting impurities to a predetermined depth; 6. The method of manufacturing a semiconductor integrated circuit according to claim 5, further comprising the step of forming the implanted impurity by heat treatment.