DD266212A1 - HIGH-SPEED DRIVER AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Abstract

The invention relates to an integrable high-speed driver and a method for its production, wherein the high-speed driver enables fast, power-saving switching large capacitive loads with low space requirements and thus largely reduced Schaltverzoegerungen. In this case, the component is created in a silicone gate design with a small footprint and ensures the switching of a high current. This is achieved by the arrangement of a highly doped layer of the conductivity type of the substrate material over the drain region of a MOS transistor. In this case, this layer is separated by the drain region of the semiconductor material, wherein the collector layer of the resulting bipolar transistor and the substrate material of the MOS structure have a common fixed potential. Fig. 1

Description

For this 4 pages drawings

Field of application of the invention

The present invention relates to a high-speed driver and a method of manufacturing the same, the high-speed driver being suitable for use in NIvIOS or CMOS damage circuits and permitting fast, loss-sustaining switching of large capacitive loadon.

The fast switching of large capacitive leads on a chip, which are usually due to long Verbindungsloitungen, which may be associated with a plurality of parallel inputs connected, requires U ur loading process relatively high pruning. in NMOS technology so far only by NiOS-T Reibertranslstoren, with a correspondingly großon W / L ratio, are reached. As the W / L ratio of these transistor transistors is increased, so does their gate capacitance, as it is, in a first approximation, proportional to the channel woofer W. In order to comply with the required minimum switching time, thus, the, the output transistor driving transistor must have a sufficiently high W / L ratio. The consistent continuation of these considerations leads to the known driver chains, z. For example, when using ED-Invortern a minimal? Have total delay if each step is larger than the previous one by the bnsin of the natural logarithm, the first step being formed by a minimum invertor (1). Other inverter types require a natural logarithm factor (2), with the minimization of the switching delay in any case precluded by an increase in footprint and power dissipation. In CMOS circuit engineering, one usually uses such area and power-consuming driver chains. Also, bipolar transistors are used to implement this function independently of the MOS transistors. It should be noted that in the slides in which the o.g. Driver chains due to their high power consumption and the relatively large F'-Jchenaufwandos are not einzushar, such as integrated storage usually Gegentaktendstufen having two driver transistors with high W / L ratios, the current paths between two Suomversorgungsklommen are connected in series and their

-2- 286 212

Gate electrodes are driven gegenphacig be used. The Arbeitsgocchwindigkoit dor Gegontaktendstufoi _(is lower than that of Treiburketten, but the Stromaufnohme and Flächunboclaif against the Trolberketten is lower.

Thus, the further reduction of the switching delay, when switching large capacitive loads, in both the NMOS, and also in the CMOS circuit technology undergoes a certain limitation, which is determined by the increase in Flächenbedarfaund the power loss, this limitation in the NMOS circuit technology much sharper than in CMOS circuit technology.

Object of the invention

The goal dor invention is to provide a high-speed driver and a method for its production, wherein the high-speed driver allows the fast, verlustlelstungssparendo unloading large capacitive Laston with low Flächonbedfv f and snf switching delays weitestgehond be reduced.

Explanation of the essence of the invention

The invention has for its object to provide a Hochguschgeschwindigkeit driver in a silicone Gato design and oin method for its production, wherein the device has a small footprint and the circuit of a high current? guaranteed. This object is achieved in an SG-type electronic device consisting of a MOS transistor spatially separated from each other by a channel region within a semiconductor substrate material of a first conductivity type, a source region and a drain region of a wide conduction type, the channel region of οίπρ, η control gate coated, according to the invention solved in that a heavily doped layer of the first conductivity type is disposed over the drain region, which is separated by the drain region of the semiconductor substrate material of the first Loitungstyps, and that the collector layer Dos thereby resulting bipolar transistor and the substrate material MOS structure have a common fixed potential. The high speed driver is advantageously provided by doping the drain region lower than the source region. A further advantageous embodiment is achieved in that the semiconductor substrate material is underlaid with a highly doped layer of the same conductivity type. A further advantageous embodiment of this component is given by partially enclosing the highly doped layer of the first conductivity type by the drain region, the enclosed layer being located in the semiconductor substrate material. The production of the electronic component is a method in which after formation of the source-drain regions and after thermal oxidation of the MOS transistor in silicon gate technology in an epitaxial Schichtabscheideprozeß a highly doped epitaxial layer of a first conductivity type on the surface of Halbloitersubstratmaterials, with Corresponding to the drain region, selectively deposited and contacted after forming a CVD passivation layer and subsequently introduced into the passivation layer contact window openings, by a l.eitbahnsystem.

LAuaführungsbelsplel

The invention will be explained in more detail with reference to an exemplary embodiment.

1 shows the electronic component according to the invention in a sectional view,

2 shows the circuit of the component with gate control,

FIG. 3 shows the peeling of the component with source ejection of a

FIG. 3a: enhancement transistor, FIG.

3 b: Zaro transistor,

Fig. 3c: depletion transistor.

The sectional view (FIG. 1) shows an intaglatable electronic component for fast switching of large capacitive loads, a so-called high-speed driver in a silicon gate design. The device has in the near-surface region einos ρ-doped semiconductor substrate material 2 of a MOS transistor, also forming the collector of a bipolar transistor, two doped layers 5 and 6, of which the layer 5, the source η'-doped and the layer 6, the drain η -doped. The drain 6 of the MOS transistor simultaneously constitutes the base of the bipolar transistor. The layers 6 and 6 are spatially separated within the semiconductor material 2 by the channel gobiet 1 δ of the electronic component, the carial region 15 being doped by a gate insulator 7 Layers 5 and 6 partially overlapping, coated. The gate electrode 9 is arranged above the gate insulator 7 in the region of the channel corner 15. The regions 5 and 6 are spatially separated within the semiconductor material 2 by the channel region 15 of the electronic device, wherein the channel region 15 is covered by a gate insulator 7, the doped layers 5 and θ partially overlapping. About the gate insulator 7, the doped layers 5 and 6 partially overlapping, coated. About the gate insulator 7, in the region of the Konalgebietes 15, the »gate electrode 9 is arranged. The areas 5 and 6, source and drain, are bounded laterally by the ρ-doped semiconductor substrate 2 and the field oxide 3. The field oxide 3, in the region of the ρ -dotiorten semiconductor substrate 2 'is followed by a ρ' -doped barrier layer 4, which corresponds to the boundary film of a ρ ^f -doped semiconductor substrate 1 connected to the p ~ doped semiconductor substrate 2. The p ⁺ -doped semiconductor substrate 1 serves to reduce the collector path resistance of the bipolar transistor. On the surface of the p ~ -doped semiconductor substrate 1, a ρ '-doped layer 10 is arranged between the gate electrode 9 and field oxide 3, corresponding to the drain 6, which constitutes the emitter of the pnp transistor. Source region 5 and emitter region 10 are contacted by means of the contacts 16. The remaining area of the electr. Component is provided with a passivation layer 14. From the component according to the invention, two basic statements can be derived. FIG. 2 shows a gate control of the high-speed driver. This circuit

consists of an n-channel enhancement transistor T11 and a pnp bipolar transistor T12, which is operated horstellungsbodingt as emitter follower. As the circuit input E, the gate electrode of the MOS transistor T11 is fixed. The source of this transistor is connected to a first power supply terminal US while its drain is connected to the base of the PNP bipolar transistor T12. The circuit output A forms the emitter of T12, while the collector is connected to the substrate, which is why it is connected to a second power supply terminal UB. If such a potential is applied to the circuit input that the gate-source voltage of the enhancement transistor T11 exceeds its threshold voltage, the base of the bipolar transistor T12 is placed practically on the potential US and at the circuit output A a potential is established is equal to the sum of the average voltage of the bipolar transistor T12 and the level of the power supply terminal US. This potential represents the output loco level of the circuit. If the level of the power supply terminal is US volts, this output low level will be about 0.7 volts. If one makes the level of Stromversorfjungsklemme US slightly negative, but not so far that the drain-substrate diode opens and injects electrons into the substrate, a correspondingly lower output low level can be achieved. When a potential of magnitude is applied to the gate of the MOS transistor T11 such that the gate-to-source voltage of T11 is less than its threshold voltage, the enhancomont transistor T11 turns off and the base of the pnp bipolar transistor T12 is isolated. The output high-pegole kanji can now be generated via a precharge circuit, which is not shown in FIG. 1, because as a result of the isolated pals connection of the pnp-1) bipolar transistor T12 and its connection as emitter follower, its base potential also increases with increasing fitter potential. It should be mentioned on this mile that, instead of the enhancement transistor T11, with suitable input signals and the corresponding level of the power supply terminal, a zero transistor can be used, which is untarnished with an increase of the output low pegol.

2nd embodiment

FIG. 2 shows the sourcestation variants of the MOS bipolar structure according to the invention that can be realized using the three MOS transistors available in NMOS technology. These circuits have substantially all the same structure. According to the use of the MOS bipolar structure according to the invention, these circuits each consist of a MOS transistor and a pnp-P ^: polar transistor, which is operated in collector circuit. In this case, the MOS transistor a

a) Enhancement Transisto. '

b) zero-transistor or

c) be depletion transistor.

The circuit input E we i each formed by the source electrode dos MOS transistor. The gate of the MOS transistor is connected to a first power supply terminal UG, wherein in the case of the depletion transistor, the gate connection of the gate to the circuit input, as shown in Figure 2c, is particularly advantageous. The level de; ' Stromversorgungsklemmo UG must be at least greater than the sum of the threshold voltage of the MOS transistor used and Dom input low level. The drain of the MOS transistor is connected in all cases to the base of the PNP bipolar transistor. The circuit output is formed by the emitter of the bipolar transistor, while its collector, due to the technology, is connected to the substrate and thus to a second power supply terminal UB. Boi all, in the figure 2 gr digton circuit variants, the pnp bipolar transistor can be locked by a suitable input high level, while he can be aufgosteuert by a corresponding input low level. The output low-level! The circuit shown in FIG . 2 is given by the sum of the input low pegol and the forward voltage of the pnp bipolar transistor and is therefore higher in the regol than the gate control variant discussed in the first exemplary embodiment. The differences between the circuit variants shown in figure 2 are discussed below. If the MOS transistor is an enhancement transistor, as shown in FIG. 2a, both the enhancement transistor T21 are in the case of a sufficiently large input high level, which is approximately equal to the output high level a, as well as the pnp BipolartronsistorT22 a locked. The circuit output A can now be charged via a precharging circuit not shown in FIG. 2a. As a result of the relatively high Schwollspannung dos enhancement transistor T21 a, the interference immunity of this circuit variant is very high compared to changes in the input high-Pogels. In concrete terms, the input high level may decrease to a value which is equal to the difference between the level of the current supply terminal UG and the threshold voltage of the enhancement transistor T21 a, without such fluctuations having an effect on the output high level , But it does not succeed synonymous durchzuschalton the full input high level on the basis dos PNP bipolar transistor T22a, so that the base potential must be increased during the precharge at correspondingly high output high levels by the base current of T12a with. If the MOS transistor is a zero transistor, as shown in FIG. 2 b, then basically the same statements are made as for the circuit according to FIG. 2 a, only that due to the lower threshold voltage of the zero transistor, the interference immunity to changes in the Lower input level and that it is possible for dom same reason, the base of the pnp bipolar transistor T22 b to higher potentials, compared to the circuit of Figure 2a, pre-charge.

If the MOS transistor is a depletion transistor and is connected in such a way as ec is shown in FIG. 2c, then the interference immunity to changes in the input high peg is practically zero. But it succeeds, the full input high-Pege! to the base of the PNP bipolar transistor T22c, so that during the generation of the output high pegolo, which is realized by a precharge circuit, which is not shown in FIG. 2c, at a sufficiently high input high. Level, the PNP bipolar transistor T22c is permanently locked.

To ensure in the driver variants of Figure 2a and 2b, so the circuits that use an enhancement or zero transistor as MOS transistor, that as long as possible, a constant base current flows during the discharge of the connected to the circuit output capacitive load, the Discharge so with declining output voltage is not delayed, it is recommended to work with lower effective Gato source voltages zg, so that the respective MOS transistor works as long as possible in the saturation region. This can be achieved by lowering the level of the first power supply terminal UG, wherein optionally dos W / L ratio of the MOS transistor must be increased.

Another, albeit much inelegant possibility is to increase the Schwollspnnnung of the MOS transistor in a suitable manner.

3rd embodiment

The following embodiment relates to the cooperation of the drive circuits discussed in Embodiments 1 and 2, which are realized on the basis of the MOS bipolar structure of the present invention, with input circuits capable of evaluating the levels output by the drivers.

In principle, it is possible to use in the input circuits, which have to evaluate the levels achievable by the above-explained drivers, enhancement transistors having a Schwoll voltage which is greater by a safety margin than the worst case output low level the buffer circuits. This possibility is particularly to be considered in the gate control variant of the MOS-bipolar structure according to the invention, since for the generally necessary conversion of the TTL poppy to the internal level of a MOS circuit enhancement transistors with a threshold voltage, which still the correct processing of a 0.8V worst-case TTL Iow level will also allow proper processing of the 0.7V output low level of the gate control variant when operating at a level of the power supply terminal US of zero volts becomes. If the source control variants of the MOS-bipolar structure in accordance with the invention are to be used, they provide the CML gates presented in FIG. 3 as input circuits for the evaluation of the pegoi that can be realized by the drivers. These allow the delay-free takeover and correct detection, even higher input low-Pogel, so that the larger output low levels of Sourcesterung variants can be easily processed.

In the following three Ausführungsboispiele for producing the MOS bipolar driver according to the invention will be described with reference to FIGS 4-9. For the above description of the function and the description of possible uses of the structure, it is immaterial to which of the three embodiments for manufacture reference is made. In the Bosch friction of the production is assumed in each case by the MOS structure shown in the figure 4, which is kung by a conventional η SGT process sequence, the MOS Blpolar Strukturspozifische process step after the structuring and thermal oxidation of the last Gateben.i of the a η SGT-Prozosfolge deviates. As will be explained below, it is advantageous for the components to be in a low-doped ρ-surface layer which has a thickness of approximately 2 μm and which is z. Epitak '.' Can be applied to produce.

Don three embodiments, the first Maskonschritt is common, which allows a selective introduction of the source-drain Gobiete. (Figure 4)

1. Ausfühmngsbeisplel for production

For selective implantation of the remaining area with substrate or channel doping region 9 ', a second Maskonschritt. In this case, the negative of the template used in the first mask step can be used. The resist edge 10 'is also positioned here on the gate 9, so that the selbstjustieronde character of the implantation is maintained. A highly doped flat p-implant and a low-doped deep η-implant are introduced, whereby the regions 10 and 6 are formed. (Figure 5) The ρ ^{f region} 10 is about 0.3 μm deep. The average doping concentration is about 10 ²⁰ cm ^-3 . The n-type region 6 extends at a depth of about 0.3μιη-0.7 pm with an average doping concentration of about 8 · 10O ^e crrT ³ . In the region 13 under the gate region, these conditions essentially remain due to the implantation energy-dependent lateral scattering of the implant, so that the ρ 'region 10 is completely enclosed by the n-type region 6 and thus insulated from the substrate regions 2 and 4. The contacting of the η 'source-drain regions 5 and the ρ' region 10 can take place jointly after the deposition of a CVD layer 14 (FIG. 6) and the contact window opening. In the transition regions between the channel-stop gobiet 4 and the p'-region 10 (FIG. 6), the isolation capability of the n-region 16 can be reduced as a result of a far-reaching channel-stop doping. With the help of modern isolation techniques, such as trench isolation or high pressure field oxidation, these problems can be bypassed or defused. A simple way to issue this problem will be explained in the second embodiment.

2nd embodiment example for the production

As in the first embodiment, a second mask step is used for introducing the deep, low-dose n 'plan. The ρ'-implantation takes place after the CVD layer deposition through the opened contact windows (FIG. 7), the gate dielectric remaining in the account window to avoid a channeling of the implant. The contact windows can reach up to about Ο, δμηι to the Foldoxidschrägon. Maintaining the doping ratios defined in FIG. 1, a sufficient isolation to the channel stop region 4 is ensured. The ρ 'implantation does not require any further masking step when the dose and penetration depth are below the values set for the source-drain regions, so that only insignificant compensation of the n- ^f regions 5 occurs. The Leitgebebononkontaktiorung can be done together as in the first embodiment for the ρ 'regions 10 and the n * -Gobiete 5.

3. Ausführungsbeisplel for production

As in the second exemplary embodiment, the introduction of the low-dose ion implant takes place after the second mask curve (FIG. 5), so that a mean doping concentration of about δ- ¹⁰ cm- ^{3 is} set to a depth of about 0.3 μm. Thus no high-energy implantation is necessary for the introduction of this implants, the etch-insulator layer is etched in the unmasked area and then the lacquer-mask is removed (FIG.

On the exposed surface 17 'is selectively epitaxiort. Thereafter, a large-area over-etching of the semiconductor wafer takes place in order to eliminate laterally grown layers, and the ρ ^f -doping of the epitaxial layer 18 (FIG. 9) shows the contacted structure.

The function of the structure is based on the fact that in each case a pnp bipolar transistor is formed by the regions 20 in FIGS. 6 and 9, the p * region 11 or the epitaxial region 18 being emitter, the n region 6 being the base and the p -Substrate 2 serves as a collector. To reduce the collector track resistance, a low-resistance p ^{+ region} 1 is used as the substrate carrier material. It is easy to see that this combined MOS bipolar struktiiron also in a complementary technology, z. B. CMOS can be made, so that a p-channel MOS transistor coupled to a npn bipolar transistor is formed.

Claims (5)

-1- 2ββ212 claim of invention: A high-speed SQ-type driver comprising an MOS transistor having, within a semiconductor substrate material of a first conductivity type, a source region and a drain region of a second conductivity type spatially separated by a channel region, the channel region being covered by a control gate, characterized a high-doped layer of the first conductivity type is arranged over the drain region, which is separated from the semiconductor substrate material of the first conductivity type by the drain region, and in that the collector layer of the resulting bipolar transistor and da :; Substrate material of the MOS structure have a common fixed potential. 2. High-speed driver for fast switching of large capacitive loads according to item 1, characterized in that the drain region is doped lower compared to the source region. 3. High-speed driver according to item 1, characterized in that the semiconductor substrate material is underlaid with a highly doped layer of the same conductivity type. 4. HochgeschwinOigkeitstreiber according to item 1, characterized in that the drain region partially encloses the highly doped Sch'cht of the first conductivity type and this enclosed layer is located befindlichem in the semiconductor substrate material. 5. A method for producing a high-speed driver according to item 1, characterized in that after formation of the source-drain regions and after thermal oxidation of the control gate of the MOS transistor in a silicon gate technology in an epitaxial Schichtabscheidoprozeß a highly doped epitaxial layer of a first conductivity type on the Surface of the semiconductor substrate material, which is corresponding to the drain region, is applied, is contacted by a Loitbahnsystem after forming a CVD passivation layer and subsequently introduced into the passivation layer Kuntaktfensteröffnungen.