JPH05211294A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05211294A JPH05211294A JP24868291A JP24868291A JPH05211294A JP H05211294 A JPH05211294 A JP H05211294A JP 24868291 A JP24868291 A JP 24868291A JP 24868291 A JP24868291 A JP 24868291A JP H05211294 A JPH05211294 A JP H05211294A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- diffusion layer
- resistor
- aluminum
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
多結晶シリコンを抵抗体とした抵抗素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resistance element using polycrystalline silicon as a resistor.
【０００２】[0002]
【従来の技術】従来の多結晶シリコンを抵抗体とした抵
抗素子について、図面を参照して説明する。図３は従来
の多結晶シリコン抵抗の平面図およびその破線Ｃ−Ｃ1
に沿った構造の断面図である。図３に示した様に、多結
晶シリコン抵抗は、シリコン基板１を熱酸化することに
より形成したフィールド酸化膜とよばれる、膜厚１〜２
μｍ程度の厚い酸化膜２上に形成される。2. Description of the Related Art A conventional resistance element using polycrystalline silicon as a resistor will be described with reference to the drawings. FIG. 3 is a plan view of a conventional polycrystalline silicon resistor and its broken line C-C 1
FIG. 5 is a cross-sectional view of the structure taken along. As shown in FIG. 3, the polycrystalline silicon resistor has a film thickness of 1 to 2 called a field oxide film formed by thermally oxidizing the silicon substrate 1.
It is formed on a thick oxide film 2 having a thickness of about μm.
【０００３】このフィールド酸化膜２上に形成すること
で、多結晶シリコン３と基板間に形成される寄生容量が
低減でき、高速動作が必要な半導体集積回路に適した抵
抗素子となる。多結晶シリコン３には、所望の抵抗率を
得るためリン，ヒ素などのＮ型不純物，又はホウ素など
のＰ型不純物をイオン注入法等により所定の量がドープ
されている。（一般には、低いものでも数１００Ω／□
の抵抗率となる様にドープされる。）この場合、多結晶
シリコン抵抗３とアルミニウム等の配線材料６との接触
部分である、抵抗の両端部のみは、配線材料６との接触
抵抗を下げるため、不純物を高濃度にドープして抵抗率
を低くしておくこともある。さらに多結晶シリコン抵抗
３上を他の導電性の物質が横切っても、それらの物質と
多結晶シリコン抵抗が短絡しない様に、多結晶シリコン
抵抗３全体を絶縁性の膜４で覆うことが必要である。シ
リコン酸化膜をＣＶＤ法により数１０００オングストロ
ーム成長させることでカバーすることができる。多結晶
シリコン抵抗３を覆う様に成長した絶縁性のカバー膜４
は、多結晶シリコン抵抗３よりも数μｍの余裕をもって
パターンニングし、多結晶シリコン抵抗と配線材料６と
のコンタクト孔５もこの時同時に形成する。By forming this on the field oxide film 2, the parasitic capacitance formed between the polycrystalline silicon 3 and the substrate can be reduced, and it becomes a resistance element suitable for a semiconductor integrated circuit which requires high speed operation. The polycrystalline silicon 3 is doped with a predetermined amount of N-type impurities such as phosphorus and arsenic or P-type impurities such as boron by an ion implantation method or the like in order to obtain a desired resistivity. (Generally, even low ones are several 100Ω / □
Is doped to have a resistivity of. In this case, in order to reduce the contact resistance with the wiring material 6, only the both ends of the resistance, which is the contact portion between the polycrystalline silicon resistor 3 and the wiring material 6 such as aluminum, are doped with impurities at a high concentration. Sometimes the rate is kept low. Furthermore, it is necessary to cover the entire polycrystalline silicon resistor 3 with an insulating film 4 so that even if another conductive substance crosses over the polycrystalline silicon resistor 3, those substances and the polycrystalline silicon resistor are not short-circuited. Is. It can be covered by growing the silicon oxide film by several thousand angstroms by the CVD method. Insulating cover film 4 grown to cover the polycrystalline silicon resistor 3
Is patterned with a margin of several μm larger than the polycrystalline silicon resistor 3, and the contact hole 5 between the polycrystalline silicon resistor and the wiring material 6 is also formed at this time.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の多結晶
シリコンを抵抗体とした時に抵抗率１ｋΩ／□以上の負
荷抵抗素子では多結晶シリコンの物性的特性によって、
使用温度が上昇すると抵抗率が下がる方向で変動すると
いう問題があった。この問題は、一般に抵抗率の高い多
結晶シリコン抵抗で著しい。例えば、多結晶シリコン膜
厚（５００オングストロームで形成した、常温での低効
率が１０ｋΩ／□の抵抗において使用温度が５０℃上昇
すると、抵抗率が５０％降下する。以上の様に温度依存
性が大きいため半導体装置の設計余裕度が小さくなると
いう問題があった。In the load resistance element having a resistivity of 1 kΩ / □ or more when the conventional polycrystalline silicon is used as a resistor, the physical properties of polycrystalline silicon cause
There has been a problem that the resistivity fluctuates in the direction of decreasing as the operating temperature rises. This problem is generally noticeable with polycrystalline silicon resistors, which have a high resistivity. For example, when the operating temperature rises by 50 ° C. at a resistance of polycrystalline silicon film thickness (500 angstroms and low efficiency at room temperature of 10 kΩ / □), the resistivity drops by 50%. Since it is large, there is a problem that the design margin of the semiconductor device becomes small.
【０００５】本発明の目的は、多結晶シリコンを抵抗体
とした、特に抵抗率の高い負荷抵抗素子を有する半導体
装置において負荷抵抗素子の温度特性を改善することに
ある。An object of the present invention is to improve the temperature characteristics of a load resistance element in a semiconductor device having a load resistance element having a high resistivity, which uses polycrystalline silicon as a resistor.
【０００６】[0006]
【課題を解決するための手段】本発明の多結晶シリコン
を抵抗体とした負荷抵抗素子は、少なくとも多結晶シリ
コンの一方の端部を、多結晶シリコンにドープされた不
純物と同一導電型の不純物で形成された拡散層に直接接
続され、配線を拡散層から引き出すことを特徴とする。According to the present invention, there is provided a load resistance element using polycrystalline silicon as a resistor, wherein at least one end of the polycrystalline silicon has the same conductivity type as the impurity doped in the polycrystalline silicon. It is characterized in that it is directly connected to the diffusion layer formed by and leads the wiring from the diffusion layer.
【０００７】[0007]
【実施例】次に本発明について図面を参照して説明す
る。図１は、本発明の一実施例である抵抗素子の平面図
およびその破線Ａ−Ａ1 に沿った断面の構造図である。
図１に示す様に本発明の抵抗素子は、抵抗体である多結
晶シリコン３は、半導体基板１表面に熱酸化により形成
されたフィールド酸化膜２上に形成されている。多結晶
シリコン３には、所望の抵抗率を得るため、例えば、ヒ
素，リンなどのＮ型不純物を所定の量ドープしてある。
多結晶シリコン３の端部は、多結晶シリコン３にドープ
した不純物と同一導電型の不純物、例えば、リンなどを
拡散したシリコン基板１によって形成されるＮ型不純物
拡散層７に接続されている。このＮ型不純物拡散層７
は、同一基板上にＮＰＮ半導体装置が形成される場合、
コレクタコンタクト拡散層と、ＭＯＳ型半導体装置が形
成される場合、ソース，ドレイン拡散層と同時に形成し
ても良い。The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a resistance element that is an embodiment of the present invention and a structural view of a cross section taken along the broken line AA 1 .
As shown in FIG. 1, in the resistance element of the present invention, polycrystalline silicon 3 which is a resistor is formed on a field oxide film 2 formed on the surface of a semiconductor substrate 1 by thermal oxidation. The polycrystalline silicon 3 is doped with a predetermined amount of N-type impurities such as arsenic and phosphorus in order to obtain a desired resistivity.
An end of the polycrystalline silicon 3 is connected to an N-type impurity diffusion layer 7 formed by a silicon substrate 1 in which an impurity of the same conductivity type as the impurity doped in the polycrystalline silicon 3, for example, phosphorus is diffused. This N-type impurity diffusion layer 7
When an NPN semiconductor device is formed on the same substrate,
When the collector contact diffusion layer and the MOS type semiconductor device are formed, they may be formed simultaneously with the source and drain diffusion layers.
【０００８】多結晶シリコン３にドープされた不純物が
Ｐ型不純物である場合、拡散層７もＰ型の不純物拡散層
にする必要がある。また、抵抗素子の抵抗値を決定する
多結晶シリコン３の抵抗値に対して拡散層７の抵抗値が
無視できる様にするためには、不純物拡散層７は、熱拡
散法によりできるだけ高濃度に形成する必要があるが、
イオン注入により、シリコン基板１に導入される不純物
量を制御することで、拡散層７にも所望の抵抗値を形成
し、抵抗素子としては、多結晶シリコン３と拡散層４が
直列抵抗をなす構造で使用することも可能である。When the impurity doped in polycrystalline silicon 3 is a P-type impurity, diffusion layer 7 must also be a P-type impurity diffusion layer. Further, in order to make the resistance value of the diffusion layer 7 negligible with respect to the resistance value of the polycrystalline silicon 3 which determines the resistance value of the resistance element, the impurity diffusion layer 7 is made to have the highest possible concentration by the thermal diffusion method. Need to be formed,
By controlling the amount of impurities introduced into the silicon substrate 1 by ion implantation, a desired resistance value is also formed in the diffusion layer 7, and as the resistance element, the polycrystalline silicon 3 and the diffusion layer 4 form a series resistance. It can also be used in construction.
【０００９】シリコン基板１内に形成された不純物拡散
層７は温度に対する抵抗率の変化は、温度の上昇により
抵抗率は高くなる特性を示し、多結晶シリコン３とは逆
の温度特性を示す。したがって多結晶シリコン３と不純
物拡散層７を接続して一つの抵抗素子を形成することで
温度に対して多結晶シリコン３と拡散層７が相補的な関
係にすることができる。The impurity diffusion layer 7 formed in the silicon substrate 1 has a characteristic that a change in resistivity with respect to temperature has a characteristic that the resistivity becomes higher as the temperature rises, and exhibits a temperature characteristic opposite to that of the polycrystalline silicon 3. Therefore, by connecting the polycrystalline silicon 3 and the impurity diffusion layer 7 to form one resistance element, the polycrystalline silicon 3 and the diffusion layer 7 can have a complementary relationship with respect to the temperature.
【００１０】多結晶シリコン３には、多結晶シリコン３
全体を覆う絶縁性の膜４が数１０００オングストローム
の膜厚で形成される。膜４は、ＣＶＤ法により成長した
シリコン酸化膜でよい。また拡散層には、アルミニウム
などの配線材料６と接続をとるコンタクト孔５が形成さ
れる。The polycrystalline silicon 3 includes the polycrystalline silicon 3
An insulating film 4 covering the whole is formed with a film thickness of several thousand angstroms. The film 4 may be a silicon oxide film grown by the CVD method. In addition, a contact hole 5 is formed in the diffusion layer to connect with a wiring material 6 such as aluminum.
【００１１】図２は本発明の第２の実施例における抵抗
素子の平面図およびその破線Ｂ−Ｂ1 に沿った断面図で
ある。第１の実施例においては、多結晶シリコン３と不
純物拡散層７を直列に接続した形で一つの抵抗素子を形
成したが、第２の実施例においては、多結晶シリコン３
下には、多結晶シリコン３と同一導電型の不純物拡散層
７が形成され、多結晶シリコン３と不純物拡散層７が並
列に接続した形で一つの抵抗素子を形成する。FIG. 2 is a plan view of a resistance element according to a second embodiment of the present invention and a sectional view taken along the broken line B-B1 thereof. In the first embodiment, one resistance element is formed by connecting the polycrystalline silicon 3 and the impurity diffusion layer 7 in series, but in the second embodiment, the polycrystalline silicon 3 is used.
An impurity diffusion layer 7 having the same conductivity type as that of the polycrystalline silicon 3 is formed below, and one resistance element is formed in a form in which the polycrystalline silicon 3 and the impurity diffusion layer 7 are connected in parallel.
【００１２】この場合にも、抵抗コンタクト孔５は、拡
散層７に配線材料６が接続されるように形成する。Also in this case, the resistance contact hole 5 is formed so that the wiring material 6 is connected to the diffusion layer 7.
【００１３】[0013]
【発明の効果】以上説明したように本発明は、抵抗体で
ある多結晶シリコンを多結晶シリコンにドープした不純
物と同一導電型の不純物拡散層と接続することで、特に
多結晶シリコンの抵抗率が１ｋΩ／□以上の場合、両者
が温度変化に対して逆方向の変動をするということが利
用でき、温度変化に対する変動を緩和できるという効果
がある。As described above, according to the present invention, the resistivity of polycrystal silicon is particularly improved by connecting the polycrystal silicon, which is a resistor, to the impurity diffusion layer having the same conductivity type as the impurity doped in the polycrystal silicon. Is more than 1 kΩ / □, it can be utilized that both of them fluctuate in the opposite direction with respect to the temperature change, which has an effect of alleviating the fluctuation with respect to the temperature change.
【００１４】また、配線用アルミニウムは拡散層に接続
されているので、アルミニウムと多結晶シリコンの反応
による多結晶シリコンの吸い出しを避けることができる
という効果もある。Further, since the wiring aluminum is connected to the diffusion layer, there is an effect that it is possible to avoid sucking out the polycrystalline silicon due to the reaction between the aluminum and the polycrystalline silicon.
【図１】本発明の一実施例の平面図および破線Ａ−Ａ1
の断面図である。FIG. 1 is a plan view of an embodiment of the present invention and a broken line AA 1
FIG.
【図２】本発明の他の実施例の平面図および破線Ｂ−Ｂ
1 の断面図である。FIG. 2 is a plan view of another embodiment of the present invention and a broken line BB.
It is a sectional view of 1 .
【図３】従来の多結晶シリコン抵抗素子の平面図および
その破線Ｃ−Ｃ1 断面図である。FIG. 3 is a plan view of a conventional polycrystalline silicon resistance element and a sectional view taken along the broken line C-C 1 thereof.
１ シリコン半導体基板 ２ フィールド酸化膜 ３ 多結晶シリコン ４ 多結晶シリコンカバー膜 ５ 抵抗コンタクト孔 ６ アルミニウム配線 ７ 不純物拡散層 1 Silicon Semiconductor Substrate 2 Field Oxide Film 3 Polycrystalline Silicon 4 Polycrystalline Silicon Cover Film 5 Resistive Contact Hole 6 Aluminum Wiring 7 Impurity Diffusion Layer
Claims (1)
リコンによる抵抗体と単結晶シリコンによる結晶体を電
気的に直接接続して使用することを特徴とした半導体装
置。1. A semiconductor device in which a resistor made of polycrystalline silicon and a crystal made of single crystal silicon formed on the same silicon substrate are electrically connected directly to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24868291A JP3160954B2 (en) | 1991-09-27 | 1991-09-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24868291A JP3160954B2 (en) | 1991-09-27 | 1991-09-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05211294A true JPH05211294A (en) | 1993-08-20 |
| JP3160954B2 JP3160954B2 (en) | 2001-04-25 |
Family
ID=17181766
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24868291A Expired - Fee Related JP3160954B2 (en) | 1991-09-27 | 1991-09-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3160954B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013239554A (en) * | 2012-05-15 | 2013-11-28 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8770504B1 (en) * | 2011-09-23 | 2014-07-08 | Thomas Sandstrom | Motor driven fishing reel |
-
1991
- 1991-09-27 JP JP24868291A patent/JP3160954B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013239554A (en) * | 2012-05-15 | 2013-11-28 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method of the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3160954B2 (en) | 2001-04-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20010123 |
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| LAPS | Cancellation because of no payment of annual fees |