JPH04130658A - Polycrystalline silicon resistor for semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize a polycrystalline silicon resistor by a method wherein it is used in a condition that one conductive type resistor peripheral layer superimposed on the resistor layer is given an electric potential in the reverse bias direction to the resistor layer. CONSTITUTION:A surface of a semiconductor substrate 1 of an integrated circuit or the like is coated with an insulating film 2, and a polycrystalline silicon resistor is incorporated thereon. A resistor layer 4 is a p-type and diffused by a pattern P4 in which both ends are wide and the center is narrow. A resistor peripheral layer 5 is of an n-type opposite to that of the resistor layer 4. In the polycrystalline silicon resistor with the above arrangement, an electrode film on the left side is connected to, for example, a plus power supply terminal, and an electrode film on the right side is connected to a desired place within the integrated circuit to use the resistor. Thus, a voltage is always applied in the reverse bias direction to a connection between the p-type resistor layer 4 and the n-type resistor peripheral layer 5, and the resistance value of the polycrystal silicon resistor which is determined by the effective width We of the resistor layer 4 is stably maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resistor made of polycrystalline silicon suitable for incorporation into a semiconductor device, particularly an integrated circuit device.

[Conventional technology]

Elements and circuit parts built into semiconductor devices such as integrated circuit devices are often used in a state where they are connected to a resistor, and although this can be so-called externally connected, it saves the space and effort required for external connections. In this case, it is generally advantageous to incorporate the resistor into the semiconductor device. As this built-in resistor, a diffused resistor or a resistance-connected MO3) transistor can be built into a single crystal silicon semiconductor, but a considerable amount of chip area needs to be allocated for it, unless the resistance value is very low.

For this reason, it has been conventional practice to construct a resistor using polycrystalline silicon, which is used for MOSFET gates, etc., and an example thereof will be briefly explained with reference to FIG.

The semiconductor substrate l shown in the cross section of FIG. 2(b) is a single-crystal silicone substrate of an integrated circuit device or the like, or an epitaxial layer grown thereon, and an element bone 111M attached to the surface thereof.
On this insulating film 2, a polycrystalline silicon film 3 is usually grown at the same time as the MOSFET gate, and by photoetching, the resistor is built in on a relatively thick insulating film 2 such as a field oxide film. It is formed into an elongated pattern as shown in the top view, and doped with p-type or n-type impurities to obtain an appropriate sheet resistance value.

Furthermore, as shown in FIG. Now, conductive contact is made to each of the slightly wide ends to form a pair of connection terminals for the resistor.This built-in resistor is insulated from the semiconductor substrate 1 by the insulating film 2, and is connected to the semiconductor device via the electrode film 7. Connected to a predetermined location within.

Note that in FIG. 2(a), the glabella insulating film 6 is shown as being transparent for convenience of illustration.

[Problem to be solved by the invention]

The above-mentioned polycrystalline silicon resistor has the advantage that the required chip area is much smaller because it does not require junction separation compared to the case where the resistor is built into the semiconductor substrate 1 because it is disposed on the top of the resistor 12. With the recent progress in high integration, it has become necessary to reduce the size of polycrystalline silicon resistors, especially high resistors, to the same level as other circuit elements.

Now, if the sheet resistance of the resistive film is Rs, and the length and width are W, then the resistance value will be Rs (L/W) as is well known, so if the sheet resistance Rs is constant, the value shown in Figure 2 (a) will be obtained. When the width W of the polycrystalline silicon film 3 is reduced, the length is also reduced and the size can be reduced. However, in reality, there are restrictions in the photo process design rules, and the width W cannot be made smaller than the minimum dimension under the rules, for example, 34, so if the resistance is high, the length increases, making it difficult to downsize. Further, in order to reduce the size, it is possible to increase the sheet resistance IRs, but there is a limit to this because the resistance value becomes unstable unless the impurity concentration is given to the polycrystalline silicon film 3 above a certain level.

What makes this problem even more difficult is that as circuit elements become more highly integrated, the current consumption of circuit elements decreases and higher resistances are required. This requires a high resistance of Ω to several MΩ, which adds to the problem.

Based on such circumstances, an object of the present invention is to miniaturize a polycrystalline silicon resistor.

[Means for Solving the Problem] According to the present invention, this problem is solved by combining a polycrystalline silicon film disposed in a predetermined pattern on an insulating film, a resistive layer diffused therein with one conductivity type, and a resistor. A polycrystalline silicon resistor is formed from the resistor peripheral layer of the other conductivity type, which is diffused in the polycrystalline silicon film in a pattern that overlaps at least a portion of the layer and limits the resistance from the periphery, and this is connected to the resistor peripheral layer. This is solved by applying a reverse bias potential to the layer.

Note that it is practically advantageous to short-circuit the resistor peripheral layer in the above structure at one end of the resistor layer and the polycrystalline silicon resistor.

In addition, various forms are possible for the diffusion pattern of the resistor layer and the resistor peripheral layer. For example, it is possible to diffuse the resistor layer over the entire surface of the polycrystalline silicon film and then diffuse the resistor peripheral layer. It is most rational to diffuse the resistor layer in a generally elongated pattern and diffuse the resistor peripheral layer in a pattern that surrounds this resistor layer and limits its effective pattern width. Since the resistor peripheral layer thus limits the effective pattern of the resistor layer that determines the resistance value of the polycrystalline silicon resistor, it is advantageous to diffuse the resistor peripheral layer with a higher impurity concentration than the resistor layer.

[Effect]

The present invention focuses on the fact that the junction surface between two adjacent diffusion layers with different conductivity types moves due to impurity diffusion from one side to the other. However, this problem was successfully solved by diffusing impurities in the resistor peripheral layer into the resistor layer and limiting the effective width, which determines the resistance value, to be narrower than the minimum dimension specified in the rules.

For this purpose, a resistor layer of one conductivity type and a resistor peripheral layer of the other conductivity type are diffused into the polycrystalline silicon film disposed on the insulating film. It is diffused in a pattern that overlaps at least a portion and limits the resistance from the periphery, thereby narrowing the effective width of the resistance layer from the minimum dimension according to the design rules and increasing the resistance value.

For example, even if the resistance layer is diffused in a pattern with a width of 3-, if 14 impurities are diffused from the resistor peripheral layers on both sides, the effective width becomes 1μ and the resistance triples. Therefore, in order to obtain the same resistance value, the effective width can be reduced to one-third and the length can be reduced to one-third accordingly, so in the present invention, the area of the effective portion of the resistor can be reduced to one-ninth. .

Furthermore, the present invention provides a reverse bias potential for the resistor layer to ensure that the polycrystalline silicon resistor operates with the narrowed effective width of the resistor layer as described above.

For example, when the resistor layer is of P type and the resistor peripheral layer is of N type, this polycrystalline silicon resistor is used with a positive potential applied to the resistor peripheral layer.

[Example] Hereinafter, an example of the polycrystalline silicon resistor for a semiconductor device of the present invention will be described with reference to FIG. The same figure (the river is a top view, ■ in the same figure) is a cross-sectional view of the central part taken in the horizontal direction, and the same figure (C) is a cross-sectional view taken in the vertical direction, which is similar to Fig. 2 explained earlier. Corresponding parts are given the same symbols.

As shown in Figure 1, etc., semiconductor substrates such as integrated circuit devices
The surface of the silicon oxide element! The polycrystalline silicon H3 used for this is covered with an insulating film 2, which is a field oxide film, and is usually about IIIm thick, and a polycrystalline silicon resistor is built thereon.
OS) It is advantageous to grow and pattern at the same time as the gate for the transistor, and the film thickness is usually 0.5 to 1i.
It is assumed that m.

In this example, the polycrystalline silicon film 3 is formed into a substantially rectangular pattern with both ends slightly larger as shown in FIG. -, it is set to about 94, which is three times that value.

The resistance layer 4 is preferably doped with impurities into the polycrystalline silicon film 3 at the same time as impurity doping for the gate of the MOS transistor. Impurity'#!J'a
It is diffused by degrees. As shown by P4 in FIG. 1(a), this resistance layer 4 is thick at both ends (it is diffused by a narrow pattern P4 in the center, and the width at the center is 311mm, which is the same as the minimum dimension according to the rule).
It is said that

The resistor peripheral layer 5 is n-type, which is opposite to the resistor layer 4, and is a MOS)
It is advantageous to diffuse the source and drain layers of the transistor at the same time, so that their impurity concentration is considerably higher than that of the resistive layer 4, for example, IQ+? It is assumed to be about atom/cj. This introduction of impurities for the resistor peripheral layer 5 is performed in a pattern opposite to the pattern P4 of the resistor layer 4, in other words, the pattern P of the polycrystalline silicon film 3.
This is done over the entire surface of the resistor layer 4 except for the inside of the resistor layer 4, but by thermally diffusing the introduced impurity into the resistor layer 4 by, for example, IJm, the actual diffusion pattern is changed to P5 in the same figure (al). The effective width We at the center is narrowed by 14 from both sides to IIIm.

Thereafter, the polycrystalline silicon film 3 is covered with an insulating film such as the interlayer insulating film 6 in the case of FIG. However, in this embodiment, as shown in the figure, the electrode on the left side can be used as a terminal for connecting to other circuit elements. The left end of the resistive layer 4 is short-circuited with the resistive peripheral layer 5 by bringing I7 into conductive contact with the resistive peripheral layer 5 within the same window.

The polycrystalline silicon resistor of this embodiment configured as above is used by connecting the left electrode film to, for example, a positive power supply terminal, and connecting the right electrode film to a desired location within the integrated circuit. As a result, a voltage is always applied in the reverse bias direction to the junction between the n-type resistance layer 4 and the n-type resistance peripheral layer 5, and the resistance layer 4
The resistance value of the polycrystalline silicon resistor determined by the effective width -e of IIIm described above is maintained stably.

As can be seen from the above, the polycrystalline silicon resistor of the present invention can make the effective width -〇 of the resistance layer 4 narrower than the minimum dimension according to the rules, and the chip area required for its integration can be reduced by about 1 compared to the conventional one.
Can be reduced by digits.

The present invention is not limited to the embodiments described above, and can be implemented in various types of S.
There is no need to always short-circuit the n-type resistor peripheral layer 5, and the electrode WI7 led out from both ends of the p-type resistor layer 4 can be connected to any location within the integrated circuit by applying a positive power supply potential to the n-type resistor peripheral layer 5. It can be used as

The conductivity types of the resistor layer 4 and the resistor peripheral rrI5 may be reversed from those in the example.Also, the resistor layer 4 is diffused over the entire surface of the polycrystalline silicon film, and the resistor peripheral layer 5 is diffused in the pattern of the example. You can also do that.

〔Effect of the invention〕

As described above, in the present invention, a polycrystalline silicon film disposed in a predetermined pattern on an insulating film, a resistor layer diffused into the polycrystalline silicon film of one conductivity type, overlap at least a part of the resistor layer, and surround the resistor. A polycrystalline silicon resistor is formed by a resistor peripheral layer of the other conductivity type diffused in a polycrystalline silicon film in a limiting pattern, and a potential in a reverse bias direction with respect to the resistor layer is applied to the resistor peripheral layer. By using this, the following effects can be obtained.

(a) By limiting the effective width of the resistor layer by the resistor peripheral layer to be narrower than the minimum dimension according to the photo process design rules, the polycrystalline silicon resistor can be made smaller and the required chip area can be reduced by about one order of magnitude compared to the conventional method.

[Yes] Polycrystalline silicon with high sheet resistance is used for the resistor,
In addition, since the effective width of the resistance layer can be narrowed, it is particularly suitable for high resistance applications, and satisfies the demands associated with higher integration of integrated circuit devices, thereby reducing the current consumption thereof.

(C1 By using a highly impurity-concentrated resistance layer with a lower sheet resistance than the conventional polycrystalline Noricon resistor having the same resistance value, variations in resistance value can be reduced and stability can be improved.

(d, 1 Since polycrystalline silicon resistors with normal resistance values can be made very small in size, the element size in an integrated circuit device is 1I).
It becomes possible to incorporate the device into a small space that was not previously available on Il1, etc., and it is possible to eliminate the need to allocate chip area to the resistor.

The present invention particularly advantageously exhibits the above-mentioned effects when applied to highly integrated circuit devices, and contributes to overcoming the bottleneck in achieving high integration.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of a polycrystalline Noricon resistor for semiconductor devices according to the present invention, where <aJ is a top view thereof, and FIG. 0))
is a cross-sectional view taken in the horizontal direction, and fcl is a cross-sectional view taken in the vertical direction. Figure 2 shows an example of a conventional polycrystalline silicon resistor (Al is its top view, and Figure (C) is its cross-sectional view. , 3; polycrystalline silicon film,
4: resistance layer, 5: resistance peripheral layer, 6: interlayer insulating film, 7: electrode film, L: length of resistance film, P4: resistance layer diffusion pattern or impurity introduction pattern for resistance peripheral layer, P5: resistance The diffusion pattern of the peripheral layer, W: width of the resistive film, -e: effective width of the resistive film. (b) La 2l-J2ry:J

Claims (1)

[Claims] 1) A polycrystalline silicon film disposed in a predetermined pattern on an insulating film, and a resistance layer diffused therein with one conductivity type;
A resistor peripheral layer of the other conductivity type is diffused in the polycrystalline silicon film in a pattern that overlaps at least a portion of the resistor layer and limits the resistance from the periphery. A polycrystalline silicon resistor for semiconductor devices, characterized in that it is used in a state where a potential is applied. 2) A resistor according to claim 1, characterized in that the resistive layer is diffused in a generally elongated pattern, and the resistive peripheral layer is diffused in a pattern that surrounds this resistive layer and limits its pattern width. Polycrystalline silicon resistor. 3) A polycrystalline silicon resistor for a semiconductor device according to claim 1, wherein the resistor layer and the resistor peripheral layer are short-circuited at one end of the resistor.