JPS586156A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain contact of a semiconductor device in high density by a method wherein impurities are introduced into a high resistance polycrystalline silicon layer from a contact hole opened in an insulating film on the polycrystlline silicon layer. CONSTITUTION:After an oxide film 15 is formed on a single crystal silicon substrate 14, the polycrystalline silicon layer 16 is formed. Then impurities 17 are doped in the silicon layer 16 to obtain the necessary resistance value. After the interlayer insulating film 18 is formed, the contact hole 19 is opened. Impurities 20 are doped using the film 18 as the mask to form a low resistance polycrystalline silicon layer 21. Then a metal layer 22 is formed, and ohmic contact is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that provides highly variable and easy contact between high resistance polycrystalline silicon and metal.

In recent years, there has been a growing trend to use polycrystalline silicon, which has a low impurity concentration, as a high-resistance material. This is because the resistivity of polycrystalline silicon can be set to a higher value than conventional resistive materials, and the area occupied by the resistor can therefore be reduced.
I cried for a reason. Since polycrystalline silicon is relatively easy to form a multilayer structure, the ability to form high-resistance polycrystalline silicon on top of other elements is also a great advantage. Furthermore, the specific resistance of polycrystalline silicon can be increased by adjusting the impurity concentration introduced, and it is easy to control it, and it is important to note that a stable resistance value can be obtained.

Figure 1 shows an inverter based on an N-channel metal-oxide-semiconductor polished field-effect transistor (hereinafter referred to as MO811 run transistor). Figure 3 (
5(b) shows a method of using high-resistance polycrystalline silicon as a resistor. 1 is an enhancement switching transistor, 2 is a load transistor made of Depreciation glue, and 3 is a load resistor using high-resistance polycrystalline silicon. In this way, high-resistance polycrystalline silicon is used as a load resistor in an inverter circuit, which is a basic circuit, and also as a simple resistive element. Therefore, its applications are very wide.If 1>4, high resistance can be achieved in a small area, so high resistance polycrystalline silicon is expected to be widely used in the future.
It is thought that it will be.

As described above, although high-resistivity polycrystalline silicon has excellent advantages, it also has problems.

In other words, in order to achieve high resistance in polycrystalline silicon, the amount of K must be reduced by adjusting the amount of doped impurities, but for this reason, resistive contact with metal (autoelectrical contact) cannot be obtained. Oh, in that there isn't.

In general, when a semiconductor and a metal come into contact, a shut-off barrier is formed due to the difference in work relationship, and diode bulging characteristics are observed. A normal semiconductor that uses metal as wiring! ! In metals, the contact with the semiconductor must be direct, and it is inconvenient for the diode conductivity to be 111111-J, so an electrical contact between the metal and the semiconductor is required. In some cases, many impurities are introduced into the semiconductor to make the barrier wider and thinner, inducing tunneling. If the width of the barrier is very thin, the tunneling effect allows the carriers to move freely between the metal and the semiconductor, resulting in an open electrical contact.

In order to obtain an electrical contact between high-resistance polycrystalline silicon and metal, there is one reason mentioned above.

At least the polycrystalline silicon in the tortoise contact region needs to be doped with a large amount of impurity. However, since the impurity concentration in high-resistance polycrystalline silicon should originally be low, it is necessary to increase the impurity concentration in the contact region with metal. For this reason, in the past, a mask was formed using the 7-odds technology, and impurities were doped into the polycrystalline silicon in the contact dominant area.Hereinafter, using #1211, The conventional method of forming contacts between highly anti-polycrystalline silicon and gold 1 will be described in detail.

No. 211 is an example of a conventional contact forming method. As shown in No. 211(a), after oxidizing lF5 is carved onto a single crystal silicon substrate 4, polycrystalline silicon 6 is formed. After this, K to obtain the desired resistance value.

The required amount of impurity 7 is doped into polycrystalline silicon 6. Since the amount of doping is usually very small, the ion bombardment method is used from the viewpoint of controllability and stability. ), impurities are heavily doped into the polycrystalline silicon located in the metal contact region. In this case, the region heavily doped with impurities is selected using photolithography technology.Usually, impurity 9 is introduced into the contact region using a photoresist 8 patterned by photolithography as a mask. Ion implantation is used to introduce the impurities that form the low-resistance polycrystalline silicon 10 that contains many impurities, and in this case, the mask material may be a thin film outside the photoresist cut. Alternatively, impurities may be introduced by thermal diffusion using a heat-resistant thin film as a mask. Next, remove the mask material and make one layer like @211(o)0.
After forming 111, a contact hole 12 for obtaining contact between polycrystalline silicon and metal is taken. After that, as shown in FIG. #2 (a), as a result of 0 or more forming the ◆ group 13, an over-current contact between the polycrystalline silicon and the metal is formed.

As is clear from the above description, the conventional method has the following drawbacks. That is, photophosphorography technology is used to select regions to be heavily doped with impurities. This complicates manufacturing needs and increases costs. Furthermore, it also causes a decrease in yield.

*Also, since it is necessary to allow for alignment errors, it is necessary to set the area of the bud region heavily doped with impurities to be larger than the contact hole. For this reason.

There are limits to high integration.

The present invention eliminates these drawbacks and forms a region heavily doped with impurities by self-alignment with the contact hole (40'1%). below.

A detailed explanation of the present invention will be given with reference to FIG.

No. ss#i is - indicating the manufacturing method of the present invention.

First, as shown in No. 5111(a), after forming oxide 1[15 on single crystal silicon base 1[14], polycrystalline silicon 16 is formed. After this, the necessary amount of impurity 17 is doped into the polycrystalline silicon 16 in order to obtain the desired resistance value. A contact hole 19 is opened in order to make contact between the bale on which the interlayer insulating film 18 is formed, the polycrystalline silicon, and the metal. Conventionally, impurities are heavily doped into the contact area using photolithography technology. However, in the present invention, as shown in FIG. 3(c), the interlayer insulating film formed previously is
1B! As a step, impurity 20 is heavily doped into polycrystalline silicon through contact hole 19 to form low-resistance polycrystalline silicon 21 containing many impurities. The ion implantation λ method or the thermal diffusion method may be used to introduce the impurity.The main point of this method is to introduce the impurity into the polycrystalline silicon through the contact hole in a self-exchanging manner. There are features of the invention.

Finally, metal 22 is formed as shown in No. 311EI (a) to obtain an open Z contact.

As is clear from the above description, according to the present invention, one step of photolithography, which was conventionally performed, is unnecessary in order to position the area of polycrystalline silicon heavily doped with impurities by positioning the contact hole AKj. becomes. For this reason,
The manufacturing process T1 is simplified, and cost reduction and yield improvement can be realized.

Furthermore, since the region heavily doped with impurities is formed by self-alignment, there is no need to allow for alignment errors, and therefore, it is possible to increase the integration of the device.

As described above, the present invention has advantages in that it achieves high integration, simplification of manufacturing, cost reduction, and improvement in yield by forming a region heavily doped with impurities to be glossy by self-alignment. There are some things that have certain effects.

[Brief explanation of the drawing]

Figures 1111(1111) and 1111(a) are diagrams showing an inverter ll1llI using an N-channel MO8 glue transistor. Second, #5 Figures (a) to (b) are diagrams showing the method for manufacturing the semiconductor substrate of the present invention. Applicant: Kinsha Co., Ltd. - Hoseikosha Fushido, Bento 1, Tsutomu Mogami Figure 1

Claims (1)

[Claims] Semiconductor using high-resistance polycrystalline silicon as a load resistor @
* The semiconductor device characterized in that impurities are introduced into the high resistance polycrystalline silicon through contact holes opened in an insulating layer on the high resistance polycrystalline silicon.