JPH027556A - Input protection device of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve static electricity withstand voltage and achieve a universal wafer production process by making first and second field-effect type transistors to be the same channel conductive type and intervening a first resistor and a second resistor between the gate and high-voltage source of the first transistor and the gate and low-voltage source of the second transistor, respectively. CONSTITUTION:A Pch BVDS transistor Q1 is connected between an aluminum electrode 1 for input bonding pad and VCC power supply and a polysilicon resistance layer 2 with a resistance of 200 ohms which is the same as the gate electrode is connected between the gate electrode and VCC power supply. On the other hand, the Pch BVDS and a transistor Q2 are connected between the aluminum electrode for input bonding pad 1 and a VSS power supply and a polysilicon resistance layer 3 with a resistance of 200 ohms which is the same as the gate electrode is connected between the gate electrode and the aluminum electrode for input bonding pad 2. As a result, it does not cause static electricity withstand voltage to be reduced and eliminates the need for constituting the wafer production process in two-layer polysilicon structure, thus achieving a universal wafer-production process.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an input protection device for a semiconductor integrated circuit, and particularly to an input protection device for a complementary semiconductor integrated circuit between an input terminal and a VCC power supply and
An input protection device configured by inserting a BVDS transistor between the S terminals is connected to the input protection device.

[Prior Art] Conventionally, this type of input protection device has a Pch type BVDS between the input terminal and the VCC power supply and between the VSS power supply.
) transistor and an Nch type BV DS transistor, or both Nch type BVPS) transistors were inserted as an input protection device.

[Problems to be solved by the invention] The conventional input protection device described above is
) Since a transistor is used, N is used for the ohmic connection between the Nch diffusion layer and the commonly used aluminum wiring layer to prevent aluminum penetration into the N+ diffusion layer.
+ Ohmic connections had to be made through a layer of polycrystalline silicon doped with impurities. Therefore, a wafer manufacturing process that employs a 2N polysilicon structure is required, and there is a drawback in that the manufacturing process is limited.

[Differences between the invention and the prior art] In contrast to the conventional input protection device described above, the present invention
) transistors are both Pch type BVDS) transistors, and the gate electrode of the Pch BVDS' transistor connected between the input terminal and the SS terminal is connected to the input terminal via a resistance element with a predetermined resistance value. The difference is that they are connected.

[Means for Solving the Problems] The gist of the present invention is to provide a first field effect transistor provided between an input terminal and a high voltage source, and a first field effect transistor provided between an input terminal and a low voltage source. In an input protection device for a semiconductor integrated circuit having two field effect transistors, the first field effect transistor and the second field effect transistor are of the same channel conductivity type, and the gate of the first field effect transistor and the high voltage transistor are of the same channel conductivity type. A first resistor is interposed between the voltage source and a second resistor between the gate of the second field effect transistor and the low voltage source.

[Example code] Fortress cliff 1 Next, the present invention will be explained through examples.

FIG. 1 is a plan view showing a layout pattern of a first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1. A PchBVDS) transistor Q1 is connected between the input bonding pad aluminum electrode 1 and the CC power supply, and a polysilicon resistance layer 2, which is the same as the gate electrode and has a resistance of 200 ohms, is connected to the gate electrode between the CC power supply and the input bonding pad aluminum electrode 1. Connect to. On the other hand, a PchBVDS and a transistor Q are connected between the input bonding pad aluminum electrode 1 and the VSS power supply.
2 is connected to the gate electrode, and a polysilicon resistance layer 3 having the same resistance as the gate electrode having a resistance of 200 ohms is connected between the input bonding pad aluminum electrodes 1. The gate input wiring is done by extending the aluminum wiring layer for the input bonding pad.

yJU EXAMPLE FIG. 3 is an equivalent circuit diagram of a second embodiment of the present invention. 1st
The difference from the embodiment is that a P-type diffused resistor R formed by extending the drain region of the input protection PchBVDS transistor is inserted between the input terminal 11 and the input gate. An improvement in electrostatic withstand voltage can be expected due to the effect of further suppressing the increase in potential of the input gate electrode.

[Effects of the Invention] In the present invention, the first
In an input protection device for a semiconductor integrated circuit having a field effect transistor and a second field effect transistor provided between an input terminal and a low voltage source, the first field effect transistor and the second field effect transistor are provided. and a transistor of the same channel conductivity type, a first resistor between the gate of the first field effect transistor and the high voltage source, and a first resistor between the gate of the second field effect transistor and the low voltage source. By interposing two resistors, the electrostatic withstand voltage does not deteriorate, and the wafer manufacturing process can be easily
Eliminating the need for layered polysilicon configurations provides versatility in the wafer fabrication process.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a layout pattern of a first embodiment of the invention, FIG. 2 is an equivalent circuit diagram of the first embodiment, and FIG. 3 is an equivalent circuit diagram of a second embodiment of the invention. 1.11... Aluminum electrode for input bonding pad, 2, 3. 22. 23...Polysilicon resistance element, Ql. Q2/P channel BVDS) Langsta O

Claims (1)

[Claims] An input protection device for a semiconductor integrated circuit, comprising a first field effect transistor provided between an input terminal and a high voltage source, and a second field effect transistor provided between the input terminal and a low voltage source. The first field effect transistor and the second field effect transistor are of the same channel conductivity type, and a first resistor is provided between the gate of the first field effect transistor and the high voltage source, and the second field effect transistor is of the same channel conductivity type. 1. An input protection device for a semiconductor integrated circuit, characterized in that a second resistor is interposed between the gate of a field effect transistor and a low voltage source.