JPS62155548A - Electrostatic protective circuit element for semiconductor integrated circuit - Google Patents

Electrostatic protective circuit element for semiconductor integrated circuit

Info

Publication number
JPS62155548A
JPS62155548A JP29690285A JP29690285A JPS62155548A JP S62155548 A JPS62155548 A JP S62155548A JP 29690285 A JP29690285 A JP 29690285A JP 29690285 A JP29690285 A JP 29690285A JP S62155548 A JPS62155548 A JP S62155548A
Authority
JP
Japan
Prior art keywords
diffusion layer
substrate
protective resistor
input
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29690285A
Other languages
Japanese (ja)
Inventor
Yasushi Kawakami
靖 川上
Takeshi Ando
毅 安東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29690285A priority Critical patent/JPS62155548A/en
Publication of JPS62155548A publication Critical patent/JPS62155548A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the short circuits among input/output terminals and substrate potential by simple structure by forming a diffusion layer having a conductivity type different from that of a semiconductor substrate just under junction sections among the terminals and polycrystalline silicon. CONSTITUTION:Input/output terminals 3 are connected to a protective resistor 4, and connected to other elements from other terminals, but a diffusion layer 15 having a conductivity type different from that of a substrate 11 is formed just under polycrystalline silicon in the protective resistor 4, the diffusion layer 15 is particularly isolated from other diffusion layers, and the diffusion layer 15 is not supplied with potential and is brought to a floating state. Consequently, thickness corresponding to the depth of a diffusion layer is added to the thickness of a conventional insulating film 12 among sections up to the substrate 11 from junction regions 14 among conventional input/output terminals and protective resistor, thus acquiring an electrostatic protective circuit element in which field breaking strength to the substrate is further increased. When a region such as a well region in a complementary MOS integrated circuit device is used as the diffusion layer 15, no process is added, and the titled element can be realized at cost the same as conventional devices.

Description

【発明の詳細な説明】 〔′産業上の利用分野〕 本発明は半導体集積回路の静電保護回路素子に関する。[Detailed description of the invention] ['Industrial application field] The present invention relates to an electrostatic protection circuit element for a semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

従来、この種の静電保護回路素子は、第2図で示すよう
に端子3が保護抵抗4を介し、保護ダ、イオード7,8
に接続され、さらに保護抵抗9を介して保護すべき素子
10(ここではインバータ)のゲートに接続される構成
になっており、さらに保護抵抗4は半導体基板上の酸化
膜上に作られていた。静電気が端子3に印加された場合
に、抵抗4とダイオード7あるいは8を介して正又は負
の電源端子1,2に流すことにより保護すべき素子10
にはダイオードの両端電圧程度の低い電圧しか印加され
ないようにして保護している。ここで5.6はダイオー
ド7.8の内部抵抗である。
Conventionally, in this type of electrostatic protection circuit element, as shown in FIG.
and further connected to the gate of an element 10 (inverter in this case) to be protected via a protective resistor 9, and the protective resistor 4 was formed on an oxide film on the semiconductor substrate. . Element 10 to be protected by flowing it to the positive or negative power terminals 1 and 2 via the resistor 4 and the diode 7 or 8 when static electricity is applied to the terminal 3.
is protected by applying only a voltage as low as the voltage across the diode. Here, 5.6 is the internal resistance of the diode 7.8.

第3図は従来の静電保護回路素子の保護抵抗部の断面図
である。第3図に於て、11は基板で、基板11上に酸
化膜12が形成され、酸化膜12上に多結晶シリコンよ
りなる保護抵抗4が形成され、保護抵抗4は絶縁層13
で被覆され、保護抵抗4の両端部に開口が設けられ端子
3が設けられている。なお16は表面保護膜である。
FIG. 3 is a sectional view of a protective resistor section of a conventional electrostatic protection circuit element. In FIG. 3, 11 is a substrate, an oxide film 12 is formed on the substrate 11, a protective resistor 4 made of polycrystalline silicon is formed on the oxide film 12, and the protective resistor 4 is connected to an insulating layer 13.
The protective resistor 4 is coated with an opening and a terminal 3 is provided at both ends of the protective resistor 4. Note that 16 is a surface protective film.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の保護抵抗4は、第3図の断面図で示した
ように、半導体基板11上の酸化[12の上に形成され
ているため、静電気が端子3と基板11間に印加される
と端子3と保護抵抗4との接合領域4から多結晶シリコ
ン4、酸化膜12を介して基板11に電界破壊を起し、
端子3と基板11が電気的に短絡してしまうという問題
がある。
As shown in the cross-sectional view of FIG. 3, the conventional protective resistor 4 described above is formed on the oxidized layer 12 on the semiconductor substrate 11, so that static electricity is applied between the terminal 3 and the substrate 11. An electric field breakdown occurs in the substrate 11 from the junction region 4 between the terminal 3 and the protective resistor 4 through the polycrystalline silicon 4 and the oxide film 12.
There is a problem in that the terminal 3 and the substrate 11 are electrically short-circuited.

本発明の目的は、従来の問題点を除去し、簡単な構造で
端子と基板電位との短絡を防止できる半導体集積回路の
静電保護回路素子を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an electrostatic protection circuit element for a semiconductor integrated circuit that eliminates the problems of the conventional art and can prevent short circuits between terminals and substrate potential with a simple structure.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体集積回路の静電保護回路素子は、半導体
基板上で直接多結晶シリコンに接続される入出力端子を
有する半導体集積回路の静電保護回路素子において、少
なくとも前記入出力端子と多結晶シリコンとの接合部の
直下に前記半導体基板と異なる導電型を有する拡散層が
形成されている構造を有している。
An electrostatic protection circuit element for a semiconductor integrated circuit according to the present invention is an electrostatic protection circuit element for a semiconductor integrated circuit having an input/output terminal directly connected to polycrystalline silicon on a semiconductor substrate. It has a structure in which a diffusion layer having a conductivity type different from that of the semiconductor substrate is formed directly below the junction with silicon.

〔実施例〕〔Example〕

第1図(a)、(b)は、本発明の一実施例の平面図及
び断面図である。
FIGS. 1(a) and 1(b) are a plan view and a sectional view of an embodiment of the present invention.

第1図(a)、(b)に示すように実施例は入出力端子
3が保護抵抗4に接続され、他端から池素子へ接続され
るが、その保護抵抗4の多結晶シリコンの直下に基板1
1と異なる導電型をもつ拡散層15を形成し、とくに拡
散層15は、他の拡散層とは分離し、拡散層15には、
電位を供給せずフローティングとする。しかるときは、
従来入出力端子と保護抵抗の接合領域14から基板11
との間に従来の絶縁膜12の厚さに拡散層の深さ分の厚
さが加えられたことになるので、基板への電界破壊強度
が一層高められた静電保護回路素子が得られる。尚、拡
散層15としては例えは相補型MOS集積回路装置のウ
ェル領域を用いれば工程の追加はなく、従来と同じ価格
で実現できる。
As shown in FIGS. 1(a) and 1(b), in the embodiment, the input/output terminal 3 is connected to the protective resistor 4, and the other end is connected to the pond element, but directly below the polycrystalline silicon of the protective resistor 4. board 1
In particular, the diffusion layer 15 is separated from other diffusion layers, and the diffusion layer 15 has a conductivity type different from that of the diffusion layer 15.
Floating without supplying potential. When scolded,
From the conventional input/output terminal and protective resistor junction area 14 to the board 11
Since the thickness corresponding to the depth of the diffusion layer is added to the thickness of the conventional insulating film 12, an electrostatic protection circuit element with further increased electric field breakdown strength to the substrate can be obtained. . Incidentally, if a well region of a complementary MOS integrated circuit device is used as the diffusion layer 15, no additional process is required and the cost can be the same as that of the conventional method.

また、第1図では、保護抵抗4の直下すべてに拡散層1
5を形成しているが、保護抵抗4の接合領域14の直下
のみに拡散層を形成してもよい。
In addition, in FIG. 1, there is a diffusion layer 1 immediately below the protective resistor
However, a diffusion layer may be formed only directly under the junction region 14 of the protective resistor 4.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、多結晶シリコンの保護抵
抗の下に拡散層を形成することで、端子と保護抵抗の接
合領域から基板までの絶縁領域が基板上に形成した絶縁
膜の厚さから拡散層の深さ分の厚さが加えられ、基板へ
の電界破壊強度を一層高めることができる。
As explained above, in the present invention, by forming a diffusion layer under a polycrystalline silicon protective resistor, the insulating region from the junction area of the terminal and the protective resistor to the substrate has the thickness of the insulating film formed on the substrate. The thickness corresponding to the depth of the diffusion layer is added to the layer, and the electric field breakdown strength to the substrate can be further increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)は、本発明の一実施例の平面図お
よび断面図、第2図は、従来の一般的な入力保護回路図
、第3図は、従来の静電保護回路素子の断面図である。 1.2・・・電源、3・・・端子、4.9・・・保護抵
抗、5.6・・・抵抗、7.8・・・保護ダイオード、
10・・・インバータ、11・・・基板、12・・・酸
化膜、13・・・絶縁層、14・・・接合部、15・・
・拡散層、16・・・表面保護膜。
Figures 1 (a) and (b) are a plan view and a sectional view of an embodiment of the present invention, Figure 2 is a conventional general input protection circuit diagram, and Figure 3 is a conventional electrostatic protection circuit diagram. FIG. 3 is a cross-sectional view of a circuit element. 1.2... Power supply, 3... Terminal, 4.9... Protection resistor, 5.6... Resistor, 7.8... Protection diode,
DESCRIPTION OF SYMBOLS 10... Inverter, 11... Substrate, 12... Oxide film, 13... Insulating layer, 14... Joint part, 15...
- Diffusion layer, 16... surface protection film.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上で直接多結晶シリコンに接続される入出力
端子を有する半導体集積回路の静電保護回路素子におい
て、少なくとも前記入出力端子と多結晶シリコンとの接
合部の直下に前記半導体基板と異なる導電型を有する拡
散層が形成されていることを特徴とする半導体集積回路
の静電保護回路素子。
In an electrostatic protection circuit element for a semiconductor integrated circuit having an input/output terminal directly connected to polycrystalline silicon on a semiconductor substrate, there is a conductive layer different from that of the semiconductor substrate immediately below the junction between the input/output terminal and the polycrystalline silicon. An electrostatic protection circuit element for a semiconductor integrated circuit, characterized in that a diffusion layer having a shape is formed.
JP29690285A 1985-12-27 1985-12-27 Electrostatic protective circuit element for semiconductor integrated circuit Pending JPS62155548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29690285A JPS62155548A (en) 1985-12-27 1985-12-27 Electrostatic protective circuit element for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29690285A JPS62155548A (en) 1985-12-27 1985-12-27 Electrostatic protective circuit element for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS62155548A true JPS62155548A (en) 1987-07-10

Family

ID=17839634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29690285A Pending JPS62155548A (en) 1985-12-27 1985-12-27 Electrostatic protective circuit element for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS62155548A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01286459A (en) * 1988-05-13 1989-11-17 Nec Corp Protecting device for semiconductor integrated circuit
US8269312B2 (en) * 2008-06-05 2012-09-18 Rohm Co., Ltd. Semiconductor device with resistive element

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6144454A (en) * 1984-08-09 1986-03-04 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6144454A (en) * 1984-08-09 1986-03-04 Fujitsu Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01286459A (en) * 1988-05-13 1989-11-17 Nec Corp Protecting device for semiconductor integrated circuit
US8269312B2 (en) * 2008-06-05 2012-09-18 Rohm Co., Ltd. Semiconductor device with resistive element

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