JPS5929455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5929455A JPS5929455A JP13937182A JP13937182A JPS5929455A JP S5929455 A JPS5929455 A JP S5929455A JP 13937182 A JP13937182 A JP 13937182A JP 13937182 A JP13937182 A JP 13937182A JP S5929455 A JPS5929455 A JP S5929455A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- contact
- semiconductor
- conductivity type
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Abstract
Description
【発明の詳細な説明】 本発明は集積回路装ｆｉ！ｉ：（ＩＣ）に関する。[Detailed description of the invention] The present invention provides an integrated circuit device fi! i: Regarding (IC).
近年、１「子機器の信頼性に対する要求が高まるにつれ
て、ＩＣ自体の信頼性も高いことが必要となってきた。In recent years, as the demand for reliability of child devices has increased, it has become necessary for the IC itself to be highly reliable.
その信頼性を低下させる要因の一つに、ＩＣ内部回路素
子の静電破壊が有り、これはＩＣ機能の破壊才たは特性
不良等を引き起すことになり信頼性上問題となる。従来
のバイポーラ■Ｃにおいて、例えばＩＣ内部の抵抗素子
の一端の電極がボンディング配線によって直接入出力端
子に導ひかれている場合、前述の抵抗素子の金属電極と
抵抗領域との接続部（コンタクト部）のそれぞれの面状
は通常、内部回路素子に用いられている標準的なコンタ
クト部の面積と等しいものを用いていた。One of the factors that lowers the reliability is electrostatic damage to IC internal circuit elements, which causes damage to IC functions or poor characteristics, which poses a problem in terms of reliability. In a conventional bipolar ■C, for example, if the electrode at one end of the resistance element inside the IC is directly led to the input/output terminal by bonding wiring, the connection part (contact part) between the metal electrode of the resistance element and the resistance region mentioned above. The shape of each surface is usually equal to the area of standard contact portions used in internal circuit elements.
ここで、従来構造の抵抗素子の平面図を第１図に、また
第２図に第１図中のＸ−Ｘ による断面図をそれぞれ示
す。第１図及び第２図における半導体装置は以下の工程
を経て製造される。まず、ｐ＋型型半導体基板１ニ１
長層１０２を形成し、熱拡散により形成されるｐ＋＋半
導体領域によって分離領域を形成する。前述分離領域中
にｐ型半導体抵抗領域１０４を熱拡散及び酸化すること
により形成し、同時に絶縁膜１０５を形成する。その後
、ｐ型半導体抵抗領域１０４に電極を設けるため絶縁膜
１０５にエツチングを施してｐ型半導体抵抗領域１０４
との接続部（コンタクト部）１０６を形成し、前述コン
タクト部１０６を金属電極１０７によって包囲した半導
体装置が完成する。また１０８は内部素子間等を接続す
る金属配線であり、１０９は金属電極１０７を入出力端
子に接続するためのポンディングパッドであることを示
す。Here, FIG. 1 shows a plan view of a resistive element having a conventional structure, and FIG. 2 shows a sectional view taken along line X--X in FIG. 1, respectively. The semiconductor devices shown in FIGS. 1 and 2 are manufactured through the following steps. First, a long layer 102 of a p+ type semiconductor substrate 1 is formed, and an isolation region is formed by a p++ semiconductor region formed by thermal diffusion. A p-type semiconductor resistance region 104 is formed in the aforementioned isolation region by thermal diffusion and oxidation, and at the same time an insulating film 105 is formed. After that, the insulating film 105 is etched to provide an electrode in the p-type semiconductor resistance region 104.
A semiconductor device is completed in which a connection portion (contact portion) 106 is formed and the contact portion 106 is surrounded by a metal electrode 107. Further, 108 is a metal wiring for connecting internal elements, etc., and 109 is a bonding pad for connecting the metal electrode 107 to an input/output terminal.
次に前述した従来構造の抵抗素子を用いた場合の欠点を
示ず。例えば、正の電荷（数百ピコファラッドのコンア
ン→）°−に数百ボルトの電圧を印加した場合の蓄積電
荷に相当）が帯電している人体が従来構造の抵抗素子を
内蔵したバイポーラＩＣを電子機器に実装する段階で、
前述した入出力端子が人体と接触し、かつＩＣの基板電
位にある端子が接地箱１位にあった場合、入出力端子か
ら抵抗素子のコンタクト部１０６及びｐ型半導体抵抗領
域１０４を通じてｐ型半導体１０１へ前述の帯電電荷が
過大電流となって流れる。この時、コンタクト部１０６
のコンタクト抵抗によるジュール熱のため抵抗素子のコ
ンタクト部１０６刊近の金属電極１０７が溶解し、さら
にはｐ型半導体抵抗領域１０４内部深く浸入してｐ型半
導体抵抗領域１０４とｎ型半導体の気相成長層１０２と
の接合部を破壊する。この結果、入出力の耐圧不良もし
くは短絡状態を生じ信頼性を低下させる。Next, the disadvantages of using the conventionally structured resistor element described above will not be shown. For example, if a human body is charged with a positive charge (equivalent to the accumulated charge when a voltage of several hundred volts is applied to a conant of several hundred picofarads), a bipolar IC with a built-in resistive element of conventional structure is At the stage of implementation in electronic equipment,
When the input/output terminal mentioned above comes into contact with the human body and the terminal at the substrate potential of the IC is in the ground box 1 position, the p-type semiconductor is connected to the input/output terminal through the contact portion 106 of the resistor element and the p-type semiconductor resistance region 104. The above-mentioned electrical charge flows to 101 as an excessive current. At this time, the contact part 106
The metal electrode 107 near the contact portion 106 of the resistance element melts due to the Joule heat caused by the contact resistance, and further penetrates deeply into the p-type semiconductor resistance region 104, causing a vapor phase between the p-type semiconductor resistance region 104 and the n-type semiconductor. The joint with the growth layer 102 is destroyed. As a result, poor input/output voltage resistance or short circuits occur, reducing reliability.
本発明の目的はプロセス変更や、面状の過大な拡大を招
くことなく大幅にバイポーラＩＣの静電破壊耐圧の向上
をはかることにある。An object of the present invention is to significantly improve the electrostatic breakdown voltage of a bipolar IC without changing the process or excessively enlarging the surface.
本発明は一導電型の半導体基体と、該半導体基体の一側
面から内部に形成された反対導′区型の半導体領域と、
前記半導体基体及び反対導電型の半導体領域の表面上に
形成された絶縁層と、前記反対導電型の半導体領域表面
上の絶縁層が少なくとも二つの開口部を有し、該開口部
を介して前記反対導１に型の半導体領域に接続された金
属１１１極とを含む半導体装置において、前記開口部の
少なくとも一つが他の開口部の面積よりも広いことを特
徴とする。The present invention includes a semiconductor substrate of one conductivity type, a semiconductor region of an opposite conductivity type formed inside from one side of the semiconductor substrate,
The insulating layer formed on the semiconductor substrate and the surface of the semiconductor region of opposite conductivity type, and the insulating layer on the surface of the semiconductor region of opposite conductivity type have at least two openings, and the A semiconductor device including a metal 111 pole connected to a semiconductor region of a type with an opposite conductor 1, characterized in that at least one of the openings is wider in area than the other openings.
次に、本発明を実施例により説明する。Next, the present invention will be explained by examples.
第１の実施例は、第３図の平面図で示されるような抵抗
素子であり、第４図は第３図中のｘ−ｘ’による断面図
である。図中の連続番号は従来構造の第１図及び第２図
中に示すものと同じであって構造がほぼ同じであること
を示唆している。ただし、第３図及び第４図において電
極のコンタクト部１０６ （ｂ）が１０６ （ａ）の面
接よりも広いことを／ｉ？徴とする。第２の実施例を第
５図に示す。第５図において、コンタクト部の形状を円
形として用いることにより更に静電破壊に強い抵抗素子
を実現できる。The first embodiment is a resistance element as shown in the plan view of FIG. 3, and FIG. 4 is a cross-sectional view taken along line xx' in FIG. 3. The serial numbers in the figures are the same as those shown in FIGS. 1 and 2 of the conventional structure, indicating that the structures are substantially the same. However, in FIGS. 3 and 4, the contact portion 106 (b) of the electrode is wider than the surface area 106 (a) /i? be a sign. A second embodiment is shown in FIG. In FIG. 5, by using a circular shape for the contact portion, a resistive element that is even more resistant to electrostatic damage can be realized.
このような抵抗素子を用いることによりコンタクト部の
コンタクト抵抗が従来のコンタクト抵抗よりも小さくな
るため、コンタクト部に発生ずるジュール熱が小さくな
るとともに箱５界の集中を防ぐことが出来る。この結果
、前述した帯電電荷による静電破壊耐圧の著しい向上が
図れた。以上のように本発明は抵抗素子にのみ限定され
るものではないことはいうまでもない。By using such a resistance element, the contact resistance of the contact portion becomes smaller than the conventional contact resistance, so that the Joule heat generated in the contact portion is reduced and concentration of the box 5 field can be prevented. As a result, the electrostatic breakdown voltage caused by the above-mentioned electrical charge was significantly improved. As described above, it goes without saying that the present invention is not limited only to resistive elements.
第１図は従来構造による抵抗素子の平面図であり、第２
図は第１図中のｘ−ｘ’による断面図である。第３図は
本発明による構造の抵抗素子の平面図であり、第４図は
第３図中のｘ−ｘ’による断面図である。第５図はコン
タクト部の形状を円形にしたものである。
１０１・・・・・・ｐ生型半導体基板、１０２・・・・
・・ｎ型気相成長層、１０３・・・・・・ｐ十型絶縁領
域、１０４・・・・・・ｐ型半導体抵抗領域、１０５・
・・・・・絶縁層、１０６・・・・・・電極のコンタク
ト部、１０７・・・・・・金属１；Ｌ極、１０８・・・
・・・ボンティング配線、１０９・・・・・ポンディン
グパッド。FIG. 1 is a plan view of a resistance element with a conventional structure.
The figure is a sectional view taken along line xx' in FIG. 1. FIG. 3 is a plan view of a resistance element having a structure according to the present invention, and FIG. 4 is a cross-sectional view taken along line xx' in FIG. In FIG. 5, the shape of the contact portion is circular. 101...P-type semiconductor substrate, 102...
. . . N-type vapor phase growth layer, 103 . . . P-type insulation region, 104 . . . P-type semiconductor resistance region, 105.
... Insulating layer, 106 ... Contact part of electrode, 107 ... Metal 1; L pole, 108 ...
...bonting wiring, 109...bonding pad.
Claims (1)
部に形成された反対導電型の半導体領域と、前記半導体
基体及び反対導電型の半導体領域の表面上に形成された
絶縁層と、前記反対導ｖＬ型の半導体領域表面上の絶縁
層が少なくとも二つの開口部を有し、該開口部を介して
前記反対導電型の半導体領域に接続された金属電極とを
含む半導体装置において、前記開口部の少なくとも一つ
が他の開口部の面撰よりも広いことを特徴とするバイポ
ーラ集積回路を含む半導体装置。a semiconductor substrate of one conductivity type; a semiconductor region of an opposite conductivity type formed inside from one side of the semiconductor substrate; an insulating layer formed on the surfaces of the semiconductor substrate and the semiconductor region of the opposite conductivity type; In a semiconductor device, an insulating layer on a surface of a semiconductor region of opposite conductivity type VL has at least two openings, and a metal electrode connected to the semiconductor region of opposite conductivity type through the openings. 1. A semiconductor device including a bipolar integrated circuit, wherein at least one of the openings is wider than other openings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13937182A JPS5929455A (en) | 1982-08-11 | 1982-08-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13937182A JPS5929455A (en) | 1982-08-11 | 1982-08-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5929455A true JPS5929455A (en) | 1984-02-16 |
Family
ID=15243764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13937182A Pending JPS5929455A (en) | 1982-08-11 | 1982-08-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5929455A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144457A (en) * | 1984-08-09 | 1986-03-04 | Nec Corp | Static type semiconductor memory |
| JPH04107709U (en) * | 1991-02-27 | 1992-09-17 | 松下電器産業株式会社 | belt conveyor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54160186A (en) * | 1978-06-09 | 1979-12-18 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS56146277A (en) * | 1980-04-15 | 1981-11-13 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-08-11 JP JP13937182A patent/JPS5929455A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54160186A (en) * | 1978-06-09 | 1979-12-18 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS56146277A (en) * | 1980-04-15 | 1981-11-13 | Toshiba Corp | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6144457A (en) * | 1984-08-09 | 1986-03-04 | Nec Corp | Static type semiconductor memory |
| JPH04107709U (en) * | 1991-02-27 | 1992-09-17 | 松下電器産業株式会社 | belt conveyor device |
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