JPS62172739A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS62172739A JPS62172739A JP1411086A JP1411086A JPS62172739A JP S62172739 A JPS62172739 A JP S62172739A JP 1411086 A JP1411086 A JP 1411086A JP 1411086 A JP1411086 A JP 1411086A JP S62172739 A JPS62172739 A JP S62172739A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- polycrystalline silicon
- diffusion layer
- intermediary
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 230000008018 melting Effects 0.000 claims 1
- 238000002844 melting Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 12
- 239000010410 layer Substances 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の構造に関し、特に過大電流で
ポリシリコン配線や金属配線を切断する事でスイッチの
役割を果たす、いわゆるヒユーズ素子の構造に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the structure of semiconductor integrated circuits, and in particular to the structure of so-called fuse elements that play the role of switches by cutting polysilicon wiring or metal wiring due to excessive current. Regarding.
またEND保護素子としてのポリシリコン抵抗素子の構
造に関する。The present invention also relates to the structure of a polysilicon resistance element as an END protection element.
従来、半導体集積回路は、スイッチ素子としてマスクR
OMを多用してきたが、少量、多品種に対応すべく、電
気的ストレスでデータを書き込めるヒユーズROM、E
PROM等が使われ始めた。Conventionally, a semiconductor integrated circuit uses a mask R as a switch element.
We have been using OM extensively, but in order to handle small quantities and a wide variety of products, we have developed fuse ROM, E, which can write data with electrical stress.
PROM etc. began to be used.
一方、ESD保護素子としてもポリシリコン抵抗は従来
から使用されている。これらの素子は、半導体基板上に
絶縁膜を介して形成されてい九〇(第3図参照)
〔発明が解決しようとする問題点〕
上述した従来のヒユーズ素子・ポリシリコン抵抗は、基
板上に絶縁膜を介して形成されるため、特に短かいパル
ス幅の電気的パルス、例えば小容量体から放電される高
電圧の静電気パルス等で絶縁膜破壊を生ずる事があった
。特にヒユーズ素子・ポリシリコン抵抗の一端子が外部
端子として用いられる場合に、この危険度が高い。その
ため、ヒユーズ素子やポリシリコン抵抗と半導体基板の
ショ−ト不良が生ずる。On the other hand, polysilicon resistors have also been conventionally used as ESD protection elements. These elements are formed on a semiconductor substrate via an insulating film (see Figure 3). [Problems to be solved by the invention] The conventional fuse element/polysilicon resistor described above is Since it is formed through an insulating film, the insulating film may be broken by an electrical pulse with a particularly short pulse width, such as a high voltage electrostatic pulse discharged from a small capacitor. This risk is particularly high when one terminal of a fuse element or polysilicon resistor is used as an external terminal. As a result, a short circuit failure occurs between the fuse element or the polysilicon resistor and the semiconductor substrate.
本発明のヒユーズ素子・ポリシリコン抵抗は、ポリシリ
コン抵抗または金属膜直下に絶縁膜を介して拡散層が設
けである。(第1図)そのため前述した絶縁膜の破壊が
生じてもヒユーズ素子・ポリシリコン抵抗は基板と接合
で絶縁された拡散層とショートし、基板とはショートし
ない。In the fuse element/polysilicon resistor of the present invention, a diffusion layer is provided directly under the polysilicon resistor or metal film with an insulating film interposed therebetween. (FIG. 1) Therefore, even if the above-described breakdown of the insulating film occurs, the fuse element/polysilicon resistor will short-circuit with the diffusion layer insulated by the junction with the substrate, and will not short-circuit with the substrate.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図、第2図はそれぞれ本発明の一実施例の縦断面図
と平面図である。N型基板6上にpwel15を形成し
、その上にシリコン酸化膜4を介してヒユーズ素子、あ
るいはポリシリコン抵抗2を形成する。更にシリコン酸
化膜3を介してAt電極1をコンタクト7を介して設け
る。FIGS. 1 and 2 are a longitudinal sectional view and a plan view, respectively, of an embodiment of the present invention. A pwell 15 is formed on an N-type substrate 6, and a fuse element or a polysilicon resistor 2 is formed thereon with a silicon oxide film 4 interposed therebetween. Furthermore, an At electrode 1 is provided via a contact 7 through the silicon oxide film 3.
今、ヒユーズ素子2としてポリシリコン抵抗を用いた場
合を考える。ポリシリコン抵抗2に過電流を流し込む事
により溶断させ、この間でQ pen状態を作)出す。Now, consider a case where a polysilicon resistor is used as the fuse element 2. By flowing an overcurrent into the polysilicon resistor 2, it is fused and a Q pen state is created during this time.
このヒーーズ素子の一端子と半導体基板間に短パルス(
0,01μsec以下)のESDパルスが印加されると
、シリコン酸化膜4を絶縁破壊して拡散層5とポリシリ
抵抗2がショートする。しかし、半導体基板6と拡散層
5は接合で絶縁されているため、機能的には全く問題が
ない。この効果を得るためには、第2図に於いて、ヒユ
ーズ素子2より拡散層5は広く形成する必要がある。A short pulse (
When an ESD pulse (less than 0.01 μsec) is applied, the silicon oxide film 4 is dielectrically broken down and the diffusion layer 5 and the polysilicon resistor 2 are short-circuited. However, since the semiconductor substrate 6 and the diffusion layer 5 are insulated by the junction, there is no functional problem at all. In order to obtain this effect, it is necessary to form the diffusion layer 5 wider than the fuse element 2 in FIG.
以上説明したように、本発明はヒユーズ素子直下に拡散
層を設けることによシ、層間絶縁膜破壊に対するフェイ
ルセーフ機構を得られる効果がある。As explained above, the present invention has the effect of providing a fail-safe mechanism against interlayer insulating film breakdown by providing a diffusion layer directly below the fuse element.
第1図は本発明のヒーーズ素子・ESD保護素子の縦断
面図、第2図はその平面図である。また第3図は従来素
子の縦断面図である。
1・・・・・・M電極、 2・・・・・・ポリシリコン
又は金属配線、3・・・・・・層間絶縁膜、4・・・・
・・層間絶縁膜、5・・・・・・拡散層、6・・・・・
・半導体基板、7・・・・・・コンタクトスルーホール
。
第 1 VFI
半 2I!fFIG. 1 is a longitudinal sectional view of the heating element/ESD protection element of the present invention, and FIG. 2 is a plan view thereof. Further, FIG. 3 is a longitudinal cross-sectional view of a conventional element. 1...M electrode, 2...Polysilicon or metal wiring, 3...Interlayer insulating film, 4...
...Interlayer insulating film, 5...Diffusion layer, 6...
- Semiconductor substrate, 7...Contact through hole. 1st VFI half 2I! f
Claims (1)
せる事でスイッチの役割を果たす素子を含む半導体集積
回路に於いて、半導体基板と反対導電型の拡散層上に絶
縁膜を介して、ポリシリコン、金属膜を形成し、かつ前
記拡散層は前記ポリシリコン配線・金属配線、ポリシリ
コン抵抗をおおいかくす大きさを有する事を特徴とする
半導体集積回路。In semiconductor integrated circuits that include elements that play the role of switches by melting polysilicon wiring or metal wiring due to overcurrent, polysilicon or metal wiring is 1. A semiconductor integrated circuit in which a film is formed, and the diffusion layer has a size that covers the polysilicon wiring, the metal wiring, and the polysilicon resistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1411086A JPS62172739A (en) | 1986-01-24 | 1986-01-24 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1411086A JPS62172739A (en) | 1986-01-24 | 1986-01-24 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62172739A true JPS62172739A (en) | 1987-07-29 |
Family
ID=11851976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1411086A Pending JPS62172739A (en) | 1986-01-24 | 1986-01-24 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62172739A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005251183A (en) * | 2004-02-06 | 2005-09-15 | Semiconductor Energy Lab Co Ltd | Semiconductor device, ic card, ic tag, rfid, transponder, paper money, securities, passport, electronic equipment, bag and clothing |
JP2007073928A (en) * | 2005-09-02 | 2007-03-22 | Renei Kagi Kofun Yugenkoshi | Esd (electrostatic discharge) protection device for programmable device |
JP2011009745A (en) * | 2009-06-29 | 2011-01-13 | Internatl Business Mach Corp <Ibm> | Electrically programmable fuse using anisometric contact and fabrication method |
US7946503B2 (en) | 2004-02-06 | 2011-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5863148A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device |
JPS60245251A (en) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-01-24 JP JP1411086A patent/JPS62172739A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5863148A (en) * | 1981-10-09 | 1983-04-14 | Toshiba Corp | Semiconductor device |
JPS60245251A (en) * | 1984-05-21 | 1985-12-05 | Hitachi Ltd | Semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005251183A (en) * | 2004-02-06 | 2005-09-15 | Semiconductor Energy Lab Co Ltd | Semiconductor device, ic card, ic tag, rfid, transponder, paper money, securities, passport, electronic equipment, bag and clothing |
US7946503B2 (en) | 2004-02-06 | 2011-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8430326B2 (en) | 2004-02-06 | 2013-04-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2007073928A (en) * | 2005-09-02 | 2007-03-22 | Renei Kagi Kofun Yugenkoshi | Esd (electrostatic discharge) protection device for programmable device |
JP2011009745A (en) * | 2009-06-29 | 2011-01-13 | Internatl Business Mach Corp <Ibm> | Electrically programmable fuse using anisometric contact and fabrication method |
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