JPH0536913A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a function as a switch element which gate electrode layer formed on a gate insulating film and having at least two input electrodes. CONSTITUTION:In a gate electrode layer of a MOSFET to be used as a switching element of a semiconductor device, for example, a gate polycrystalline silicon film 103 in which high concentration P-type impurity is implanted, and a gate polycrystalline silicon film 106 in which low concentration N-type impurity is implanted, is formed. Here, gate electrode layers made of the films 103, 106 are disposed on an element region through a gate insulating film 107. Accordingly, a potential state to be input to an input terminal of the layer 103 is altered to control charge to be formed the film 107. Thus, two potentials can be input with respect to one MOSFET.

Description

Detailed Description of the Invention

[Object of the Invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MO of a semiconductor integrated circuit.
The present invention relates to the structure of an S field effect transistor.

[0002]

2. Description of the Related Art The prior art is a MOS field effect transistor (hereinafter referred to as MOSFET) in a semiconductor integrated circuit.
A binary logic digital circuit is used as a switching element. The MOS field effect transistor has two states of ON and OFF depending on the potential applied to the gate electrode.
A logic circuit is configured by a combination of two OFF states.

However, in the conventional technique, one MO is used.
Since there is only one switching element function for the SFET, the number of MOSFETs increases in proportion to the number of inputs of the logic gate. For example, a plan view in FIG. 6 and a circuit diagram in FIG. 7 show the E / DNMO having the smallest number of elements.
Taking the NAND gate by S as an example, a 2-input NAND
The gate is composed of three MOSFETs. This layout has an N-type impurity diffusion region 201 as shown in FIG.
A polycrystalline silicon film 202 is disposed on the polycrystalline silicon film 202, and the polycrystalline silicon film 202 serves as the gate electrodes 203 and 204 of the MOSFET and is connected to the metal wirings 205 and 206, respectively. The power supply line 207 is connected to the impurity diffusion region of the load MOSFET 208. Ground line 209 is N-type MOSFET 210, 211
Connected to the impurity diffusion region. In this NMOS logic circuit, (the number of inputs + 1) MOSFETs are required, and if this number can be reduced, it will have a remarkable effect on the high integration of the semiconductor device, which has been a problem in the past.

[0004]

Conventionally, M of a semiconductor device has been used.
In a binary logic digital circuit using an OS field effect transistor as a switching element, one MOSFET is used.
Since it is used as one switching element,
The number of MOSFETs increases in proportion to the number of logic gate inputs. In the conventional technology using one switching element with respect to this one MOSFET, there is a limit to the high integration of the semiconductor integrated circuit, and there is a plurality of inputs for one MOSFET rather than one input for one MOSFET. If it becomes possible, it will significantly contribute to the high integration of the semiconductor integrated circuit. [Constitution of Invention]

[0005]

In order to solve the problems of the prior art, in a gate electrode layer of a MOSFET used as a switching element of a semiconductor device, for example, an input terminal formed on an element isolation film is used. The peripheral region has the same conductivity type as the semiconductor substrate, and the impurity concentration is set higher than the impurity concentration of the semiconductor substrate. Further, the region formed on the gate insulating film has a PNP type structure which has a conductivity type opposite to that of the semiconductor conductor substrate and has an impurity concentration lower than that of the semiconductor substrate. By changing the potential state input to the input terminal of the gate electrode layer, the charge formed near the gate insulating film is controlled. According to the present invention, such a gate electrode layer is arranged to form a MOSFET. In this way, 1 MOS
Allows two potential states to be input to the FET, M
The number of OSFETs is reduced, and high integration of semiconductor integrated circuits is possible.

[0006]

In the present invention, for example, when a MOSFET is formed, in the gate electrode layer, the peripheral region of the two input terminals on the element isolation film has the same conductivity type as that of the semiconductor substrate and has the impurity concentration. PNP structure that has a high conductivity region (low wiring resistance value) and a region with a low impurity concentration (high wiring resistance value) on the other gate insulating films and a conductivity type opposite to that of the semiconductor substrate. To form. Further, the impurity concentration of the gate electrode layer formed on the gate insulating film is made lower than that of the semiconductor substrate. Here, both of the input terminals of the gate electrode layer formed on the element isolation film,
Alternatively, if a potential higher than that of the semiconductor substrate is applied to either one of them, a channel region is formed near the gate insulating film in the gate electrode layer formed on the gate insulating film, and the gate region is formed.
The entire electrode layer becomes conductive. As a result, a channel region is also formed near the gate insulating film of the semiconductor substrate, and the source and drain of the semiconductor substrate are also in a conductive state. Here, the reason why the impurity concentration of the gate electrode layer formed on the gate insulating film is made lower than the impurity concentration of the semiconductor substrate is the gate electrode formed on the gate insulating film. This is because the threshold value of layer inversion is lowered to facilitate inversion and the channel region is easily formed. As described above, two potentials can be input to one MOSFET, and the potentials of the input terminals at both ends of the gate electrode layer of the MOSFET can be changed to be used as an ON / OFF switching element. . In a circuit using this MOSFET as a switching element, depending on the potential state of the input terminals at both ends of the gate electrode layer, if the MOSFET is in the ON state, a channel region is formed between the source and drain of the semiconductor substrate and the current flows. When the MOSFET is in the OFF state, a control function can be provided such that a channel region is not formed between the source and the drain of the semiconductor substrate and no current flows. Therefore, by inputting two potential states from the input terminals at both ends of the gate electrode in one MOSFET, the output state can be displayed from the output terminal. In this way, by allowing two potential states to be input to one MOSFET, the number of MOSFETs in the semiconductor integrated circuit can be reduced as compared with the prior art, and high integration can be achieved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A NOR circuit according to the present invention will be described below in detail with reference to FIGS.

The semiconductor integrated circuit will be described with reference to FIG. 1, which is a plan view, and FIG. 2, which is a sectional view taken along the broken line AB in FIG. The semiconductor substrate 101 is doped with either impurity As or P at a concentration of 1 × 10 ¹⁷ / cm ^3.
Introduced to some extent, a P-type semiconductor substrate 101 is formed.
The gate electrode layer formed in a region surrounded by a broken line as shown in FIG. 1 on each device region surrounded by the device isolation film 102 on the semiconductor substrate 101 contains 1 × impurity B.
10 ²⁰ / cm ³ The gate polycrystal silicon film 103, 104, 105 having a high concentration of P-type impurities introduced therein, and the gate electrode layer formed in the other regions are formed with impurities As or P of 5 × 10 ¹⁶ / cm. ³ A gate polycrystalline silicon film 106 into which an N-type impurity having a low concentration is introduced is formed. Here, a gate electrode layer made of gate polycrystalline silicon films 103 and 106 is arranged on the device region with a gate insulating film 107 interposed therebetween.

FIG. 2 is a sectional view taken along the broken line AB in FIG.
As shown in FIG. 3, N-type impurity diffusion regions are formed as the source region 108 and the drain region 109 in a self-aligned manner with the gate electrode layer. Impurities are introduced into the gate polycrystalline silicon film 106 of the gate electrode layer, but the P-type high concentration impurities are introduced into the gate polycrystalline silicon films 103 and 10.
6 is a contact hole with the input electrodes 110 and 111.
And connected via a cable 112 to form an input terminal. Also,
The power supply line 113, the ground line 114, and the output electrode 115 are connected using a metal line as shown in FIG.

FIG. 3 is a sectional view taken along the broken line CD of FIG.
As described above, a gate polycrystal silicon film in which a low concentration of N-type impurities is introduced through the gate insulating film 107 on the semiconductor substrate 101.
106 are arranged. The gate polycrystalline silicon film 106 into which this low concentration N-type impurity is introduced has a concentration of 5 × 10 ¹⁵ / cm ³ with either As or P as an impurity. It has been introduced with a low level of electrical resistance. Further, on the element isolation film 102, the concentration of B is 1 × 10 ²⁰ / cm ³ Gate polycrystal silicon films 104 and 105, in which a high concentration of P-type impurities is introduced, which has been raised to a certain degree to reduce the electric resistance value, are arranged. Thus, the MOSFET having the gate electrode layer having the PNP type structure, and further the MOSFET having the gate electrode layer
Functions as a switching element. The source 108, which is an N-type impurity diffusion layer, and the drain region 109 are arranged as shown in FIG.

The operation of the semiconductor device according to the present invention will be described with reference to FIG. 3, which is a sectional view taken along the broken line CD in FIG. Here, by applying a positive potential to the gate electrode, the semiconductor substrate
When a negative potential is applied to 101 to the gate electrode, the gate insulating film 10 in the gate polycrystalline silicon film 106 of the gate electrode layer is formed.
Since a hole channel is formed in the vicinity of the gate electrode 7 and becomes conductive with the gate polycrystalline silicon films 104 and 105, the entire gate electrode layer is connected through the contact hole 109 to the input electrodes 110 and 1.
11 is electrically connected to. Then, the gate insulating film
When a hole channel region is formed in the vicinity of 107, a channel region due to electrons is also formed in the vicinity of the gate insulating film 107 of the semiconductor substrate 101, and the source substrate 108 is also formed in the semiconductor substrate 101.
The drain 109 is electrically connected, and the MOSFET functions as a switching element. Also MOSFET
When the switching element is electrically turned off, the source 108 and the drain 109 are not electrically connected even in the semiconductor substrate 101. Therefore, depending on the combination of potentials applied to the input electrodes 110 and 111, 2
It can function as an input switching element. Here, FIG. 4 is a circuit diagram of the NOR circuit of the present embodiment.
Indicates. For example, as shown in FIG. 5, if a low potential state is input to the input electrode 110 and the input electrode 111, the potential state of the output electrode becomes a high potential, and either one of the input electrode 110 and the input electrode 111, or both of them. If you input a low potential state to
The potential state of the output electrode 115 is low. Here, the high potential is set to 5V and the low potential is set to 0V. As a result, the NOR circuit is constructed from the potential state of the input electrode applied to the input electrode 110 and the input electrode 111 and the potential state of the output electrode with respect to it. In this way, the combination of the potentials input to the output electrodes and the potentials output from the output electrodes are shown.

As described above, the embodiment of the present invention can function as a switching element for inputting two potential states to one MOSFET in a NOR circuit. From this, a MOSFET capable of inputting two potential states to one MOSFET
It becomes possible to form a wide variety of logic circuits by using the NOR circuit according to, and the area of the circuit can be reduced by reducing the number of MOSFETs.

Further, in the embodiment of the present invention, a large number of MOs are used.
It is very effective when a logic circuit is composed of SFETs. For example, conventionally, a NOR circuit has been configured by connecting in parallel MOSFETs that can input only one potential state. On the other hand, according to the embodiment of the present invention, two MOSFETs connected in parallel are made into one MOSFET in the logic circuit. For example, a logic circuit composed of four MOSFETs will be composed of two MOSFETs. With this method, it is possible to reduce the number of MOSFETs by half and reduce the area of the semiconductor integrated circuit. As described above, in the embodiment of the present invention, the larger the number of inputs of the potential state to the MOSFET, the greater the effect of the present invention. Therefore, the embodiment of the present invention is extremely effective in increasing the degree of integration of a semiconductor integrated circuit.

[0014]

According to the present invention, by making a MOSFET function as a switch element capable of inputting two potential states to one MOSFET, it is possible to achieve high integration of a semiconductor device.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device shown along the broken line AB in FIG.

FIG. 3 is a sectional view of the semiconductor device shown along the broken line CD in FIG.

FIG. 4 is a circuit diagram of a semiconductor device showing an embodiment of the present invention.

FIG. 5 is a diagram showing an output potential with respect to an input potential of a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a plan view showing a semiconductor device according to a conventional technique.

FIG. 7 is a circuit diagram showing a semiconductor device in the related art.

[Explanation of symbols]

101 ・ ・ ・ Semiconductor substrate, 102 ・ ・ ・ Device isolation film, 103,104,105 ・ ・ ・ Gate polycrystal silicon film with high concentration P-type impurity introduced, 106 ・ ・ ・ Gate polycrystal with low concentration N type impurity introduced Silicon film, 107 ・ ・ ・ Gate insulating film, 108 ・ ・ ・ Source region, 109 ・ ・ ・ Drain region, 110,111 ・ ・ ・ Input electrode, 112 ・ ・ ・ Contact hole, 113 ・ ・ ・ Power line, 114 ・ ・ ・ Grounding Wire, 115 ...... Output electrode, 201 ・ ・ ・ N type impurity diffusion layer, 202 ・ ・ ・ Polycrystalline silicon film, 203,204 ・ ・ ・ Gate electrode, 205,206 ・ ・ ・ Metal wiring, 207 ・ ・ ・ Power supply line, 208 ・ ・ ・ Load MOSFET, 209 ... Ground wire, 210, 211 ... N-type MOSFET, 212 ... Contact hole.

Claims (7)

[Claims] 1. A first conductivity type semiconductor substrate, a second conductivity type source / drain region formed in the first conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate. And a gate insulating film formed on the gate insulating film, and a gate electrode layer having at least two input electrodes formed on the gate insulating film. 2. The gate electrode layer comprises a first region of the first conductivity type and a second region of the second conductivity type, and an impurity concentration of the second region of the second conductivity type is 2. The semiconductor device according to claim 1, wherein the impurity concentration is lower than that of the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein the gate electrode layer has at least one PN junction. 4. The semiconductor device according to claim 1, wherein the gate electrode layer has a PNP junction. 5. The second conductive type second region, wherein the gate electrode layer is disposed on the channel region of the first conductive type semiconductor substrate with the gate insulating film interposed therebetween. Formed in contact with the end of the second region of the second conductivity type,
The semiconductor device according to claim 1, further comprising: the first region to which the input electrode is connected. 6. The integrated circuit including the semiconductor device is NO
The semiconductor device according to claim 1, further comprising an R circuit. 7. A MOS field effect transistor, wherein one gate electrode layer has two input electrodes.