JPH02226808A - Power mosfet with overcurrent protecting function - Google Patents

Abstract

PURPOSE:To securely display the overcurrent protecting function which is not affected by temperature variation by supplying a current which flows through a current mirror MOS transistor(TR) directly to the base of a bipolar TR and controlling the gate voltage of a main MOS TR with the current. CONSTITUTION:The current i0 which flows through the current mirror MOS TR M2 is supplied directly to a switching means 102 for gate voltage limitation composed of bipolar TRs TR0, TR1-TRn, etc. Then, this switching means 102 for gate voltage limitation is driven with the current to control the gate voltage of the main MOS TR M1. Consequently, the power MOSFET 101 can securely be protected from an overcurrent without being affected by variation in ambient temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention is directed to a power MOSFET with an overcurrent protection function.
(MOS type field effect transistor).

B. Prior art As a power MOSFET with an overcurrent protection function, for example, as shown in FIG. 12, there is one shown in Japanese Patent Application No. 62-223018 proposed by the present applicant.

In FIG. 12, 100 is a power MOSFET with an overcurrent protection function, and RL is a load.

The power MOSFET with overcurrent protection function is the main MOSFET Ml (hereinafter referred to as M
OS transistor Ml) and a current mirror MOSFE connected in parallel to this main MOS transistor M1.
TM2 (hereinafter referred to as MOS transistor M2),
The current mirror MoS transistor M2 is made up of a single power MOSFET cell or several power MOSFET cells connected in parallel, and the main MOS transistor M1 is each made up of several tens of the same power MOSFET cells connected in parallel.

In addition, in FIG. 12, RB is a current detection resistor, Ri
is an input resistance, and T1 is a bipolar transistor that limits the gate voltage VGt of the main MOS transistor M1. The current detection resistor Rs is connected in series to the source of the current mirror MoS transistor M2, and the input resistor Ri is connected in series between the common gate input terminal G of the MOS transistors M1 and M2 and the gate of the main MOS transistor M1. . The collector of the bipolar transistor T1 is connected via an input resistor Ri to the gate of a current mirror MOS transistor M2, which is connected to the gate input terminal G, and its emitter is connected to the source of the main MOS transistor M1, and its base is connected to the source of current mirror MOS transistor M2.

Next, the operation of the conventional power MOSFET with overcurrent protection function configured as described above will be explained.

In a state where the power supply voltage VB is applied to the main MOS transistor M1 through the load RL, for example, the load R
If an abnormality occurs such as a short circuit between the main MoS
Voltage V applied between the drain and source of transistor M1
As DS increases, the current I flowing therein also increases. At this time, if the power MOSFET does not have an overcurrent protection function, its temperature will rise due to the overcurrent and it will be destroyed.

Therefore, in the power MOSFET having the configuration shown in the twelfth example, when an overcurrent flows, the current i flowing to the current detection resistor R8 through the raster M2 on the current mirror MOS also increases. Therefore, the base-emitter voltage V of the bipolar transistor T1
aE=i-R5 increases and finally reaches the base-emitter voltage threshold VBEON (=0.6V).

Then, the base current i flows through the bipolar transistor T1.
B flows, transistor T1 conducts, and collector current i
(H flows. Then, as the base current iB increases, the collector current ic also increases, and the gate voltage vG of the main MOS transistor M1 decreases. This is expressed by the following equation.

Rs(i-in)=VaEoq=0.6V...
...(1)i(H=hpB-iB
−”・(2)Vq,=Vc,−Ri−ic
−・” (3) If ic and iB are removed from the above equations (1), (2), and (3), the following is obtained. However, hPB is the bipolar transistor T1
is the common emitter current amplification factor. Further, the conditions for formula (4) to hold can be expressed as formula (5) below.

R5-1>VBEON-・” (
5) The following can be seen from the above equations (4) and (5).

As current i increases so that R8-1 exceeds VBEON, bipolar transistor T1 turns on.

When the current i further increases, Ic and IB increase,
As a result, when the gate voltage VGL becomes smaller than the threshold voltage VTH of the main MOS transistor M1, the main MOS
Transistor M1 turns off.

Therefore, the current I decreases, and the power MO8 and FET can be protected from overcurrent.

By the way, the current detection resistor R8 is a power MOSFET.
There are two types of resistors: a diffused resistor, which is formed by diffusing impurities into a predetermined region on the same silicon substrate, and a polysilicon resistor, which is formed in a polysilicon film deposited on an insulating film on the silicon substrate.

Figure 13 shows a temperature characteristic diagram of polysilicon resistance.
hycics.

Vol, 46. No, 12. Dec, 1975. T
he tactical properties o
f polycrystalline 5ilicon
filn+s''-P, 5249J. The vertical axis uses units in which the ratio of the specific resistance at each temperature to the specific resistance at 160° C. is expressed in logarithm.

FIG. 13 shows that the resistance value of the polysilicon resistor decreases as the temperature increases, that is, there is temperature dependence. This is because the number of thermally emitted electrons that exceed the potential barrier of the crystal grain boundaries of the polysilicon film increases as the temperature rises.

When using such a polysilicon resistor as a current detection resistor, its resistance value decreases as the temperature rises, so
R8 in the above equation (5) becomes smaller.

Accordingly, in order to satisfy the condition of equation (5), the current i must be increased, but even if this current i is used to ensure the turn-on condition of the bipolar transistor T1, the main MOS transistor M1
There is a risk that an overcurrent may flow. Furthermore, the bipolar transistor T1 becomes difficult to turn on, and the overcurrent protection function of the power MOSFET is hardly exhibited.

Moreover, FIG. 14 shows a temperature characteristic diagram of diffused resistance.
“University Lecture of Institute of Electrical Communication Engineers, Coronasha, February 1, 1960
It is disclosed in "Semiconductor Electronics Engineering", P. 31, first published on June 0.

This FIG. 14 shows the following.

When the temperature decreases, it becomes difficult for carriers to be supplied from impurities, so the conductivity decreases. Furthermore, when the temperature rises, most of the impurities are ionized and carriers do not increase, so there is a region where the conductivity is saturated. When the temperature further increases, carriers are generated from the intrinsic semiconductor and the conductivity increases again. However, in the saturated region, the conductivity tends to decrease somewhat as the temperature increases due to the temperature dependence of carrier mobility.

That is, the resistance value of the diffused resistor decreases as the temperature increases over most temperature ranges. However, within a certain temperature range, the resistance value is almost constant or increases somewhat as the temperature rises. This temperature range is determined by impurity density, crystal defect density, etc.

When using such a diffused resistor as a current detection resistor,
By controlling the impurity density and defect density so that the resistance value of the diffused resistor increases with temperature within the temperature range in which the operation of the MOSFET is guaranteed, the overcurrent protection function of the MOSFET can be effectively exhibited. However, the diffusion resistance is
Since the resistance value decreases as the temperature decreases, it is necessary to take this into consideration when designing the device so that the overcurrent protection function is not lost.

C1 Problems to be solved by the invention Conventional power MOSF with overcurrent protection function as described above
In ET, the current i flowing through the current mirror MOS transistor M2 is converted into a voltage by a current detection resistor Rs made of a polysilicon resistor or a diffused resistor, and when the voltage exceeds a predetermined threshold voltage, the bipolar transistor T1 is turned on. Since the gate voltage of the main MoS transistor M1 is lowered and the main MoS transistor M1 is turned off, the resistance value of the current detection resistor decreases due to an increase in ambient temperature.

The condition of equation (5) for turning on the bipolar transistor T1 does not hold, and the overcurrent protection function is lost.

In addition, the above problem can be solved by using a diffused resistor designed so that the resistance value of the current detection resistor does not decrease due to temperature rise, but on the other hand, when forming a diffused resistor on a silicon substrate, impurity density and defects It is necessary to control the density holes with high precision, which limits the degree of freedom in circuit design and makes circuit design difficult. Furthermore, since current always flows through the current detection resistor, there is a problem that power consumption is large and heat is generated.

A technical object of the present invention is to facilitate circuit design without being affected by temperature changes, increase the degree of freedom in design, and ensure overcurrent protection with low power consumption.

The present invention will be explained with reference to FIG. 1 showing an embodiment of the present invention.The power M○5FET with an overcurrent protection function according to the present invention has a gate input signal input to a gate input terminal G. Main MOSFE that switches the load on and off according to the
T Ml and its main MOSFET Ml such that a current flows proportional to the current flowing through the main MOSFET Ml.
1 and a current mirror MOSFET M2 that is turned on and off according to a gate input signal input to a gate input terminal G.

Furthermore, at least the first and second switching elements T r, , T r are turned on depending on the magnitude of the current flowing directly through the current mirror MOSFET M2.
It also has a gate voltage limiting switching means 102 having . The first switching element Tr is connected to the current mirror MOSFET M2 and the second switching element Tr so as to control the second switching element Tr according to the current flowing through the current mirror MOSFET M2 when turned on; Second switching element T
The resistor is connected to the gate of the main MOSFET M1 so as to limit the gate voltage of the main MOSFET M1 according to the current flowing through the current mirror MOSFET M2 when turned on.

Due to the increase in the E6 action load current, the drain-source voltage VBB of the main MOSFET M1 increases, and the voltage between the control terminal 102a and the common terminal 102b of the gate voltage limiting switching means 102 increases as the voltage between the first and second switching elements T r , Tr, the current 10 flows through the current mirror MOSFET M2 and the first and second switching elements Tr, Tr.

The current mirror current 11 is proportional to this current i.
flows through the switching element Tri.

Now, the first and second switching elements Tr.

If the transistors are formed adjacently on the same substrate in the same process, the current amplification factor hpBt of these switching elements is
Since various characteristics such as internal base resistance and threshold voltage are equal to each other, current 10 and current 12 are.

However, n is the number of second switching elements. As a result, if the current amplification factor (hps) is set to 1, the current i can be made to flow in accordance with the current i regardless of the variation in the current amplification factor hFB. As a result, the main MOSFET
The gate voltage VGm of Ml can be controlled as a function of the load current, and when the current 11 increases as the load current increases, the gate voltage VG□ decreases below the threshold and the main MOSF
ETM1 turns off.

Therefore, according to the present invention, the power MOSFET can be reliably protected from overcurrent with high reliability without being affected by ambient temperature or variations in the characteristics of the gate voltage limiting switching means. Further, by eliminating the need for a current detection resistor, the degree of freedom in circuit design is increased and the circuit design is facilitated.

Although the present invention has been described above with reference to figures of embodiments, the present invention is not limited to the embodiments.

F. Example An embodiment of the present invention will be described below based on the drawings.

Figure 1 shows a power MO with overcurrent protection function according to the present invention.
12 is a circuit diagram showing a first embodiment of the SFET, and the same parts as in FIG. 12 are given the same reference numerals and will be described.

In the figure, the reference numeral 101 in the part surrounded by the dashed line indicates a power MOSFET with an overcurrent protection function, which includes a drain terminal D, a source terminal S, and a gate input terminal Gtil. The drain terminal is connected to the power supply voltage V via the load RL.
a, and the source terminal S is grounded.

The power MOSFETIOI with an overcurrent protection function includes a main MOS transistor M1 for load switching whose drain and source are connected between the drain terminal and the source terminal S, a current mirror MoS transistor M2,
The current mirror circuit 102 limits the gate voltage VG of the main MOS transistor M1.

The gate of the main MOS transistor M1 is connected to the input resistor R1.
The gate of the current mirror MoS transistor M2 is connected to the gate input terminal G via a gate resistor R1.

The current mirror circuit 102 includes two or more bipolar transistors Tr formed in the same process and close to each other on the same semiconductor substrate.

~Equipped with a Tr port. These are bipolar transistor Tr and bipolar transistor Tr.

It is divided into two groups: ~Trn. The collectors of the first group of bipolar transistors Tr are connected to the control terminal 102a of the current mirror circuit 102, and the emitters thereof are connected to the common terminal 102b. Also,
The collector and base of bipolar transistor Tro are directly connected.

A second group of bipolar transistors Tr.

The collectors of ~Trn are commonly connected in parallel to the current mirror terminal 102c of the current mirror circuit 102,
Further, each emitter is connected in parallel to the common terminal 102b, and each base is connected to the base of the first group of bipolar transistors Tr. The control terminal 102a of the current mirror circuit 102 connects the common terminal 1 to the source of the current mirror MOS transistor M2.
02b is connected to the source of the main MOS transistor M1, and the current mirror terminal 102c is connected to the gate of the main MoS transistor M1.

Note that the reason why the second group of the current mirror circuit 102 is composed of a plurality of bipolar transistors Tr, -Trn is to flow a sufficient current mirror current i□.

Here, since the bipolar transistors Tr, . The amplification factor hFE, internal base resistance, etc. are equal to each other. Therefore, these bipolar transistors Tr,
, Tr, ~Trn base-emitter threshold voltage V
BBON is also equal.

Next, the operation of the power MOSFET configured as described above will be explained.

(During normal operation of the power MOSFET) When the gate voltage Va input to the gate input terminal G is higher than the threshold voltage VTH and the main MoS transistor M1 is conducting, its on-resistance is small, so the voltage between its drain and source increases. The voltage Vos is small, and the accompanying base-emitter voltage VBE (<VO2) of the bipolar transistors Tr, Tr, ~Trn is smaller than their threshold voltage VBBON (=0.6V), and the base current in does not flow. , hence the bipolar transistor Tr.

Tr, -Trn are turned off. Therefore, the input current i1 and current mirror current i of the current mirror circuit 102 are both 0, and the gate voltage VG is Va"Va
a=Vcz, and the main MOS transistor Ml and current mirror MOS transistor M2 maintain a conductive state.

On the other hand, the gate voltage Va is the main MoS transistor M1
When the threshold voltage of the current mirror MOS transistor M2 becomes smaller than the threshold voltage VT)I, the main MOS transistor M1 and the current mirror MOS transistor M2 are turned off, and at this time as well, the bipolar transistors Tr, ,
TrL"Trn is turned off and the input current is 10.
Both current mirror currents are O.

(When an abnormality occurs such as load RL short-circuiting) Power MOS
For example, if the load RL is short-circuited and the load current IL increases when FETIOI is turned on, the main MOS transistor M1
The drain-source voltage VD8 also increases. Along with this, bipolar transistors T r,, T r, ~T
The r-gate base-emitter voltage VaS increases and eventually becomes larger than the base-emitter voltage threshold V BHON. Then, the bipolar transistor Tr...
A base current in flows through Tr, to Trn, and all of them turn on at the same time, and a noctor current IC also begins to flow. At this time, current i, = (h
ps+n+1)io flows.

At this time, each bipolar transistor Tro.

The base currents is of Tr and ~Trn are equal, and the collector current iC of each transistor is.

1c=hpa-in ・・・・・・・・・・・・
(6) However, hFE is the current amplification factor of each bipolar transistor Tro, Tr1 to Trn.

bawl. On the other hand, the input current 18 is.

1o=ic+(n+1)ia・・・・・・・・・・・・
......(7), and the current mirror current i4 is.

i engineering=n-1c ・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・ Since (8),
ic from the above equations ('6), (7), and (8).

When iB is removed, if hps>>1, then the proportionality constant of i and i has no relation to the current amplification factor hFE.

i□=n-1゜ It turns out that

On the other hand, the point that the current I flowing through the main MOS transistor M1 and the current i flowing through the current mirror MOS transistor M2 are also proportional will be explained.

Main MoS transistor M1 and current mirror Mo
Assuming that each S transistor M2 is composed of n□ and 02 identical power MOSFET cells, the ratio of the current flowing through the main MOS transistor M1 to the current i flowing through the current mirror MOS transistor M2 is n□: It becomes 12. That is, the current i is as follows. That is, bipolar transistors Tr0, Tr
1~When Trn is turned on, the current mirror current i
i is proportional to the input current i. Also, from equation (9), this current mirror circuit 102 is obtained. This allows M
OS transistor M2 will function as a current mirror.

Furthermore, the gate voltage VGx at this time is given by the following equation.

VGx = VQ R1” 1 z (10) As is clear from the above, due to the increase in the load current IL,
When the bipolar transistors Tro, Tr~Tr are turned on and the load current IL increases, the current 10 flowing through the current mirror MOS transistor M2 also increases proportionally.

At this time, due to the voltage drop across the input resistor Ri, the gate voltage of the current mirror MoS transistor M2 is maintained above its threshold value and continues to be turned on. On the other hand, the main MOS transistor M1 is a bipolar transistor Tr, ~Tr
As the collector current IC of n increases, it decreases to below the threshold value. As a result, the main MoS transistor M1 is turned off, protecting the power MOSFETIOI from overcurrent due to a load short circuit or the like.

FIG. 2 shows part of the device structure of the power MOSFET described above, namely, a current mirror MOS transistor M2, a bipolar transistor T I'', , T
FIG. 2 is a schematic structural diagram of a high gate resistance R1 and an input resistance Ri.

The power MOSFETIOI with an overcurrent protection function includes an N-type semiconductor substrate 1 consisting of an N-type high concentration substrate 1a and an N-type low concentration substrate 1b, and a drain terminal is provided on the back surface of the N-type semiconductor substrate 1.

A vertical MOSFET, that is, a current mirror M, is formed on the N-type low concentration substrate 1b of the N-type semiconductor substrate 1 by the double diffusion method.
An OS transistor M2 is formed. This current mirror MOS transistor M2 is connected to an N-type low concentration substrate 1b.
P well regions 2a, 2b formed in the P well regions 2a, 2b, N0 regions 3a, 3b formed in the P well regions 2a, 2b, N
A gate electrode 5 disposed with a gate oxide film 4 interposed between the "" regions 3a and 3b, an interlayer insulating film 6 covering the gate electrode 5, a P well region 2a and an N" region 3a.
Although not shown, the main MOS transistor M1 is also formed on the substrate 1 as such a vertical MOSFET.

Also, bipolar transistors Tr,, TrL.

The gate resistance R1 and the input resistance Ri are connected to an N-type semiconductor substrate l.
It is formed in the polysilicon films 9A, 9B, 9C, and 9D on the insulating 5iOa[8 formed thereon. and,
Each of these elements is connected by a wiring Q as shown in FIG.

FIG. 3 is a plan view showing an example of a device in which a power MOS transistor with overcurrent protection function 101 corresponding to FIG. 1 is formed on a semiconductor substrate, and the same reference numerals as in FIG. 1 represent the same parts. ing.

The device shown in FIG. 3 includes a main MOS transistor M1, a current mirror MoS transistor M2,
Bipolar transistor Tr.

Tr, a gate resistance R1, and an input resistance Ri. Here, the main MoS transistor M1 consists of a P well Mll provided in an N-type semiconductor substrate, an N4 source region M12 provided in the P well Mll, and a P0 region M13 provided in the source region M12. one cell 5Ml-
1 to 5M1-8, with a gate M1 between each adjacent cell.
4 are provided. The current mirror MOS transistor M2 has P
Well M21, N3 source region M22, P0 region M23
and a gate M24. Each of these elements is connected to the @ path shown in FIG. 1 with the arrangement aΩ.

4 and 5 are a plan view of the bipolar transistors T ra and T r shown in FIG. 3, and a sectional view taken along the line V-V in FIG. 4.

In FIGS. 4 and 5, a polycrystalline silicon layer 102 as a semiconductor thin film is deposited on an insulating substrate 501 to a required thickness and patterned into a predetermined shape. A mask material 110 is formed on a predetermined region of this polycrystalline silicon N102. Polycrystalline silicon directly below this mask material 110! 102, a lightly doped N-type collector region 105a and a P-type base region 104a are formed in contact with each other.

In the polycrystalline silicon layer 102 immediately below the mask material 110, an N0 type collector extraction region F4.105b is formed in contact with the N type collector region 105a, and an N0 type emitter region 103 is formed in contact with the P type base region 104a. is formed.

The P-type base region 104a sandwiched between the N0-type emitter region 103 and the N-type collector region 105a has an extremely narrow base width W (several thousand people). Note that this base @W is formed by using the mask material 110 as a mask to form the P-type impurity forming the P-type base region 104a and the N-type collector region 1.
05a is double diffused into the polycrystalline silicon JLW 102, and is defined by the difference in the lateral diffusion lengths of the two types of impurities.

Furthermore, the polycrystalline silicon layer 1 other than directly under the mask material 110 is
02, a P0 type base drawing area 104b is formed in contact with the P type base area 104a. And this P
9-type base extraction region 104b and N-type emitter region 1
03 is separated by an interlayer insulating film 107 in a region other than directly under the mask material 110. Immediately below the mask material 110, the P-type base extraction region 104b and the N1-type emitter region 103 are connected to the P-type base region 104a so as to overlap in the base width direction. That is, the P-type base lead-out region 104b and the N0-type emitter region 103 are connected only within the base region 104a.

In addition, the N2 type emitter area 103, the P2 type base drawer area 104b, and the N8 type I-knocker drawing area 10.
5b are emitter electrodes 106E through contact holes formed in the interlayer insulating film 107 deposited on the polycrystalline silicon layer 102.

It is connected to the base electrode 106B and the nocturnal electrode 106C.

Bipolar transistor T r configured in this way,
, T r□ is the P-shaped base extraction region 1 connected to the base electrode 106B except directly under the mask material 110.
04b and the N0 type emitter region 103 are separated from each other, and directly under the mask material 110, the N0 type emitter region 103
and P9 type base lead-out region 104b are in contact with each other via the P type base region 104a with a contact length shorter than that of the base 1llW, so no parasitic diode is formed between the emitter and base due to the PN junction. Therefore, all the base current iB Now contributes to transistor operation,
It is possible to prevent the current amplification factor hpE from decreasing due to the formation of a parasitic diode. In addition, since no parasitic diode is formed between the emitter and base, there is no parasitic capacitance between the emitter and base due to the junction capacitance of this parasitic diode, and as a result, the operating speed of the transistor can be increased and the cutoff frequency fT can be increased. You can also do it.

The power MOS with overcurrent protection function of this example
In the FET, the current 10 flowing through the current mirror MOS transistor M2 is directly connected to the bipolar transistors Tr, Tr, without using a current detection resistor.
This current flows through the base of Trn, and the current is configured to control the gate voltage of the main MOS transistor M1, so that the overcurrent protection function can be reliably exerted without being affected by temperature changes. Furthermore, since there is no current detection resistor, there is no need to design a circuit that takes its temperature characteristics into consideration, which increases the degree of freedom in design and facilitates circuit design.

Furthermore, since the gate resistor R1 is interposed between the gate of the current mirror MOS transistor M2 and the gate input terminal G, the gate input signal of the current mirror MOS transistor M2 is delayed and turns on before the main MOS transistor M1. The main MOS transistor M1 can be turned on without fail.

Furthermore, since the current detection resistor can be omitted, the circuit configuration is simplified, the circuit can be made smaller, and a smaller area and higher integration are possible. Furthermore, when a current detection resistor is used, a current always flows, but by using the configuration of this embodiment, the base-emitter voltage VBE of the voltage 1ia becomes larger than the threshold voltage VBBON. Since only time flows, power consumption can be reduced.

FIG. 6 is a modification of FIG. 3, in which the polysilicon film 9C
, 9D, and the Tr fabrication are fabricated in the bulk of the substrate. That is, a P well region 10 is formed in an N type low concentration semiconductor substrate lb, and N regions 11a, llb, P regions 12a,
12b, N'' regions 13a and 13b are sequentially formed to form bipolar transistors Tr and Trl. Note that the input resistor Ri and gate resistor R1 are provided in a semiconductor substrate region not shown.

FIG. 7 is a circuit diagram showing another embodiment of the current mirror circuit 102 according to the present invention, in which the same parts as in FIG. 1 are given the same reference numerals, and different parts are emphasized.

That is, in this embodiment, as is clear from the figure, the first and second groups of bipolar transistors Tr,
and each bipolar for fixed bias of Tr, ~Trn.
The collector and emitter of the same bipolar transistor 20 are connected between the base of the transistor and the control terminal 102a, respectively.

Similarly to the current mirror circuit shown in FIG. 1, the current mirror circuit shown in this embodiment does not operate until the base-emitter voltage Vee becomes larger than its threshold voltage VBEON. The input current 10 and current mirror current i□ at this time are i,=i□=0. Also, v8ε is V
When it becomes larger than BEON, the current mirror current 12
flows in proportion to the input current 10. This lowers the gate voltage VGz of the main MOS transistor M1, turns off the main MOS transistor M1, and turns off the power MO.
SFET can be protected from overcurrent. Further, the threshold voltage V B111' between the base and emitter of the bipolar transistor 20 is set to the bipolar transistor Tr.
If the threshold voltage VBE of the bipolar transistors Tr, ~Trn is set higher than the threshold voltage VBE of the bipolar transistors Tr, ~Trn,
Even if there are variations in the threshold voltages of rn, there is an effect that they can all be turned on at the same time.

FIG. 8 is a circuit showing still another embodiment of the current mirror circuit 102 according to the present invention, and the same parts as in FIG. 1 are given the same reference numerals, and different parts will be mainly described.

That is, in this embodiment, the collectors of the bipolar transistors Tr to Trn of the second group are connected to the current mirror terminal 102c via the same bipolar transistor 21, and the bipolar transistor 2
1 is connected to the control terminal 102a. Then, each bipolar transistor Tr of the second group
n collector and each bipolar transistor Tr, ,
The bases of Tr and -Trn are directly connected.

Similarly to the current mirror circuit of FIG. 1, the current mirror circuit 102 configured in this manner does not operate when the base-emitter voltage VBB is less than its threshold voltage VBEON. Input current i at this time. and current mirror current 11 is zero.

Also, when the base-emitter voltage VBE becomes larger than VBEON, the current mirror current i becomes the input current i,
flows in proportion to. The ratio of surface currents at this time is expressed by the following formula.

i, hps”+ (n+1)hps+ (n
+1)... (11) In the embodiment shown in Fig. 8 as well as in Fig. 7 above, (1
As can be seen from equation 1), as described above, if the current amplification factor bps of the bipolar transistor is large, its proportionality constant no longer depends on hFE and is not affected by variations in hFE. Also in the embodiment of FIG. 8, the base-emitter voltage VBε of the bipolar transistor 21 is set to
By setting the threshold voltage Vss to be higher than the threshold voltage Vss of n, all bipolar transistors Tr, to Trn can be turned on at the same time.

Figure 9 shows a power MO with overcurrent protection function according to the present invention.
2 is a circuit diagram showing a second embodiment of SFETIOI, in which the same parts as in FIG. 1 are given the same reference numerals, and different parts will be described with emphasis.

That is, as is clear from FIG. 9, the gate of the main MOS transistor M1 is directly connected to the gate of the current mirror MOS transistor M2, and the gates of both MOS transistors M1 and M2 are connected to the gate terminal G via the input resistor Ri. It is connected to.

The operation of this embodiment against overcurrent is the same as that of the first embodiment, but since the gate of the main MOS transistor M1 and the gate of the current mirror MOS transistor M2 are directly connected, the overcurrent causes the current mirror circuit to 102 operates and the gate voltage VGz of the main MOS transistor M1 decreases and turns off, the gate voltage VGi of the current mirror MOS transistor M2 also decreases, and the current mirror MOS transistor M2 also turns off, causing the overcurrent protection circuit to become inoperable. Therefore, the gate voltage VaiV(aa rises again and the main M
When the OS transistor M1 and the current mirror MoS transistor M2 are turned on, current flows again and the overcurrent protection circuit starts operating again. Therefore, the embodiment shown in FIG. 9 has the effect of limiting the current to a constant value against overcurrent.

Figure 10 shows the power M with overcurrent protection function according to the present invention.
It is a circuit diagram showing a third example of OSFET 102,
The same parts as in the first figure are given the same reference numerals, and their explanations are omitted, and the parts different from the first figure will be mainly described.

This embodiment differs from FIG. 1 in that the gate of the main MOS transistor M1 and the gate of the current mirror MoS transistor M2 are directly connected, and both MoS transistors M
1 and M2 are connected to the gate input terminal G via a nonlinear element 25 having nonlinear characteristics such as current saturation characteristics.

The nonlinear element 25 is a junction type FET, a normally-on type MO
It consists of SFET, TPT (thin film transistor), etc., and its current 11-voltage V3 (VG-VG□) is determined as shown in FIG.

In such a power MOSFET, the current mirror current i when the current mirror circuit 102 operates,
is designed to be larger than the saturation value of one current passing through the nonlinear element 25. In this way, the current i when the current mirror circuit 102 operates is limited by the nonlinear element 25, and as a result, the gate voltage VG□ decreases rapidly, and the power MOSFET is reliably protected from overcurrent. Can be done.

Note that in the current mirror circuits shown in FIGS. 1 and 7 to 10 above, the case where the second group of bipolar transistors is composed of n bipolar transistors indicated by symbols Tr□ to Trn has been described. However, if a current mirror circuit is constructed using polysilicon bipolar transistors, one bipolar transistor may not be able to flow a sufficient amount of current. In this case, it is desirable to use a plurality of bipolar transistors as in the embodiment.

Note that although the N-channel low-side switch has been described above, the present invention can be similarly applied to an N-channel high-side switch. Furthermore, the present invention can be similarly applied to P-channel low-side and high-side switches by inverting all polarities and 'mi.

Detailed Description of the G0 Invention According to the present invention, the current mirror M.O.
The current flowing through the SFET is made to flow directly to the gate voltage limiting switching means constituted by a bipolar transistor or the like, and the gate voltage of the main MOSFET is controlled by removing the current from the gate voltage limiting switching means. , it is possible to reliably protect the power MOSFET from overcurrent without being affected by changes in ambient temperature, and by eliminating the need for a current detection resistor, the degree of freedom in circuit design is increased. This has the effect of making circuit design easier and reducing power consumption. Furthermore, since the gate voltage limiting switching means has the first and second switching elements, the gate voltage of the main MOSFET can be controlled as a function of the load current without being affected by variations in these switching elements. Highly reliable M
OSFET can be provided.

[Brief explanation of the drawings] Figure 1 shows a power MOS with overcurrent protection function according to the present invention.
A circuit diagram showing the first embodiment of the FET, FIG. 2 is a configuration diagram showing a part of the device structure of a power MOSFET corresponding to FIG. 1, and FIG. 3 is a circuit diagram showing a part of the device structure of a power MOSFET corresponding to FIG. 1.
FIG. 4 is an enlarged plan view of a bipolar transistor used in the power MOSFET shown in FIG. 3, FIG. S is a cross-sectional view along V-V in FIG. 4, and FIG. is a block diagram of a power MOSFET device showing a modification of FIG. 2, FIG. 7 is a circuit diagram showing another embodiment of the current mirror circuit according to the present invention, and FIG. 8 is a circuit diagram showing another embodiment of the current mirror circuit according to the present invention. 9 is a circuit diagram showing a second embodiment of the power MOSFET with overcurrent protection function according to the present invention, and FIG. 10 is a circuit diagram showing the power MOSFET with overcurrent protection function according to the present invention.
FIG. 11 is a current-voltage characteristic diagram of the nonlinear element in the third embodiment, FIG. 12 is a circuit diagram of a conventional power MOSFET with overcurrent protection function,
FIG. 13 is a temperature characteristic diagram of a polysilicon resistor, and FIG. 14 is a temperature characteristic diagram of a diffused resistor. 101: Power MOSFET102 with overcurrent protection function
: Current mirror circuit 102a : Control terminal 102b : Common terminal 10
2c: Current mirror one terminal Ml: Main MOSFET M2: Current mirror MOSFET Trat Tr1 to Trn: Bipolar transistor R1: Input resistance R1: Gate resistance RL: Load resistance 25: Nonlinear element patent applicant Nissan Motor Co., Ltd. Attorney Fuyuki Nagai Ml: Main MOsFET M2: Current mirror MOSFET Fig. 3 SM+-8 5M1'''7 MI-6 Fig. 10 06C Fig. 5 Fig. 7 Fig. 8 Fig. 25: Nonlinear element Fig. 12 B Fig. 11 Figure voltage Vz = va -VGI Figure 13 Figure 14

Claims (1)

[Claims] Main MOSFE that switches the load by turning on and off according to the gate input signal input to the gate input terminal.
T, a current mirror MOSFET connected to the main MOSFET so that a current proportional to the current flowing through the main MOSFET flows, and which is turned on and off in accordance with a gate input signal input to the gate input terminal; It has at least a first switching element and a second switching element which are turned on depending on the magnitude of the current flowing directly through the current mirror MOSFET, and the first switching element is turned on depending on the current flowing through the current mirror MOSFET when the first switching element is turned on. is connected to the current mirror MOSFET and the second switching element so as to control the switching element of the main MOSFET, and the second switching element limits the gate voltage of the main MOSFET according to the current flowing through the current mirror MOSFET when turned on. A power MOSFET with an overcurrent protection function, characterized in that it comprises a gate voltage limiting switching means connected to the gate of the main MOSFET.