JP2002289702A - Method for manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an alignment margin between a plug of a lower layer and a plug of an upper layer without relaxing a layout rule in a semiconductor integrated circuit device having a stacked via structure. SOLUTION: After having formed a metal film 19 on a silicon oxide film 12, a plug 16 and a SiN film 18, by anisotropically etching the metal film 19 by using a photo resist film, the metal film 19 is left on the side wall of the protruded portion from the silicon oxide film 12 of the plug 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device.
The present invention relates to a method of manufacturing a semiconductor integrated circuit device having a stacked via structure, and a technique effective when applied to the semiconductor integrated circuit device.

[0002]

2. Description of the Related Art SRAM (Static Random Access Memor)
y) is a RAM that does not require a refresh operation when power is applied and that can be written and read as needed. In addition, since the SRAM can reduce the power consumption during standby, the SRAM is used as a cache memory for a system such as a portable device in which the number of components is limited, a personal computer, a workstation, and the like.

An SRAM has a flip-flop circuit for storing 1-bit information and two MISFETs for information transfer.
(Metal Insulator Semiconductor Field Effect Trans
istor) and the flip-flop circuit is
For example, a pair of drive MISFETs and a pair of load MIs
It consists of an SFET.

In such a memory cell, a soft error due to α rays has become a problem. This is a phenomenon in which α-rays contained in external cosmic rays and α-rays emitted from radioactive atoms contained in LSI package materials enter the memory cell and destroy information stored in the memory cell. is there. As a countermeasure against the α-ray, a method of increasing the capacity of the information storage unit by adding a capacity to the information storage unit (input / output unit of the flip-flop circuit) in the memory cell is being studied.

For example, in Japanese Patent Application Laid-Open No. 10-163440, a capacitor is constituted by two wirings cross-connecting input / output terminals of a flip-flop circuit for storing information and a thin insulating film interposed therebetween. Accordingly, a technique is disclosed in which the capacity of the storage node of the memory cell is increased to prevent a decrease in α-ray soft error resistance.

[0006]

SUMMARY OF THE INVENTION The present inventors have found that the above S
In order to prevent a soft error in a memory cell of a RAM, a method of providing a capacitance between a power supply voltage in the memory cell and a three-phase node was studied. The manufacturing process is as follows.

A first connection hole and a wiring groove reaching the source / drain of the MISFET are formed in a first interlayer insulating film deposited on a semiconductor substrate. Subsequently, a first plug is formed in the first connection hole, and a wiring is formed in the wiring groove. Then, the first interlayer insulating film is etched back, and the first plug and the wiring are projected. Let it. Next, a capacitor insulating film and a capacitor electrode serving as a capacitor are formed over the first interlayer insulating film and the wiring. Then, the second on the semiconductor substrate
Is deposited, and a second connection hole reaching the first plug is formed in the second interlayer insulating film. Next, a second plug for electrically connecting the first plug and the first layer wiring is formed in the second connection hole, and the first plug and the second plug are used to form a second plug. A so-called stacked via structure is formed.

However, the present inventors have found that the method for forming the stacked via structure has the following problems.

That is, the diameter of the bottom of the second connection hole is adjusted to the first diameter.
When the opening position of the second connection hole is deviated from a predetermined position, the contact area between the first plug and the second plug is reduced, and the first connection hole is substantially equal to the diameter of the upper portion of the first connection hole. There is a problem that the contact resistance between the first plug and the second plug increases.

In the etching step for forming the second connection hole, over-etching is performed for a predetermined etching amount in consideration of a variation in the etching amount in the semiconductor wafer surface. However, when the opening position of the second connection hole deviates from a predetermined position, the lower first interlayer insulating film and the like are etched by the over-etching. If the second plug is formed in this state, there is a problem that the second plug and another conductive layer (for example, the gate electrode of the MISFET) are short-circuited and an electrical failure occurs.

An object of the present invention is to provide a technique for improving a matching margin between a lower plug and an upper plug without relaxing a layout rule in a semiconductor integrated circuit device having a stacked via structure.

It is another object of the present invention to provide a technique for preventing an increase in contact resistance between a lower plug and an upper plug in a semiconductor integrated circuit device having a stacked via structure.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a step of forming a first insulating film on a main surface of a semiconductor substrate, and a step of forming a first insulating film on the first insulating film.
Forming a connection hole; forming a first plug in the first connection hole;
Projecting on the insulating film, and after depositing the first thin film on the first insulating film and the first plug, the first thin film is anisotropically etched to project on the first insulating film. The first plug is provided on at least a side wall of the projected portion of the first plug.
Leaving a thin film; forming a second insulating film on the first insulating film, the first plug and the remaining first thin film; and a second connection reaching the first plug on the second insulating film. Forming a hole.

Further, the present invention provides (a) a first insulating film formed on a main surface of a semiconductor substrate, and (b) a first insulating film formed in a first connection hole formed in the first insulating film, A first plug having a protrusion protruding from the surface of the first insulating film; (c)
(E) a first thin film formed on at least a side wall of the protrusion of the first plug; (d) a second insulating film formed on the first insulating film, the first plug and the first thin film; )
A second connection hole formed in the second insulating film;
A second plug connected to the first plug.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

In this embodiment, for example, the present invention is applied to an SRAM. The method of manufacturing the SRAM according to the present embodiment will be described with reference to FIGS. In the present embodiment, hatching is used even in a plan view so as to make the configuration of the SRAM of the present embodiment easy to understand.

FIG. 1 is a plan view of an essential part during a manufacturing process of the SRAM of the present embodiment, and FIG. 2 corresponds to a cross section taken along line AA of FIG.

First, as shown in FIGS. 1 and 2, element isolation is formed on the element formation surface (main surface) of the semiconductor substrate 1.
Subsequently, a p-type impurity (for example, B (boron)) and an n-type impurity (for example, P (phosphorus)) are ion-implanted into the semiconductor substrate 1, and the semiconductor substrate 1 is subjected to a heat treatment at about 1000 ° C. The p-type well 2 and the n-type well are formed by diffusing the type impurity and the n-type impurity. As shown in FIG. 1, active regions Ap and An, which are the main surfaces of a p-type well 2 and an n-type well, are formed in a semiconductor substrate 1, and these active regions are, for example, embedded with a silicon oxide film. It is surrounded by element isolation.

Next, after the main surfaces of the semiconductor substrate 1 (p-type well 2 and n-type well) are wet-oxidized using a hydrofluoric acid-based cleaning solution, the p-type well 3 is thermally oxidized at about 800 ° C.
Then, a clean gate oxide film 3 having a thickness of about 6 nm is formed on each surface of the n-type well.

Next, a low-resistance polycrystalline silicon film having a thickness of about 100 nm is deposited on the gate oxide film 3 by, for example, a CVD method. Subsequently, the polysilicon film is dry-etched using the photoresist film as a mask to form a gate electrode 4.

Subsequently, in the region where the p-type well 2 is formed,
Here, the n-type impurities are formed in the p-type wells 2 on both sides of the gate electrode 4.
By ion-implanting a substance (for example, P), n^-Mold half
The conductor region 5 is formed. Also, an n-type well was formed.
In the region, the n-type well on both sides of the gate electrode 4 is p-type
Impurity (for example, B) is ion-implanted to ^-
A type semiconductor region is formed.

Subsequently, after depositing a SiN (silicon nitride) film having a thickness of about 40 nm on the semiconductor substrate 1 by, for example, the CVD method, the SiN film is anisotropically etched to form the gate electrode 4. A side wall spacer 6 is formed on the side wall.

Subsequently, an n ⁺ -type semiconductor region 7 (source, drain) is formed by ion-implanting an n-type impurity (for example, P or As (arsenic)) into the p-type well 2.
A p ⁺ -type semiconductor region (source, drain) is formed by ion-implanting a p-type impurity (for example, B) into the n-type well. Through the steps so far, the MISFETs (driving MISFETs Qd,
Transfer MISFET Qt, Load MISFET QLd)
Is completed. Driving MISFET Qd and transfer MI
The SFET Qt is composed of an n-channel MISFET,
The load MISFET QLd is a p-channel type MISFE
Consists of T. The gate electrode 4 of the driving MISFET Qd and the gate electrode 4 of the load MISFET QLd are common.

Next, after cleaning the surface of the semiconductor substrate 1,
For example, by sputtering, C
An o (cobalt) film and a Ti (titanium) film are sequentially deposited. Then, a CoSi ₂ layer 9 is formed on the n ⁺ -type semiconductor region 7, the p ⁺ -type semiconductor region and the gate electrode 4 by subjecting the semiconductor substrate 1 to a heat treatment at about 600 ° C.

Subsequently, after the unreacted Co film and Ti film are removed by etching, the resistance of the CoSi ₂ layer 9 is reduced by a heat treatment at about 700 ° C. to 800 °.

Next, an SiN (silicon nitride) film 10 (first insulating film) having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by the CVD method. The SiN film 10 functions as an etching stopper when forming a contact hole described later.

Next, a PSG (Phos) is formed on the SiN film 10.
(pho Silicate Glass) film 11 (first insulating film) is applied. Subsequently, after the PSG film 11 is planarized by performing a heat treatment, a silicon oxide film 12 (first insulating film) is deposited. This silicon oxide film 12 can be formed by a plasma CVD method using, for example, tetraethoxysilane as a raw material. In addition, a film thickness of 700 nm to 8
After depositing a silicon oxide film 12 of about 00 nm, the surface of the silicon oxide film 12 is subjected to chemical mechanical polishing (CMP; Chem.
(Physical Mechanical Polishing) method, and the surface thereof may be flattened.

Next, as shown in FIGS. 3 and 4, dry etching is performed using the photoresist film as a mask.
The silicon oxide film 12 and the PSG film 11 are dry-etched. Subsequently, by dry-etching the SiN film 10, the contact hole 13A (first connection hole) and the wiring groove 13B reaching the n ⁺ -type semiconductor region 7 (source and drain) and the p ⁺ -type semiconductor region (source and drain) To form The wiring groove 13B is provided for the transfer MISF.
It extends from above the drain of ETQt to above the gate electrode of the load MISFET QLd.

Next, a Ti film having a thickness of about 10 nm and a TiN film having a thickness of about 20 nm are sequentially deposited on the silicon oxide film 12 by, for example, a sputtering method. At this time, the Ti film and the TiN film are
A is also deposited inside the wiring groove 13B. continue,
By subjecting the semiconductor substrate 1 to a heat treatment at about 500 ° C. to 700 ° C. for about 1 minute, the barrier conductor film 14 composed of a laminated film of a Ti film and a TiN film is formed.

Next, a W (tungsten) film 15 for burying the inside of the contact hole 13A and the wiring groove 13B is deposited on the barrier conductor film 14 by, for example, a CVD method. Subsequently, etch back or CMP is performed on the barrier conductor film 14 and the W film 15 until the surface of the silicon oxide film 12 appears, so that the barrier conductor film 14 outside the contact holes 13A and the wiring grooves 13B is formed.
And the W film 15 are removed. Thereby, the plug 16 (first plug) can be formed in the contact hole 13A, and the wiring 17 can be formed in the wiring groove 13B.

Next, as shown in FIG. 5, the surface of the silicon oxide film 21 is further etched by about 150 nm. At this time, the upper portions of the side walls of the plug 16 and the wiring 17 are exposed. When the PSG film 11 is formed, the PSG film 11 is formed.
Silicon oxide film 12 so that the surface of G film 11 is not exposed.
Adjust the film thickness.

Next, as shown in FIGS. 6 and 7, the silicon oxide film 12, the plug 16 and the wiring 17 are
A SiN film 18 of about 0 nm is deposited. Subsequently, by etching the SiN film 18 using a photoresist film, the SiN film 18 is etched such that SiN is left on the protruding surface of the wiring 17 and the periphery thereof. The remaining SiN film 18 is used as a wiring 17 serving as a lower (capacity) electrode
And an upper (capacitance) electrode to be described later, and becomes a capacitance insulating film.

Subsequently, the silicon oxide film 12, the plug 16
Then, a metal film 19 (first thin film (conductive film)) is formed on the SiN film 18. This metal film 19 is provided to prevent an increase in contact resistance between the plug and the plug 16 when the position of the plug formed on the plug 16 in a later step is shifted from a predetermined position. The material is preferably the same as that of the barrier conductor film of the plug. In the present embodiment, a TiN film can be exemplified as the metal film 19.

When the metal film 19 is formed of a TiN film, for example, a CVD method is used to form a 20 nm thick film on the silicon oxide film 12, the plug 16 and the SiN film 18.
After depositing a TiN film of about m, a TiN film of about 20 nm in thickness is deposited by a sputtering method, and a TiN film deposited by a CVD method and a TiN film deposited by a sputtering method.
Together with the N film, a metal film 19 having a thickness of about 40 nm can be formed. When the metal film 19 is formed, the coverage of the metal film 19 in the main surface of the semiconductor substrate 1 can be improved by first using the CVD method.

Next, as shown in FIGS. 8 and 9, a photoresist film R is formed on the surface of the metal film 19 by photolithography. This photoresist film R is
It is formed so as to cover the capacitor formation region and to expose the rest. Thereafter, the metal film 19 is anisotropically etched using the photoresist film as a mask. Thus, the metal film 19 is removed from the upper surface of the plug 16 and the surface appears. Further, the metal film 19 can be left on the side wall of the portion of the plug 16 protruding from the silicon oxide film 12, and the plug 1
6 may be surrounded by a metal film 19. On the other hand, the metal film 19 in the capacitor formation region covered with the photoresist film R
It remains on the film 18 and becomes the upper electrode of the capacitor.

Next, as shown in FIG.
A silicon oxide film 20 (second insulating film) having a thickness of about 1000 nm is deposited on the semiconductor substrate 1 by the method D. Subsequently, the thickness of the silicon oxide film 20 is reduced to about 500 nm by polishing the silicon oxide film 20 by, for example, a CMP method, and then a thickness of 90 nm is formed on the silicon oxide film 20 by, for example, a CVD method.
A silicon oxide film 21 (second insulating film) of about m is deposited.

Subsequently, the silicon oxide films 20 and 21 on the plug 16 are etched by using a photoresist film formed by a photolithography technique.
A contact hole 22 (second connection hole) is formed. At this time, as shown in FIG. 11, due to a mechanical error, the opening position of the contact hole 22 is changed to the lower contact hole 1.
Even in the case where the metal film 19 is relatively shifted from the planar position of 3A, the metal film 19 remaining on the side wall of the plug 16 protruding from the silicon oxide film 12 can be used as an etching stopper. That is, it is possible to increase the margin for aligning the positions of the contact holes 22 without relaxing the layout rule. Even if it has shifted,
It is possible to prevent a problem that the silicon oxide film 12 and the PSG film 11 and the like underneath are cut away. As a result, for example, when a plug is formed in the contact hole 22 in a subsequent step, it is possible to prevent a problem that the conductive film forming the plug and the gate electrode 4 are short-circuited. Further, since the layout rules do not have to be relaxed, it is possible to prevent the element integration degree of the SRAM of the present embodiment from being reduced.

Further, since the metal film 19 remains on the protruding side wall of the plug 16 protruding from the silicon oxide film 12, even if the opening position of the contact hole 22 is shifted, the metal film 19 remains in the contact hole 22. Since a sufficient contact area between the formed plug and the plug 16 can be ensured, an increase in contact resistance between the plug and the plug 16 can be prevented.

On the other hand, when the diameters of the contact holes 13A and the contact holes 22 are sufficiently large, the diameters of the plug and the plug 16 can be set so large that the contact resistance does not matter. In such a case, the metal film 19 is
Instead of the N film, it is also possible to use it only for the purpose of an etching stopper.

Next, as shown in FIG. 12, in order to remove the reaction layer on the surface of the plug 16 exposed at the bottom of the contact hole 22, a surface treatment by sputter etching is performed. Subsequently, a Ti film having a thickness of about 30 nm and a TiN film having a thickness of about 100 nm are sequentially deposited on the silicon oxide film 21 by, for example, a sputtering method, and a barrier conductor film 23 made of a laminated film of a Ti film and a TiN film is formed. (Third
(Conductive film). At this time, the Ti film and Ti
The N film is also deposited inside the contact hole 22. After depositing the Ti film and the TiN film, the semiconductor substrate 1 may be subjected to a heat treatment at about 500 ° C. to 700 ° C. for about 1 minute.

Subsequently, a W film 24 (fourth conductive film) is deposited on the barrier conductor film 23 including the inside of the contact hole 22 by, for example, the CVD method. Then, CMP
The plug 25 (second plug) is formed by removing the barrier conductor film 23 and the W film 24 outside the contact hole 22 by a method or an etch-back method.
Through the steps so far, a stacked via structure having a structure in which the plug 25 overlaps the upper portion of the plug 16 is formed.

At this time, the contact hole 1
13A and FIG. 13B, since a problem of shaving the silicon oxide film 12 and the PSG film 11 under 3A is prevented.
As shown in FIG. 11, in a situation where the opening position of the contact hole 22 is relatively shifted with respect to the planar position of the lower contact hole 13A (see FIG. 11), the plug 25
Is formed, the conductive film constituting the plug 25 does not short-circuit with the gate electrode 4 in the lower layer. Also, plug 25
Is in contact with the metal film 19, it is possible to prevent the contact resistance between the plug 16 and the plug 25 from increasing.

Next, as shown in FIG. 14, a Ti film and a TiN film are sequentially deposited on the silicon oxide film 21 and the plug 25 by, for example, a sputtering method.
A heat treatment at about 0 ° C. to 700 ° C. is performed. Subsequently, an Al (aluminum) film is deposited on the TiN film by, for example, a CVD method, and then a Ti film and a TiN film are sequentially deposited on the Al film. After that, the thin film is patterned to form the wiring 26 on the plug 25, and the SRAM of the present embodiment is manufactured.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

In the above embodiment, the present invention
Although the case where the present invention is applied to a method of manufacturing a RAM has been exemplified,
ASIC with stacked via structure (Application Sp
ecific IC), microcomputer or DRAM (D
It is also possible to apply to other semiconductor integrated circuit devices such as dynamic random access memory.

[0048]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) In the semiconductor integrated circuit device having the stacked via structure, since the thin film is formed on the side wall of the projecting portion of the lower plug protruding from the insulating film, the opening position of the connection hole where the upper plug is formed is lower. Even in the case where the connection hole in which the plug is formed is relatively displaced from the planar position, overetching can be prevented by using the thin film as an etching stopper. (2) In a semiconductor integrated circuit device having a stacked via structure, the position of the connection hole in which the upper layer plug is formed is relatively shifted with respect to the planar position of the connection hole in which the lower layer plug is formed. Even in the case where the thin film is used, overetching can be prevented by using the thin film as an etching stopper, so that the alignment margin between the lower layer plug and the upper layer plug can be improved without relaxing the layout rule. (3) In the semiconductor integrated circuit device having the stacked via structure, since the conductive film is formed on the upper sidewall of the lower plug, the opening position of the contact hole in which the upper plug is formed is shifted from a predetermined position. Also in this case, the contact area between the upper plug and the lower plug can be ensured, so that an increase in the contact resistance between the upper plug and the lower plug can be prevented.

[Brief description of the drawings]

FIG. 1 is a plan view of an essential part showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view showing the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

3 is a fragmentary plan view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;

FIG. 6 is a fragmentary plan view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step;

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

8 is a fragmentary plan view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9;

FIG. 11 is a view showing a case where the position of the upper-layer connection hole is relatively shifted with respect to the planar position of the lower-layer connection hole during the manufacturing process of the semiconductor integrated circuit device following FIG. 9; It is a fragmentary sectional view.

12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10;

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11;

14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

[Description of Signs] 1 semiconductor substrate 2 p-type well 3 gate oxide film 4 gate electrode 5 n ⁻ type semiconductor region 6 sidewall spacer 7 n ⁺ type semiconductor region (source, drain) 9 CoSi ₂ layer 10 SiN film (first Insulating film) 11 PSG film (first insulating film) 12 silicon oxide film (first insulating film) 13A contact hole (first connection hole) 13B wiring groove 14 barrier conductor film 15 W film 16 plug (first plug) 17 wiring Reference Signs List 18 SiN film 19 Metal film (first thin film) 20 Silicon oxide film (second insulating film) 21 Silicon oxide film (second insulating film) 22 Contact hole (second connection hole) 23 Barrier conductor film (first conductive film) ) 24 W film (second conductive film) 25 plug (second plug) An active region Ap active region Qd Driving MISFET Qt Transfer MISFET Ld load MISFET R photoresist film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/108 21/8242 (72) Inventor Fumiaki Endo 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Group (72) Inventor Yasuko Yoshida 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-Term in Hitachi Semiconductor Group, Ltd. (Reference) 5F033 HH08 HH18 HH19 HH33 JJ18 JJ19 JJ33 KK01 KK25 MM01 MM08 MM12 MM13 NN06 NN07 NN37 NN38 PP06 PP15 QQ08 QQ09 QQ11 QQ14 QQ16 QQ24 QQ25 QQ37 QQ48 QQ74 QQ92 RR04 RR06 RR14 SS04 SS15 SS21 TT02 TT06 VV16 XX15 BB31 BF31 BS06 BS03 BS01 BS01 BS48 GA09 JA35 JA39 JA40 LA01 MA05 MA06 MA19 PR34 PR39 PR40

Claims (5)

[Claims] (A) forming a first insulating film on a main surface of a semiconductor substrate; (b) forming a first connecting hole in the first insulating film; and (c) forming the first connecting hole. Forming a first plug therein, (d) removing the first insulating film by a predetermined thickness, and projecting a part of the first plug above the first insulating film, (e) forming the first plug. After depositing a first thin film on an insulating film and on the first plug, the first thin film is anisotropically etched to form at least a side wall of a projecting portion of the first plug projecting on the first insulating film. (F) after the step (e), forming a second insulating film on the first insulating film, the first plug and the first thin film, and (g) forming the second insulating film after the step (e). Forming a second connection hole reaching the first plug in the insulating film; and (h) forming a second plug in the second connection hole. A method of manufacturing a semiconductor integrated circuit device, comprising: 2. A step of forming a first insulating film on a main surface of a semiconductor substrate, a step of forming a first connecting hole in the first insulating film, and a step of forming a first connecting hole in the first insulating film. Forming a first plug therein, (d) removing the first insulating film by a predetermined thickness, and projecting a part of the first plug above the first insulating film, (e) forming the first plug. After depositing a first thin film on an insulating film and on the first plug, the first thin film is anisotropically etched to form at least a side wall of a projecting portion of the first plug projecting on the first insulating film. (F) after the step (e), forming a second insulating film on the first insulating film, the first plug and the first thin film, and (g) forming the second insulating film after the step (e). Forming a second connection hole reaching the first plug in the insulating film; and (h) forming a second plug in the second connection hole. A method of manufacturing a semiconductor integrated circuit device, wherein the first thin film is a conductive film. 3. A step of forming a first insulating film on a main surface of a semiconductor substrate, a step of forming a first connection hole in the first insulating film, and a step of forming a first connection hole in the first insulating film. Forming a first plug therein, (d) removing the first insulating film by a predetermined thickness, and projecting a part of the first plug above the first insulating film, (e) forming the first plug. After depositing a first thin film on an insulating film and on the first plug, the first thin film is anisotropically etched to form at least a side wall of a projecting portion of the first plug projecting on the first insulating film. (F) after the step (e), forming a second insulating film on the first insulating film, the first plug and the first thin film, and (g) forming the second insulating film after the step (e). Forming a second connection hole reaching the first plug in the insulation film, (h) on the second insulation film including the inside of the second connection hole A first conductive film and a second conductive film are sequentially laminated, and the first conductive film and the second conductive film outside the second connection hole are removed, so that the inside of the second connection hole is removed. Forming a second plug at
The method for manufacturing a semiconductor integrated circuit device, wherein the first thin film is a conductive film, and the first conductive film and the first thin film are made of the same material. 4. A first insulating film formed on a main surface of a semiconductor substrate, and a protrusion formed in a first connection hole formed in the first insulating film and protruding from a surface of the first insulating film. A first plug having a portion, a first thin film formed on at least a side wall of the protrusion of the first plug, and a second insulating film formed on the first insulating film, the first plug and the first thin film. A semiconductor integrated circuit device comprising: a film; and a second plug formed in a second connection hole formed in the second insulating film and connected to the first plug. 5. A first insulating film formed on a main surface of a semiconductor substrate, and a protrusion formed in a first connection hole formed in the first insulating film and protruding from a surface of the first insulating film. A first plug having a portion, a first thin film formed on at least a side wall of the protrusion of the first plug, and a second insulating film formed on the first insulating film, the first plug and the first thin film. A second plug formed in a second connection hole formed in the second insulating film and connected to the first plug, wherein the first thin film is a conductive film. Of manufacturing a semiconductor integrated circuit device.