JPH04218957A - High withstand-voltage mos transistor and its manufacture and semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize a high withstand-voltage MOS transistor, which can be miniaturized while realizing a high withstand voltage, in the high withstand- voltage MOS transistor and its manufacture and a semiconductor device having the high withstand-voltage MOS transistor and its manufacture. CONSTITUTION:The drain/source region 15 on the high withstand voltage side of a MOS transistor has an impurity concentration lower than that of a source/ drain region 16, and an electrode 38 composed of a conductive material layer 49 containing a polycrystalline silicon of the same conductive type higher in dose than the drain/source region 15 is directly connected with the drain/source region 15.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method of manufacturing the same, and a semiconductor device having a MOS transistor and a method of manufacturing the same. For details, see DR
A high voltage MOS transistor suitable for use in an AM boost section, a method for manufacturing the same, and such a high voltage MOS transistor
The present invention relates to a semiconductor device having an S transistor and a method for manufacturing the same.

0002

2. Description of the Related Art In DRAMs, in order to apply a sufficiently high voltage to the capacitor of a memory cell and reliably write data, it is common practice to boost the voltage applied to the word line to a level higher than the power supply voltage. There is. FIG. 21 shows an example of a bootstrap word line drive circuit for applying a boosted voltage to a word line. In the figure, the first and second N-type MO
The S transistors 551 and 552 are connected in series, and the drain d3 of the third N-type MOS transistor 553
is connected to the gate g1 of the transistor 551 at a node A.

A boosted voltage V0 from a booster circuit (not shown) is connected to the drain d1 of the transistor 551 at the terminal 55.
5 and the gate g3 of transistor 553
The power supply voltage VCC from a power supply (not shown) is connected to terminal 5.
56. The output signal of a decoder (not shown) is connected to the source s3 of the transistor 553 at the terminal 5.
57. Source s3 and terminal 557 are connected at node B. The gate g2 of the transistor 552 is connected to the reset signal line RL via the terminal 558.
It is connected to the. Source s1 of transistor 551
and d2 of the transistor 552 are connected at a node D, and the node D is connected to the word line WL via a terminal 559. The source s2 of transistor 552 is grounded.

[0004] Transistor 5 is activated by the output signal of the decoder.
53 is selected and turned on, the potential of the source s3 (node B) becomes VCC. The potential of the drain d3 (node A) of the transistor 553 is VCC-Vth (Vt
h is the threshold voltage of the transistor 553). Therefore,
Transistor 551 is turned on and transistor 553 is turned on.
is turned off, and the drain d3 becomes a floating state. Note that the potential at node A becomes voltage Vr which is boosted to higher than boosted voltage V0 due to gate capacitance coupling of transistor 551, so the boosted voltage at node D becomes Vr.
0 is applied to the word line WL without voltage drop. For example, VCC=5V, V0=7.5V, Vr=
It is 14V.

Since a voltage Vr, which is boosted from the power supply voltage VCC, is applied to the drain d3 of the transistor 553, the diffusion layer constituting the drain d3 is required to have a sufficient breakdown voltage. If the diffusion layer constituting the drain d3 does not have a sufficient breakdown voltage, the potential of the node A will gradually decrease, making it impossible to maintain the voltage applied to the word line WL at V0.

[0006] As a method for preventing a drop in the potential of node A,
Although it is possible to thicken the gate oxide film of the transistor 553, this would go against the recent trend of thinning the gate oxide film as semiconductor devices become smaller.

As a conventional example, for example, an LD shown in FIG.
There is a D-structure high voltage MOS transistor. The drain d3 of the transistor 553 is a relatively low concentration, wide N
By widening the depletion layer formed by the type layer 553d and generated at the junction surface between the N type layer 553d and the P type semiconductor substrate 600, it is possible to increase the breakdown voltage. Furthermore, since the drain electrode 601 is usually made of aluminum (Al), the drain d3 is made of a relatively high concentration of N+ at the part where the drain electrode 601 is connected to prevent the contact resistance from increasing.
This is a mold layer 553e. In addition, in FIG. 22, 602
603 is a field oxide film, 603 is a gate oxide film, and 604 is a BPSG interlayer insulating film.

There are generally the first and second methods for manufacturing the above conventional example. According to the first method, a contact hole for the drain electrode 601 is formed in the N+ layer 553e formed in advance. On the other hand, according to the second method, ions are implanted through the contact hole for the drain electrode 601 to form N+ in a self-aligned manner.
A mold layer 553e is formed.

[0009]

[Problems to be Solved by the Invention] FIG. 23 is a diagram for explaining the first method. In the figure, L1 is the gate g
3 and the N+ type layer 553e, L2 is BP
The overlapping distance L3 between the GS interlayer insulating film 604 and the N+ type layer 553e is a distance corresponding to the width of the contact hole for the source electrode 601. drain d3
The breakdown voltage of is determined by L1. However, the N-type layer 553d
If it comes into direct contact with the Al drain electrode 601, the contact resistance will become too large, so the N+ type layer 553e is
Therefore, there is a limit to reducing L3 for making contact. Also, if the contact hole is not formed with a margin of L2, the drain electrode 60
1 may come into direct contact with the N-type layer 553d, so there is a limit to reducing L2. Therefore, conventionally, in order to ensure the withstand voltage of the drain d3 determined by L1, the element would spread in the lateral direction by a distance of L1 +L2 +L3. In other words, there is a limit to the reduction in the area occupied by a high voltage MOS transistor. FIG. 24 is a diagram for explaining the second method. In the same figure (a), the N-type layer 553
s is formed and contact holes are formed in the BPSG interlayer insulating film 604 and the gate oxide film 603. In the same figure (b), after forming the resist layer 605, ion implantation is performed to form an N+ type layer 553e and a source s3.
The process of forming the N+ type layer 553s constituting the is shown. During this ion implantation, impurity ions are also implanted into the portions marked with "x" in FIG. 2B due to the alignment margin of the resist layer 605. For this reason, if pre-treatment with an HF-based etchant is performed before the step of forming the Al layer constituting the drain electrode 601, the etching rate of the ion-implanted portion is faster than that of the other portion. ) will result in a step 610 as shown in FIG. If such a step 610 exists, it is undesirable because it tends to cause disconnection in the wiring layer etc. that will be formed thereafter. Also, compared to the first method, since the N+ type layer 553e is formed in a self-aligned manner, there is an advantage that L2 can be made smaller; however, L1 +L2 +L
There is a limit to the reduction in the area occupied by the high-voltage MOS transistor in order to secure 3. Also, according to the second method,
The number of steps is increased compared to the first method.

[0010] The present invention provides a high-voltage structure that reduces the exclusive area and enables high breakdown voltage of the drain/source without increasing the contact resistance between the drain/source electrode and the diffusion layer constituting the drain/source. An attempt is made to realize a voltage resistant MOS transistor and its manufacturing method, and a semiconductor device having a high voltage resistant MOS transistor and its manufacturing method.

[0011]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of a high voltage MOS transistor according to the present invention. In the same figure,
1 is a first conductivity type semiconductor substrate; 13 is a gate oxide film; 14 is a gate oxide film;
and a gate electrode, 15 a drain/source region of the second conductivity type with a relatively low impurity concentration, 16 a source/drain region of the second conductivity type with a relatively high impurity concentration, 28 a contact hole for the source/drain electrode, and 29 a drain/source region of the second conductivity type with a relatively low impurity concentration. Contact hole for drain/source electrode, 35 is source/drain electrode,
38 is a drain/source electrode, and 27 is an interlayer insulating film. The source/drain electrode 35 and the drain/source electrode 38 are made of a conductor layer 49 containing polycrystalline silicon of the second conductivity type and having an impurity concentration higher than that of the second conductivity type drain/source region 15 . The first and second conductivity types are opposite conductivity types.

0012

[Operation] The drain/source of the MOS transistor is composed only of the relatively lightly doped second conductivity type drain/source region 15, and the drain/source electrode 38 is formed via the relatively highly doped second conductivity type region. The second conductivity type drain/source region 15 is connected directly to the second conductivity type drain/source region 15. Therefore, L2 required in the conventional method becomes unnecessary, and the MOS transistor can be miniaturized accordingly.

The drain/source electrode 38 is directly connected to the relatively lightly doped second conductivity type drain/source region 15, but the drain/source electrode 38 is not made of Al but is made of a second conductivity type drain/source region 15.
Since the conductive layer 49 is of a conductive type and includes polycrystalline silicon, contact resistance does not increase. Furthermore, since the relatively low concentration second conductivity type drain/source region 15 is thin, if an Al electrode is formed directly above it, Al spikes will be a problem, but since the drain/source electrode 38 does not use Al, spikes will be a problem. does not occur.

Furthermore, compared to contacts between Al and Si, contacts between polycrystalline silicon and Si can be formed with a lower impurity concentration. Since the breakdown voltage of a transistor increases as the impurity concentration decreases, it is easier to increase the breakdown voltage of the transistor in the present invention compared to the conventional example.

A second electrode constituting the drain/source electrode 38
When a conductive layer 49 containing polycrystalline silicon of a conductive type is formed, impurities in the conductive layer 49 are diffused into the comparatively low concentration second conductive type drain/source region 15 to a depth shallower than that depth by solid phase diffusion. do. This makes it possible to reduce contact resistance. Furthermore, since the boundary between the relatively low concentration second conductivity type drain/source region 15 and the above-mentioned portion where the concentration has increased due to solid phase diffusion is gentle, a structure with higher breakdown voltage than the conventional structure can be realized. Ru.

FIG. 2 is a diagram showing the characteristics of the high voltage MOS transistor according to the present invention in comparison with a conventional example. In the same figure,
The vertical axis shows the impurity concentration on a log scale, and the horizontal axis shows the impurity concentration in Figure 1,
The x direction at 22 and 24 is shown. Dashed lines I and II indicate the characteristics of the conventional examples manufactured by the first and second methods, respectively,
The dashed line III indicates the characteristics of the high voltage MOS transistor according to the present invention.

Therefore, according to the present invention, the area occupied by a multi-voltage MOS transistor can be reduced, and the drain/source electrode can be formed without increasing the contact resistance between the drain/source electrode and the diffusion region constituting the drain/source. This makes it possible to achieve high voltage resistance.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a semiconductor device according to the present invention having a first embodiment of a high voltage MOS transistor according to the present invention will be described with reference to FIG. 1A is a cross-sectional view of the semiconductor device, and FIG. 1B is a circuit diagram thereof.

A P-type semiconductor substrate 1 made of silicon or the like is formed with a plurality of elements such as N-type MOS transistors to be described later. A bootstrap word line drive circuit 2 for applying a voltage to the word line WL includes three MOS transistors 3 to 5, which will be described later. The first MOS transistor 3 and the second MOS transistor 4 are connected in series,
The drain layer 15 of the third MOS transistor 5 is connected to the gate electrode 7 of the first MOS transistor 3.

The first MOS transistor 3 includes a gate electrode 7 formed on the semiconductor substrate 1 via a gate oxide film 6, and N+ and N- electrodes formed on the semiconductor substrate 1 on both sides of the gate electrode 7. The source layer 8 and the drain layer 9 have an LDD structure.

The second MOS transistor 4 is formed of a gate electrode 11 provided on the semiconductor substrate 1 via a gate oxide film 10, and a source layer 12 and a drain layer 113 of an LDD structure formed on both sides of the gate electrode 11. ing. Since the drain layer 113 is provided integrally with the source layer 9 of the first MOS transistor 3, the drain layer 113 is integrated with the source layer 9 of the first MOS transistor 3.
S transistors 3 and 4 are connected in series.

The third MOS transistor 5 has a gate electrode 14 formed on a gate oxide film 13, an N- type conductive layer 15 is provided on the substrate 1 on one side, and an LDD on the other side. It has a structure in which a conductive layer 16 of the structure is formed. The N- type conductive layer 15 is connected to the gate electrode 7 of the first MOS transistor 3 via a wiring electrode (not shown).

Stacked capacitor type DRAM cell 17
The fourth MOS transistor 18 constituting the
A gate electrode 21 formed on the semiconductor substrate 1 via a gate electrode 21, and an N type or N- type conductive layer 22 provided on both sides of the gate electrode 21,
23. One conductive layer 22 is connected to the bit line BL, and the gate electrode 21 is connected to the word line WL. A capacitor 19 of the DRAM cell 17 is provided on the other conductive layer 23 through a contact hole 34, which will be described later. This capacitor 19 includes a storage electrode 24 made of polycrystalline silicon doped with N-type impurity ions such as phosphorus (P), a dielectric film 25 made of SiO2, and a counter electrode made of polycrystalline silicon containing N-type impurity ions. It is formed by laminating 26 in order,
A voltage of VCC/2 is applied to the counter electrode 26.

[0024] First to fourth MOS transistors 3 to 5, 1
Contact holes 28 to 33 are formed in an interlayer insulating film 27 made of PSG or the like formed on 8 to expose the conductive layers 8, 9, 15, 16, etc. Interlayer insulation film 27
On top of each source layer 9, 12 and drain layer 8, 13
Electrodes 35 to 40 made of polycrystalline silicon with impurities of the same polarity diffused therein are formed to fill the contact holes 28 to 33. Also, similar to these, the fourth MOS
An electrode 41 is formed on one conductive layer 22 of the transistor 18 .

Note that 42 is a field oxide film formed around the first to third MOS transistors 3 to 5 and around the DRAM 17 by a selective oxidation method.

In this embodiment, when writing data to the DRAM cell 17, first, the power supply voltage VCC is applied to the gate electrode 14 of the third MOS transistor 5. When an output signal from a decoder (not shown) is input to the N+ type conductive layer 16 of the third MOS transistor 5, the potential of this conductive layer 16 becomes VCC. As a result, the potential of the N- type conductive layer 15 becomes VCC-Vth (Vth is the gate threshold voltage), the first MOS transistor 3 is turned on, and the third MOS transistor 5 is turned off.
N- type conductive layer 15 is boosted to a level higher than boosted potential V0 due to capacitive coupling of first MOS transistor 3. Therefore, the boosted voltage V0 is applied to the drain layer 9 of the first MOS transistor 3 and the word line WL without voltage drop.

As a result, the boosted voltage V is applied to the gate electrode 21 of the fourth MOS transistor 18 via the word line WL.
0 is applied. The fourth MOS transistor 18 selected by the bit selection signal from the bit line BL is turned on, charges are accumulated in the capacitor 19 connected to it, and data is written into the DRAM cell 17. When a boosted voltage V0 higher than the power supply voltage VCC is applied to the drain layer 8 of the first MOS transistor 3, the gate electrode 7 of the first MOS transistor 3 is boosted by capacitive coupling to a potential approximately twice that of V0. Become. Therefore, a doubly boosted voltage is also applied to the N- type conductive layer 15 of the third MOS transistor 5. However, since the conductivity type 15 of the third MOS transistor 5 is reduced in concentration and becomes N- type, it has a high breakdown voltage with respect to the semiconductor substrate 1.

Moreover, since the N- type conductive layer 15 is composed of only a low concentration layer without a high concentration conductive layer, the area of the device does not become large. Moreover, N-
Since the electrode 38 made of polycrystalline silicon containing impurities of the same polarity as that of the N- type conductive layer 15 is formed on the N- type conductive layer 15, the impurities in the electrode 38 are removed by annealing.
By shallowly diffusing it into the type conductive layer 15, the contact resistance can be lowered.

FIG. 4 is a diagram showing the relationship between the dose of polycrystalline silicon and the contact resistance between the electrode 38 and the N- type conductive layer 15. In the figure, the vertical axis shows resistance on a log scale, and the horizontal axis shows the dose on a log scale. Figure 4
In this case, the film thickness of the polycrystalline silicon electrode 38 is 2000 Å, N-
The impurity dose of the type conductive layer 15 is 1×10 13 /cm
2, and it can be seen from the same figure that the contact resistance is extremely small when the dose of polycrystalline silicon is 1×10 15 /cm 2 or more.

FIGS. 5 and 6 are enlarged views of the main parts of the first embodiment of the high voltage MOS transistor. In this embodiment, the N+ type conductive layer 16 is an LD as shown in FIG.
It has a D structure, and has an N+ type part 161 and an N- type part 162.
It consists of The impurity concentration of the N+ type part 161 is N-
The impurity concentration of the N- type part 162 is substantially the same as that of the N- type conductive layer 15. Further, as shown in FIG. 6, the N- portion 162 partially overlaps the gate electrode 14.

Note that the dose of P ions in the N- type conductive layer 15 is 1×10 3 /cm 2 , the thickness of the polycrystalline silicon electrode 38 is 2000 Å, and the dose of P ions in the polycrystalline silicon is 1×10 15 /cm 2 . cm2, and the distance D between the gate electrode 14 and the contact hole 29 shown in FIG. 5 is 1
Under the μm condition, a breakdown voltage of 20V could be secured at the drain of the MOS transistor.

Next, taking the method of forming the first and third MOS transistors 3 and 5 as an example, the drain layer 1 with a low concentration
An embodiment of a method for manufacturing a semiconductor device having a high concentration source layer 16 and a high concentration source layer 16 will be described.

First, a first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described. As shown in FIG. 7(a), first and third transistor forming regions T1,
Field oxide film 4 is formed around T2 by LOCOS method.
After forming 2, gate oxide films 6 and 13 are formed by thermal oxidation. Thereafter, a polycrystalline silicon film containing impurities is formed and patterned by photolithography, and a gate electrode 7 made of polycrystalline silicon is placed in the center of each transistor forming region T1, T2 via gate oxide films 6, 13. , 14.

Then, N-type impurity ions such as P are implanted and diffused in a self-aligned manner on both sides of the gate electrodes 7 and 14 to form a low concentration conductive layer 43. The impurity dose in this case is 1013 to 1014/cm2, and N-
A mold conductive layer 43 is formed.

Thereafter, as shown in FIG. 7(b), a SiO2 film 44 with a thickness of about 1000 Å is formed on the entire surface by CVD. Further, one conductive layer 43 and its surroundings in the third transistor formation region T2 are covered with a resist 45, and SiO2 is etched by reactive ion etching (RIE).
When the film 44 is selectively removed, the portion of the SiO2 film 44 covered by the resist 45 remains, and sidewalls 46 of the remaining SiO2 film 44 are formed beside the gate electrodes 7 and 14 as shown in FIG. 7(c). It is formed.

Next, by implanting and diffusing arsenic (As) ions into the semiconductor substrate 1 using the SiO2 film 44 and sidewalls 46 as masks, a high concentration layer of about 1020/cm3 is formed in the region not covered by the SiO2 film 44. The conductive layer 43 thus formed has an LDD structure. In this case, SiO
2. The conductive layer 43 covered with the film 44 is maintained in a low concentration state as shown in FIG. 7(d).

After that, as shown in FIG. 8(a), Si is applied to the entire surface.
By forming an O2 film 47 and patterning the SiO2 film 47 and the SiO2 film 44 by photolithography, contact holes 28 to 31 as shown in FIG. 8(b) are formed on the conductive layer 43.

Next, after forming a polycrystalline silicon film 49 with a thickness of about 2000 Å over the entire surface, P ions are added to the film at 1×10
Implant at a dose of 15/cm2. Further, the polycrystalline silicon film 49 is selectively etched by photolithography to form a contact hole 2 as shown in FIG. 8(c).
A polycrystalline silicon film 49 is left in areas 8 to 31.

In this state, the conductive layer 43 formed in the first transistor formation region T1 has an LDD structure, with one layer forming the drain layer 8 shown in FIG. 3 and the other forming the source layer 9. Further, the third transistor formation region T2
Of the conductive layers 43 formed therein, the one covered with the SiO2 film 44 and in a low concentration state constitutes the N- type conductive layer 15, and the other constitutes the conductive layer 16 having an LDD structure. Furthermore, the polycrystalline silicon film 49 left in the contact holes 28-31 is used as electrodes 35-38.

In subsequent heating steps such as thermal oxidation and annealing, the electrodes 35 to 38 are heated, and the impurities contained therein are absorbed into the source layer 9, drain layer 8, conductive layer 15,
16, these layers and electrodes 35-38
The contact resistance with the

Therefore, one conductive layer 15 of the third MOS transistor 5 to which a voltage higher than the boosted voltage V0 is applied
Even if it is N- type, the contact resistance with the electrode 38 is low and good contact can be achieved.

By the way, when covering the N- type conductive layer 15 of the third MOS transistor 5 with the SiO2 film 44, if the SiO2 film 44 is patterned using the resist 45 as a mask, as shown in FIG. The periphery of the SiO2 film 44 remaining on the substrate 1 has a vertical shape, resulting in a step. Therefore, if the SiO2 film 44 is thick, problems such as disconnection of wiring and etching residue during processing may occur in subsequent steps.

A second embodiment of the method for manufacturing a semiconductor device according to the present invention, which improves this problem, will be described with reference to FIG.

FIG. 9(a) shows a state in which the resist 45 has been removed from the step of FIG. 7(c). Next, as shown in FIG. 9(b), a second SiO2 film 44b with a thickness of 1000 Å is deposited on the entire surface.
After laminating the layers to a thickness of
When the film 44b is etched, the side edges of the SiO2 film 44 remaining on the source layer 15 become smooth as shown in FIG. 9(c), improving step coverage. In this case, the sidewalls 46 on both sides of the gate electrodes 7 and 14
is formed in two layers, and its thickness can be easily controlled by adjusting the thickness of the first and second SiO2 films 44, 44b.

After that, the sidewall 46 and SiO2
Implanting impurity ions using the films 44 and 44b as a mask,
The conductive layer 43 having an LDD structure and the conductive layer 43 having a low concentration coexist as shown in FIG. 9(d) in the same way as in the case of FIG. 7(d).

According to the second embodiment of the method for manufacturing a semiconductor device, the second embodiment of the high voltage MOS transistor of the present invention is manufactured. FIG. 10 shows the main part of a second embodiment of a high voltage MOS transistor. In this embodiment, the N- type portion 162 of the N+ type conductive layer 16 is formed under the sidewall 46.

Next, a third embodiment of the high voltage MOS transistor according to the present invention will be described with reference to FIG. In the figure, the same parts as in FIG. 3 are designated by the same reference numerals, and the explanation thereof will be omitted. In this embodiment, the contact hole 28 and the gate electrode 1
12 shows the relationship between the distance d2 and the withstand voltage on the N- type conductive layer 15 side. From the figure, it can be seen that when d2 is about 0.8 μm or more, the breakdown voltage is 20V.

FIG. 13 is a diagram for explaining fourth and fifth embodiments of the high voltage MOS transistor according to the present invention. In the figure, the same parts as those in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted. FIG. 13(a) shows a cross section of the fourth and fifth embodiments, and FIGS. 13(b) and 13(c) show plane views of the fourth and fifth embodiments, respectively. As shown in FIG. 13(b), in the fourth embodiment, the contact hole 29 consists of a plurality of holes. On the other hand, as shown in FIG. 13(c), in the fifth embodiment, the contact hole 29 is a single hole larger than that in the fourth embodiment. In the fifth embodiment, a larger contact area can be obtained than in the fourth embodiment.

Note that when forming the electrode 38 and the like using polycrystalline silicon, the manufacturing process can be simplified if the electrode 38 and the like are formed in the same process as the conductive layer of the semiconductor device. Therefore, in the second embodiment of the semiconductor device according to the present invention, the polycrystalline silicon layer forming the electrode 38 is also used as a conductive layer in the DRAM. FIG. 14 shows the main part of the second embodiment of the semiconductor device, and FIG.
The same parts are given the same reference numerals, and their explanation will be omitted. For example, the storage electrode 24 and electrode 38 of the DRAM may be formed from the same polycrystalline silicon layer, and the bit line BL and the electrode 38 of the DRAM may be formed from the same polycrystalline silicon layer.

Next, a first embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention will be described with reference to FIG. In the figure, the same parts as in FIGS. 7 and 8 are designated by the same reference numerals, and the explanation thereof will be omitted.

In this embodiment, as shown in FIG. 15(a),
As explained in conjunction with FIG. 7(a), the field oxide film 42 is formed by the LOCOS method, the gate oxide film 13 is formed by the thermal oxidation method, and the gate electrode 14 is formed by forming and patterning a polycrystalline silicon film. Then, a low concentration conductive layer 43 is formed by ion implantation.

Thereafter, as shown in FIG. 15(b), FIG.
As explained in conjunction with c), a resist 45 is formed on the conductive layer 43 on the side to which a high voltage is applied. By performing ion implantation using the field oxide film 42, gate electrode 14, and resist 45 as masks, a conductive layer 43 (source layer 16) having an LDD structure is formed.

The formation of interlayer insulating films, contact holes, and electrodes may be performed in the same manner as in FIGS. 7 and 8, and their explanations will be omitted.

Next, a second embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention will be described with reference to FIG. In the figure, the same parts as in FIGS. 7 and 8 are designated by the same reference numerals, and the explanation thereof will be omitted.

In this example, after obtaining the structure shown in FIG. 15(a), an SiO2 oxide film 44 is formed on the entire surface and R
By etching the SiO2 oxide film 44 using the IE method, sidewalls 46 are formed on the side surfaces of the gate electrode 14 as shown in FIG. Furthermore, a resist 45 is formed on the conductive layer 43 on the side to which a high voltage is applied. Field oxide film 42, sidewall 46, gate electrode 14
By performing ion implantation using the resist 45 as a mask, the conductive layer 43 (source layer 16
) is formed.

Next, a third embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention will be described with reference to FIG. In the figure, the same parts as in FIGS. 7 and 8 are given the same reference numerals, and the description thereof will be omitted. In this embodiment, a conductive layer 43 (source layer 16) having an LDD structure is formed using an SiO2 oxide film 44 as part of a mask instead of the resist 45 shown in FIG. 15(b).

Next, a fourth embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention will be described with reference to FIG. In the figure, the same parts as in FIGS. 7 and 8 are designated by the same reference numerals, and the explanation thereof will be omitted. In this example, the SiO
2. When etching the oxide film 44 by the RIE method, a sidewall 46 is formed on the side surface of the gate electrode 14. Therefore, when forming the conductive layer 43 (source layer 16) of the LDD structure, the sidewall 46 is also used as part of the mask.

Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In the same figure, Figure 3,
The same parts as 7 and 8 are given the same reference numerals, and the explanation thereof will be omitted. In this embodiment, after forming the gate electrode 14 of the high voltage MOS transistor 5 and the gate electrode 21 of the MOS transistor 18 of the DRAM cell 17 as shown in FIG. 19(a), an SiO2 oxide film 44 is formed on the entire surface. MO that configures memory cells using photolithography technology
On S transistor 18 and high voltage MOS transistor 5
SiO2 oxide film 4 on the conductive layer 43 (drain layer 15)
As shown in FIG. 19(b), ions are implanted using the SiO2 oxide film 44 as a mask, leaving only the conductive layer 43 (source layer 16) having an LDD structure. In addition, SiO
2 The sidewall 46 remaining on the side surface of the gate electrode 14 when the oxide film 44 is etched by the RIE method is also shown in FIG.
used as part of a mask, as in the case of

Next, a fourth embodiment of the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG. In the figure, the same parts as those in FIGS. 3 and 9 are designated by the same reference numerals, and the explanation thereof will be omitted. In this example, as shown in FIG. 20(a), SiO2
After etching the oxide film 44 by the RIE method, a SiO2 film 44b is further laminated, and this S layer is etched by the RIE method.
Etch the iO2 layer 44b. As a result, Figure 2
As shown in FIG. 0(b), the side edges of the SiO2 oxide film 44 remaining on the conductive layer 43 (source layer 16) and the gate electrode 14 become smooth, and both sides of the gate electrode 21 also become smooth. Therefore, inconveniences such as disconnection of wiring in subsequent steps and etching residue during effect processing can be prevented.

Note that etching the oxide film directly exposes the substrate surface to etching, which increases junction leakage due to contamination, surface damage, and the like. Therefore, it is preferable not to etch the oxide film in the memory cell portion of the DRAM, where a small leakage current can lead to deterioration of characteristics. In the third and fourth embodiments of the semiconductor device manufacturing method described above, it is necessary to cover the memory cell portion with a resist when etching the SiO2 oxide film 44. However, since the conductive layer 43 (drain layer 15) of the high voltage MOS transistor 5 is also covered with resist at the same time, no additional steps are required. Note that although the conductive layers 22 and 23 in the memory cell portion have the same relatively low impurity concentration as the conductive layer 43 (drain layer 15), high-concentration ion implantation induces crystal defects and causes junction leakage. , this is a rather desirable condition.

In each of the above embodiments, the electrode formed on the low concentration conductive layer is made of polycrystalline silicon, but amorphous silicon or high melting point metal silicide may be used instead of polycrystalline silicon. The high melting point metals contained in the high melting point metal silicide include tungsten (W), molybdenum (Mo), tantalum (Ta), and titanium (Ti).
etc. Alternatively, a polycide film in which a high melting point metal silicide such as tungsten silicide is laminated on a polycrystalline silicon film may be used as an electrode on the conductive layer. Furthermore, an Al wiring layer may be formed on the electrode made of polycrystalline silicon or polycide, and "AL" in FIG. 1 indicates the Al wiring layer. Note that in order to form a polycide film, for example, the film thickness is 0.
．． After a 0.1 μm thick high melting point metal film is laminated on a 1 μm thick polycrystalline silicon film, for example, P ions may be implanted at a dose of about 10 15 /cm 2 from above the high melting point metal film.

[0062]

According to the present invention, since the relatively low concentration drain/source region of a high voltage MOS transistor is directly connected to the drain/source electrode, it is possible to miniaturize the MOS transistor. Since a conductor containing polycrystalline silicon is used for the source electrode, the drain/
This is extremely useful in practice, since it is possible to prevent an increase in contact resistance between the source region and the drain/source electrode, and also to achieve a high breakdown voltage.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view illustrating the principle of a high voltage MOS transistor according to the present invention.

FIG. 2 is a diagram showing the characteristics of a high voltage MOS transistor according to the present invention in comparison with a conventional example.

FIG. 3 is a cross-sectional view and a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

[Figure 4] Impurity dose of polycrystalline silicon, electrode and N-
FIG. 3 is a diagram showing the relationship between the contact resistance and the mold conductive layer.

[Fig. 5] The first high-voltage MOS transistor according to the present invention
FIG. 2 is an enlarged cross-sectional view showing the main parts of the embodiment.

FIG. 6: The first high-voltage MOS transistor according to the present invention
FIG. 2 is an enlarged cross-sectional view of the main part of the embodiment.

FIG. 7 is a cross-sectional view illustrating a first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view illustrating a first embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view illustrating a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a sectional view showing a main part of a second embodiment of a high voltage MOS transistor according to the present invention.

FIG. 11 is a sectional view showing a main part of a third embodiment of a high voltage MOS transistor according to the present invention.

FIG. 12 is a diagram showing the relationship between the distance d2 and the withstand voltage on the N- type conductive layer side.

FIG. 13 is a sectional view and a plan view of main parts for explaining fourth and fifth embodiments of a high voltage MOS transistor according to the present invention.

FIG. 14 is a sectional view showing a main part of a second embodiment of the semiconductor device according to the present invention.

FIG. 15 is a cross-sectional view illustrating a first embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention.

FIG. 16 is a cross-sectional view illustrating a second embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention.

FIG. 17 is a cross-sectional view illustrating a third embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention.

FIG. 18 is a cross-sectional view illustrating a fourth embodiment of the method for manufacturing a high voltage MOS transistor according to the present invention.

FIG. 19 is a cross-sectional view illustrating a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 20 is a cross-sectional view illustrating a fourth embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 21 is a circuit diagram showing an example of a bootstrap word line drive circuit.

FIG. 22 is a cross-sectional view showing an example of a high voltage MOS transistor with a conventional LDD structure.

FIG. 23 is a cross-sectional view illustrating an example of a conventional method for manufacturing a high voltage MOS transistor.

FIG. 24 is a cross-sectional view illustrating another example of a conventional method for manufacturing a high voltage MOS transistor.

[Explanation of symbols]

1 Semiconductor substrate 2 Boost circuit 3 First MOS transistor 4 Second MOS transistor 5 Third MOS transistor 6,13 Gate oxide film 7,14 Gate electrode 8 Source layer 9 Drain layer 15 N- type conductive layer 16 Conductive layer with LDD structure 35-38 electrode 44 SiO2 film

Claims (17)

[Claims] 1. A high breakdown voltage semiconductor substrate comprising a semiconductor substrate (1), a first diffusion region (15) and a second diffusion region (16) of conductivity type opposite to that of the semiconductor substrate, and a gate electrode (14). M
In the OS transistor, the first diffusion region (15)
The impurity concentration of is lower than the impurity concentration of the second diffusion region (16), and at least the electrode (38) directly connected to the first diffusion region (15) is made of a conductor (49) containing polycrystalline silicon. The conductor (4) containing the polycrystalline silicon
9) A high breakdown voltage MOS transistor characterized in that the impurity concentration of the first diffusion region (15) is higher than that of the first diffusion region (15). 2. The second diffusion region (16) is a first region formed on the surface side of the semiconductor substrate (1) and has substantially the same impurity concentration as the first diffusion region (15). (1
62) and a second region (161) which has an impurity concentration higher than that of the first diffusion region (15) and is continuous with the first region. The high voltage MOS transistor according to claim 1. 3. The high withstand voltage according to claim 2, wherein a sidewall (46) of an insulating film is formed at least on the first region (162) on a side surface of the gate electrode (14). MOS transistor. 4. A conductor (4) containing the polycrystalline silicon;
4. The high breakdown voltage MOS transistor according to claim 1, 2 or 3, wherein the depth of the solid phase diffusion from 9) to the first diffusion region is shallower than the depth of the first diffusion region. 5. A step of selectively forming a field oxide film (42) on the semiconductor substrate (1), and forming a gate oxide film (13) and a gate in a region on the semiconductor substrate limited by the field oxide film. Impurity regions (43, 15, 1
6) and one impurity region (43, 15).
) with a mask layer (45, 44), and a second ion implantation is performed using the field oxide film, the gate electrode, and the mask layer as a mask to form the other impurity region (43, 1).
Step 6) of making the impurity concentration higher than the impurity concentration of the one impurity region, and directly applying a conductor ( 49) A method for manufacturing a high voltage MOS transistor, comprising the step of forming an electrode (38) comprising: 6. The one impurity region (43, 15)
In the step of covering with a mask layer (45, 44), the mask layer is formed on the entire surface of the semiconductor substrate (1) and selectively etched to remove at least the other impurity on the side surface of the gate electrode (14). 6. The method of manufacturing a high-voltage MOS transistor according to claim 5, characterized in that sidewalls (46) of the mask layer are left on the regions (43, 16). 7. The one impurity region (43, 15)
In the step of covering with the mask layer (45, 44), a second mask layer (44b) is further laminated on the mask layer and selective etching is performed to cover the side edges of the mask layer and the sidewall (44b). 7. The method of manufacturing a high voltage MOS transistor according to claim 6, wherein the portion (46) is made gentle. 8. A semiconductor substrate (1), a first diffusion region (15) and a second diffusion region (16) of opposite conductivity type to the semiconductor substrate, and a semiconductor substrate formed on the first diffusion region. A semiconductor device having a high voltage MOS transistor comprising a first electrode (38) formed on the second diffusion region, a second electrode (35) formed on the second diffusion region, and a gate electrode (14). The impurity concentration of the diffusion region (15) is lower than the impurity concentration of the second diffusion region (16), and at least the first electrode (38) has an impurity concentration higher than that of the first diffusion region. It is characterized by being made of a conductor (49) containing crystalline silicon, and configured such that a voltage higher than the voltage applied to the second electrode (35) is applied to the first electrode (38). A semiconductor device having a high voltage MOS transistor. 9. A plurality of elements are formed on the semiconductor substrate (1), and the conductor (49) containing polycrystalline silicon is in the same layer as the conductive layer of at least one element. A semiconductor device comprising the high voltage MOS transistor according to claim 8. 10. A plurality of elements are formed on the semiconductor substrate (1), and the conductor (49) containing polycrystalline silicon is in the same layer as a wiring layer connected to at least one element. A semiconductor device having a high voltage MOS transistor according to claim 8 or 9. 11. The high voltage MOS transistor (5
) further includes another MOS transistor (3) to which a voltage (V0) higher than the power supply voltage (VCC) applied externally to the gate electrode (14) of the transistor (3) is applied to one of the source electrode and the drain electrode. 9. A semiconductor device having a high voltage MOS transistor according to claim 8, wherein the gate electrode (7) of the other MOS transistor is connected to the first electrode (38) of the high voltage MOS transistor. 12. The high voltage MOS transistor (5
) and the gate electrode (7) of the other MOS transistor (3) is higher than the voltage (V0). A semiconductor device having a high voltage MOS transistor. 13. Said other MOS transistor (3)
13. A semiconductor device having a high voltage MOS transistor according to claim 11 or 12, wherein the other of the source electrode and the drain electrode is connected to a word line (WL) of the memory cell (18, 19). 14. The memory cell (18, 19) has 1
one MOS transistor (18) and one capacitor (
19) The high withstand voltage M according to claim 13, characterized in that it consists of
A semiconductor device having an OS transistor. 15. A method for manufacturing a semiconductor device having at least a high voltage MOS transistor (5) and a MOS transistor (18) constituting a memory cell on a semiconductor substrate (1). a step of forming a field oxide film (42); a step of sequentially forming a gate oxide film (13, 20) and a gate electrode (14, 21) in a region on the semiconductor substrate limited by the field oxide film; By the first ion implantation, impurity regions (4
3, 15, 16, 22, 23) and the impurity region (
43, 22, 23) and one impurity region (43, 15) of the high voltage MOS transistor is covered with a mask layer (45, 44).
), the field oxide film, the high voltage MO
A second ion implantation is performed using the gate electrode (14) of the S transistor and the mask layer as a mask to form the high voltage MOS.
a step of making the impurity concentration of the other impurity region (43, 16) higher than the impurity concentration of the one impurity region (43, 15); impurity region (43,1
5) Forming an electrode (38) made of a conductor (49) containing polycrystalline silicon with an impurity concentration higher than the impurity concentration in step 5). 16. In the step of covering with the mask layer (45, 44), the mask layer is formed on the entire surface of the semiconductor substrate (1) and selectively etched, and the high voltage MOS
16. The high voltage MOS transistor according to claim 15, wherein a sidewall (46) of the mask layer is left on at least the other impurity region (43, 16) on a side surface of the gate electrode (14) of the transistor. A method for manufacturing a semiconductor device. 17. The step of covering with the mask layer (45, 44) includes forming a second mask layer (44b) on the mask layer.
are further laminated and selectively etched to remove the side edges of the mask layer, the side wall (46) and the gate electrode (2) of the MOS transistor constituting the memory cell.
17. The method of manufacturing a semiconductor device having a high voltage MOS transistor according to claim 16, wherein the portions on both sides of step 1) are made smooth.