JP2980086B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to the formation of a device between a trench element isolation region and a first field insulating film having an upper surface lower than the surface of a silicon substrate. The first MOS transistor formed in the region (edge operation type) and the element formation region formed between the second field insulating film having the upper surface at a position higher than the upper surface of the first field insulating film. And a method of manufacturing the same.

[0002]

2. Description of the Related Art DRAMs and SRAMs are required to have low power consumption and high speed. An effective means of reducing power consumption is to lower the power supply voltage. However, for example, lowering the power supply voltage while the threshold voltage V _t was kept constant of the MOS transistors constituting the DRAM, the ratio of the threshold voltage is increased to the supply voltage, slower switching speed of the circuit, The demand for higher speed will not be satisfied.

[0003] It is naturally considered to lower the V _t itself as a countermeasure. However, in the MOS transistor constituting a memory cell of a conventional DRAM, it is difficult to be lowered V _t by lowering the supply voltage for the following reasons. For example, a DRAM memory cell has one N-channel M
It is composed of an OS transistor and one capacitor, and information is held when the capacitor is kept at “high” or “low” potential. Here, in order to charge stored in the capacitor is not lost when the gate voltage V _G of the N-channel MOS transistor constituting the memory cell is 0V flows from the drain region of the transistor to the source region (drain current I _D 1) The leakage current must be sufficiently small. This leakage current and V _t (V
I _D in the sub-threshold region consisting of _G <V _t
The determined by the defined are) S value V _G needed to 1 order of magnitude, as the V _t is larger or as the S value is smaller the leakage current is reduced. For this reason, even if the power supply voltage drops, in order to keep this leakage current small, V
_t had to be set large. Similarly, in an SRAM including a MOS transistor, an N-channel M (which is a transfer transistor of a memory cell)
OS transistor also had increased to set the V _t in order to hold the information of the memory cell.

Japanese Patent Application Laid-Open No. 8-335 filed by the present applicant earlier
Japanese Patent Publication No. 700 discloses that an N-channel M
Means for reducing the S value of the OS transistor is disclosed. The upper surface of the field insulating film surrounding the element formation region where the N-channel MOS transistor is formed is provided at a position lower than the surface of the P-type silicon substrate by a height of 25 nm or more and 100 nm or less. The gate electrode (word line) of this N-channel MOS transistor extends over the upper surface of the field insulating film. With such a structure, in the N-channel MOS transistor, depletion is likely to occur at the channel edge, so that the ordinary narrow channel effect does not occur. Will function as For this reason, the present inventors have proposed this N-channel MO.
The S transistor is called an edge operation type N-channel MOS transistor.

FIG. 15 is a schematic plan view of a semiconductor device.
15 (a) and FIGS. 15 (b), 15 (c) and 15 (d), which are schematic cross-sectional views taken along lines AA, BB and CC in FIG. 15 (a). DR including edge operation type MOS transistor described in Japanese Patent Publication
AM is as follows. Note that FIG.
In (a), the portion of the field insulating film is hatched by a dotted line that is descending to the left.

In a cell array region on the surface of a P-type silicon substrate 301, T-shaped element forming regions 3 which are regularly arranged are arranged.
In the peripheral circuit region on the surface of the P-type silicon substrate 301, an element forming region 303b and the like are provided. The impurity concentration on the surface of the element formation region 303a is set higher than the impurity concentration on the surface of the element formation region 303b. A groove 305 having a desired depth is provided on the surface of the P-type silicon substrate 301 surrounding the element formation regions 303a and 303b, and the groove 305 is filled with a field insulating film 307 made of a silicon oxide-based insulating film. The upper surface of the field insulating film 307 is lower than the surface of the P-type silicon substrate 301 by, for example, about 50 nm. A gate oxide film 309 is provided on the side surface of the groove 305 exposed on the field insulating film 307 and on the surface of the P-type silicon substrate 301 forming the element forming regions 303a and 303b.

In the memory cell region, a word line 311 serving as a gate electrode is formed on the surface of a P-type silicon substrate 301 forming a plurality of element forming regions 303a via a gate oxide film 309.
a in the peripheral circuit region, a P-type silicon substrate 30 forming an element forming region 303b via a gate oxide film 309.
The gate electrode 311b crosses over the surface of No. 1. The gate electrode 311b extends on the upper surface of the field insulating film 307. The word line 311a is formed by stacking a tungsten silicide film pattern 339a on an N ⁺ type polysilicon film pattern 337a, and the gate electrode 311b is formed by N
^A tungsten silicide film pattern 339b is laminated on the ⁺ type polycrystalline silicon film pattern 337b. An N-type source / drain region 313a is provided in a self-aligned manner with the word line 311a on the surface of the P-type silicon substrate 301 forming the element forming region 303a, and a gate is formed on the surface of the P-type silicon substrate 301 forming the element forming region 303b. Electrode 31
N-type source / drain region 313b
Is provided. A first N-channel MOS transistor forming a memory cell includes a gate oxide film 309, a word line 311a, and N-type source / drain regions 313a, and a second N-channel MOS forming a peripheral circuit.
The S transistor has a gate oxide film 309 and a gate electrode 31
1b and an N-type source / drain region 313b. The gate length of the first N-channel MOS transistor is set shorter than the gate length of the second N-channel MOS transistor, and the gate width of the first N-channel MOS transistor is smaller than the gate width of the second N-channel MOS transistor. Is set.

[0008] The surface of the P-type silicon substrate 301 including the first and second N-channel MOS transistors and the field insulating film 307 is covered with an interlayer insulating film 315. In the interlayer insulating film 315, (the first N-channel MO
N-type source / drain region 313a (of S transistor)
, A contact hole 318 reaching the other of the N-type source / drain regions 313a and a contact hole 319 reaching the N-type source / drain region 313b (of the second N-channel MOS transistor). Is provided. Interlayer insulating film 3
Although not shown, a bit line, a capacitor, and the like are provided on the surface or on the surface of 15.

Due to the above structure, for example, in the first MOS transistor, the word line 311 in the element forming region 303a is formed.
An electric field concentration occurs at a channel edge portion immediately below a, and a current also flows through this portion. This portion effectively V _t is lower than the central portion of the channel in this first
S value of the N-channel MOS transistor becomes smaller.
The first N-channel MOS transistor constituting the memory cell utilizes this phenomenon.

[0010]

Is large S value of N-channel MOS transistors constituting a memory cell of DRAM [0006], forced with Oki Do N-channel MOS transistor of the V _t in order to reduce the leakage current in the sub-threshold region It was completed. In this case, the access speed of the memory cell decreases. This point can be solved by employing the edge operation type N-channel MOS transistor described in the above-mentioned patent publication.

[0011] In order to increase the operating speed of the peripheral circuit, the current drive function of the MOS transistor constituting the peripheral circuit is emphasized. Therefore, the impurity concentration of the element forming region that is to be the peripheral circuit region is set to a lower value than the impurity concentration of the element region that is to be the cell array region. However, when a peripheral circuit is constituted by edge operation type MOS transistors, even if the MOS transistor has a wide channel width, the on-state current decreases, and as a result, the operation speed of the peripheral circuit decreases.

[0012] With reference to FIG. 16 is a graph schematically showing the I _D -V _G characteristics, explaining the reason.

Edge operation type MOS constituting a peripheral circuit
I _D -V _G characteristics of the channel central portion of the transistor is as a solid line. This I _D -V _G characteristic is (V _{t of the} same value
This is the same as the I _D -V _G characteristic of the non-edge operation type MOS transistor (set in (1)). I _D -V _G characteristics of the channel edge portion of the edge operation type MOS transistor constituting a peripheral circuit is as shown in broken line, V in effective V _t is the channel central portion initially set at this portion Even lower than _t . Edge operation type M constituting peripheral circuit
The leakage current of the sub-threshold region at the channel edge of the OS transistor is larger than the leakage current of the sub-threshold region at the center of the channel of the MOS transistor. Therefore, in the sub-threshold region, in order to ensure the MOS transistor equal to the leakage current of the non-edge-operation with edge operation type MOS transistor, the I _D -V _G characteristics of the channel edge portion and central portion of the channel In FIG. 16, it must be shifted to the right. As a result, the ON current decreases. That is, the edge operation type MOS transistor described in the above-mentioned patent publication is preferable for a MOS transistor in which a potential transfer function is more important than a current drive function like a transfer transistor, but a MOS transistor in which a current drive function is important. This is not preferable for transistors.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device capable of increasing the access speed of a MOS transistor serving as a transfer transistor and suppressing a decrease in the operating speed of a MOS transistor in which a current driving function is important, and a method of manufacturing the same. And to provide a method.

[0015]

A feature of the semiconductor device according to the present invention is that an element formation region provided on the surface of a P-type silicon substrate is surrounded by a groove formed on the surface of the P-type silicon substrate. The first field insulating film is filled with a first field insulating film and a second field insulating film, and the upper surface of the first field insulating film is provided at a position lower than the surface of the P-type silicon substrate by a required height. An upper surface of the insulating film is provided at a position higher than an upper surface of the first field insulating film, and a first gate electrode and a first gate oxide film are provided in the element formation region sandwiched between the first field insulating films. A first N-channel MOS transistor having a first N-type source / drain region; and a second gate electrode in the element formation region sandwiched by the second field insulating film. , The second gate oxide film and the second
In this embodiment, a second N-channel MOS transistor having the N-type source / drain region is provided.

Preferably, the first and second gate electrodes are formed on the first and second N ⁺ -type polycrystalline silicon film patterns having the same thickness, respectively, by the first and second high melting points having the same thickness. A metal silicide film pattern is laminated, the first and second gate oxide films have the same thickness, and the first and second N-type source / drain regions have the same junction depth. Alternatively, the first and second gate electrodes are formed by forming first and second refractory metal silicide film patterns having the same thickness on the P ⁺ -type polycrystalline silicon film pattern and the N ⁺ -type polycrystalline silicon film pattern, respectively. The first and second gate oxide films have the same thickness, and the first and second N oxide films are stacked.
The junction depths of the mold source / drain regions are equal. Alternatively, the first and second gate electrodes are formed by forming first and second refractory metal silicide film patterns of the same thickness on first and second N ⁺ -type polycrystalline silicon film patterns of the same thickness. Are stacked, the first gate oxide film is thicker than the second gate oxide film, and the junction depths of the first and second N-type source / drain regions are equal. Has become.

In a first preferred embodiment of the semiconductor device of the present invention, a first element formation region which is regularly arranged is provided in a cell array region on the surface of a P-type silicon substrate.
A second element formation region is provided in a peripheral circuit region on the surface of the p-type silicon substrate; these first and second element formation regions are respectively surrounded by grooves provided on the surface of the p-type silicon substrate; The trenches surrounding the first and second element formation regions, respectively, are filled with first and second field insulating films, respectively, and the upper surface of the first field insulating film is more required than the surface of the P-type silicon substrate. , The upper surface of the second field insulating film is provided at a position higher than the upper surface of the first field insulating film, and the first element interposed between the first field insulating films. A first N-channel MOS having a first gate electrode also serving as a word line, a first gate oxide film, and a first N-type source / drain region in a formation region
Transistors are provided and these first N-type sources
One of the drain regions is connected to a bit line, the other of the first N-type source / drain regions is connected to a capacitor, and the first N-channel MOS transistor and the capacitor are used to store a DRAM memory. A cell is formed, and a second gate electrode, a second gate oxide film, and a second N-type source / drain region are provided in the element formation region sandwiched between the second field insulating films. 2
And a peripheral circuit including these second N-channel MOS transistors.

According to a second preferred aspect of the semiconductor device of the present invention, a pair of element forming regions is provided in each of the regions on the surface of the P-type silicon substrate where the SRAM memory cells are formed. Is surrounded by a groove formed on the surface of the P-type silicon substrate, the groove is filled with a first field insulating film and a second field insulating film, and the upper surface of the first field insulating film is The upper surface of these second field insulating films is provided at a position lower than the upper surface of these first field insulating films by a predetermined height below the surface of the mold silicon substrate. First and second N-channel MOS transistors are provided in the regions, respectively, and the first N-channel MOS transistor is sandwiched between the first field insulating films. These first N-channel MOS transistors are provided in a part of the element formation region, and these first N-channel MOS transistors have a first gate electrode also serving as a word line, a first gate oxide film, a first N-type source / drain region, One of these first N-type source / drain regions is connected to a bit line, and the other of these first N-type source / drain regions is connected to a resistive load element. A channel MOS transistor is provided in the element formation region at a portion sandwiched between the second field insulating films. These second N-channel MOS transistors include a second gate electrode, a second gate oxide film and a second gate oxide film. One of these second N-type source / drain regions comprises the other of the first N-type source / drain regions, and the second N-type source / drain region The other of the source / drain regions is connected to a ground wiring, and the other of the first N-type source / drain regions provided in one of the paired element formation regions is connected to the other of the paired element formation regions. It is characterized in that it is connected to the second gate electrode of the second N-channel MOS transistor provided on the other side.

According to a first aspect of the method of manufacturing a semiconductor device of the present invention, a pad oxide film and a silicon nitride film are formed on a surface of a P-type silicon substrate, and a first photoresist film pattern covering an element formation region is formed. Etching the silicon nitride film and the pad oxide film using the mask as a mask, further etching the P-type silicon substrate to form a groove in the surface of the P-type silicon substrate; Forming a film, chemically mechanically polishing the insulating film until the upper surface of the silicon nitride film is exposed to form a field insulating film filling the trench, and using the second photoresist film pattern as a mask. The field insulating film is etched to a desired thickness to form a second photo
Forming a first field insulating film in a portion not covered by the resist film pattern and leaving a second field insulating film in a portion covered by the second photo-resist film pattern; Etching the silicon film, removing the pad oxide film by etching, and removing the upper surface of the first field insulating film by the P
Forming a gate oxide film in the element formation region by thermal oxidation; forming an N ⁺ -type polycrystalline silicon film over the entire surface; A high melting point metal silicide film is formed, and the high melting point metal silicide film and the N ⁺ -type polycrystalline silicon film are patterned by using the third photoresist film pattern as a mask. A first gate electrode is formed in the element formation region, and a second gate electrode is formed in the element formation region sandwiched by the first field insulating film.
Forming an N-type source / drain region on the surface of the element formation region using the first and second gate electrodes as a mask.

According to a second aspect of the method of manufacturing a semiconductor device of the present invention, a pad oxide film and a silicon nitride film are formed on a surface of a P-type silicon substrate, and a first photoresist film pattern covering an element formation region is formed. Etching the silicon nitride film and the pad oxide film using the mask as a mask, further etching the P-type silicon substrate to form a groove in the surface of the P-type silicon substrate; Forming a film, chemically mechanically polishing the insulating film until the upper surface of the silicon nitride film is exposed to form a field insulating film filling the groove, and using the second photoresist film pattern as a mask. The field insulating film is etched to a desired thickness to form a second photo
Forming a first field insulating film in a portion not covered by the resist film pattern and leaving a second field insulating film in a portion covered by the second photo-resist film pattern; Etching the silicon film, removing the pad oxide film by etching, and removing the upper surface of the first field insulating film by the P
Forming a gate oxide film in the element formation region by thermal oxidation, a step of lowering the surface by a required height from the surface of the type silicon substrate, and a step of forming an N ⁺ type N ⁺ Forming a film, and ion-implanting a P-type impurity using a third photo-resist film pattern covering the element formation region sandwiched between the second field insulating films as a mask. A step of converting the N ⁺ -type polycrystalline silicon film on the element formation region sandwiched between the field insulating films into a P ⁺ -type polycrystalline silicon film, and forming a refractory metal silicide film on the entire surface; resist film pattern are sequentially patterned by a mask and the refractory metal silicide film and the N ⁺ -type polycrystalline silicon film and the P ⁺ -type polycrystalline silicon film on sandwiched the first field insulating film The element forming region to form a first gate electrode made of a refractory metal polycide film comprising the P ⁺ -type polycrystalline silicon film, above the element formation region sandwiched between the second field insulating film this Forming a second gate electrode made of a refractory metal polycide film containing an N ⁺ -type polycrystalline silicon film;
Forming an N-type source / drain region on the surface of the element formation region using the gate electrode as a mask.

According to a third aspect of the method of manufacturing a semiconductor device of the present invention, a pad oxide film and a silicon nitride film are formed on a surface of a P-type silicon substrate, and a first photoresist film pattern covering an element formation region is formed. Etching the silicon nitride film and the pad oxide film using the mask as a mask, further etching the P-type silicon substrate to form a groove in the surface of the P-type silicon substrate; Forming a film, chemically mechanically polishing the insulating film until the upper surface of the silicon nitride film is exposed to form a field insulating film filling the groove, and using the second photoresist film pattern as a mask. The field insulating film is etched to a desired thickness to form a second photo-
Forming a first field insulating film in a portion not covered by the resist film pattern and leaving a second field insulating film in a portion covered by the second photo-resist film pattern; Etching the silicon film, removing the pad oxide film by etching, and removing the upper surface of the first field insulating film by the P
Forming a silicon oxide film in the element formation region by thermal oxidation to cover the element formation region sandwiched by the first field insulating film; Removing the silicon oxide film using the photo-resist film pattern of No. 3 as a mask, and leaving the silicon oxide film in an element formation region sandwiched by the first field insulating film; Forming a first gate oxide film in the element formation region interposed between the first and second field insulating films; and forming a first gate oxide film in the element formation region interposed between the second field insulation films and having a smaller thickness than the first gate oxide film. forming a second gate oxide film, is formed on the entire surface N ⁺ -type polycrystalline silicon film, further, to form a refractory metal silicide film, this was the fourth photoresist film pattern as a mask Patterning the refractory metal silicide film and the N ⁺ -type polycrystalline silicon film above to the element formation region sandwiched between the first field insulating film to form a first gate electrode, in the first field insulating film Forming a second gate electrode in the element formation region sandwiched therebetween, and forming N-type source / drain regions on the surface of the element formation region using the first and second gate electrodes as a mask; It is characterized by including.

[0022]

Next, the present invention will be described with reference to the drawings.

FIG. 1A is a schematic plan view of a semiconductor device.
1 (b), FIG. 1 (c) and FIG. 1 (d), which are schematic cross-sectional views taken along lines AA, BB and CC in FIG. In the semiconductor device according to the first embodiment of the present invention, the N-channel MOS transistors constituting the memory cell and the peripheral circuit are constituted by edge-operation type and non-edge-operation N-channel MOS transistors, respectively. The thickness of the gate oxide film is the same, and the configuration of the gate electrode is the same. In FIG. 1A, for easy understanding, a portion of the (first) field insulating film in the cell array region is hatched by a dotted line on the lower left.

In a cell array region on the surface of the P-type silicon substrate 101, T-shaped element forming regions 1 which are regularly arranged are arranged.
In the peripheral circuit region on the surface of the P-type silicon substrate 101, an element formation region 103ab and the like are provided. The impurity concentration in the vicinity of the surface of the element formation regions 103aa and 103ab is, for example, about 5 × 10 ¹⁷ cm ⁻³ , 3
It is about × 10 ¹⁷ cm ⁻³ . The element formation region 103aa,
A groove 105 having a depth of about 250 nm is provided on the surface of the P-type silicon substrate 101 surrounding the 103ab, and the grooves 105 around the element forming regions 103aa and 103ab are formed of field insulating films 107aa and 107a made of a silicon oxide film.
7ab. Field insulating film 107
The upper surface of aa is lower than the surface of the P-type silicon substrate 101 by, for example, about 80 nm.
What is necessary is just a range of 100 nm. Outside this range, the effect of the edge operation type in the N-channel MOS transistor is weakened. Field insulating film 10
The upper surface of 7ab is, for example, higher than the surface of the P-type silicon substrate 101, but may be set at a position higher than a position about 25 nm lower than the surface of the P-type silicon substrate 101. The side surface of the groove 105 exposed on the field insulating film 107aa and the element forming regions 103aa, 103aa
The surface of the P-type silicon substrate 101 forming 3ab is 7n
A gate oxide film 109 having a thickness of about m is provided.

In the memory cell region, the gate oxide film 109
The word line 111aa also serving as a gate electrode is connected to the P-type silicon substrate 1
01) on the surface. In the peripheral circuit region, the gate electrode 111ab is connected via the gate oxide film 109 to the element formation region 103ab (the P-type silicon substrate 10ab).
It crosses on the surface of 1). The gate electrode 111ab extends on the upper surface of the field insulating film 107. The word line 111aa is an N ⁺ type polysilicon film pattern 13
7aa is a tungsten silicide film pattern 139a
The gate electrode 111ab is formed by stacking a tungsten silicide film pattern 139ab on an N ⁺ type polycrystalline silicon film pattern 137ab.

On the surface of the P-type silicon substrate 101 forming the element formation region 103aa, N-type source / drain regions 113aa are provided in self-alignment with the word lines 111aa.
P-type silicon substrate 101 forming element formation region 103ab
Are provided with N-type source / drain regions 113ab in a self-aligned manner with the gate electrode 111ab. Although the N-type source / drain region 113aa may be composed of only the N ⁻ -type diffusion layer, the N-type source / drain region 113ab is preferably a diffusion layer having an LDD structure. The first N-channel MOS transistor forming the memory cell includes a gate oxide film 109, a word line 111aa and an N-type source / drain region 113aa, and the second N-channel MOS transistor forming a peripheral circuit is a gate oxide film 109. , A gate electrode 111ab and an N-type source / drain region 113ab. N-channel MO (by word line 111aa)
The channel length and channel width of the S transistor are 0.2 μm.
m and 0.2 μm. The channel length and channel width of the second N-channel MOS transistor (by the gate electrode 111ab) are set to, for example, about 0.3 μm and about 10 μm.

The surface of the P-type silicon substrate 101 including the first and second N-channel MOS transistors and the field insulating films 107aa and 107ab is
5. (1st interlayer insulating film 115)
A bit contact hole 117 reaching one of the N-type source / drain regions 113aa, a node contact hole 118 reaching the other of the N-type source / drain regions 113aa, and a (second N-type MOS transistor).
A contact hole 119 reaching the N-type source / drain region 113ab (of the channel MOS transistor) is provided. Although not shown, a bit line, a capacitor, and the like are provided on the surface or on the surface of the interlayer insulating film 115.

According to the first example of the first embodiment, the first MOS transistor forming the memory cell has the electric field concentration at the channel edge portion of the element formation region 103aa just below the word line 111aa. occur becomes a current flows in this portion, setting a low V _t S value becomes smaller. As a result, when the first MOS transistor is used, when V _G = 0 V, V _t can be reduced while keeping _ID low, so that the access speed to the memory cell is increased. On the other hand, since the second N-channel MOS transistor constituting the peripheral circuit is of the non-edge operation type, the increase in the leakage current (of _ID ) in the subthreshold region does not occur in the case of the edge operation type. Become. For this reason, it is difficult for the second N-channel MOS transistor to reduce the on-current, and the operation speed of the N-channel MOS transistor is prevented from being reduced.

FIG. 2 is a schematic cross-sectional view of the manufacturing process of the semiconductor device, and FIG. 2 is a schematic cross-sectional view of the manufacturing process along the line AA in FIG.
FIG. 3 is a schematic cross-sectional view of a manufacturing process along the line BB in FIG. 1A, and FIG.
FIG. 4 is a schematic cross-sectional view of a manufacturing process using the CC line in FIG.
An example of the manufacturing method of the first embodiment of the first embodiment will be described with reference to FIG.

First, a pad oxide film 131 covering the surface of a P-type silicon substrate 101 and having a thickness of about 10 nm,
A silicon nitride film 132 of about nm is formed. Using the first photoresist pattern (not shown) as a mask, the silicon nitride film 132, the pad oxide film 131 and the P-type silicon substrate 101 are sequentially etched to form the (first) element formation region 103aa and ( A groove 105 surrounding the (second) element formation region 103ab is formed. The depth of the groove 105 is about 250 nm. A silicon oxide film is formed on the entire surface, and the silicon oxide film is subjected to chemical mechanical polishing until the upper surface of the silicon nitride film 132 is exposed, thereby forming a field insulating film 107a filling the trench 105 [FIG. ), FIGS. 3A and 4A].

Next, the field insulating film 107a is etched by using the (second) photoresist film pattern 135 covering the peripheral circuit region and having an opening in the cell array region as a mask to form a groove 105 in the cell array region. A (first) field insulating film 107aa to be filled is formed,
A (second) field insulating film 107ab filling the trench 105 in the peripheral circuit region is formed. The upper surface of the field insulating film 107aa is, for example, a P-type silicon substrate 101
About 30 nm below the surface. An exposed portion is formed on the side surface of the groove 105 in the cell array region [FIGS. 2B, 3B, and 4B].

Next, a sacrificial oxide film 133 having a thickness of about 20 nm is formed on the exposed portion on the side surface of the groove 105 by thermal oxidation. The silicon nitride film 132 is removed by wet etching. The purpose of forming the sacrificial oxide film 133 is to form the silicon nitride film 1 without the exposed portion of the groove 105.
This is to remove 32. For example, if the upper surface of the field insulating film 107aa is located higher than the surface of the P-type silicon substrate 101, the formation of the sacrificial oxide film 133 becomes unnecessary. Finally, the element formation regions 103aa, 1
The impurity concentration near the surface of 03ab is, for example, 5 × 10 ¹⁷ c
Boron ion implantation (channel doping) is performed into at least the element forming region 103aa so as to have an implantation energy of, for example, about 30 keV so as to be about m ^{−3 and} about 3 × 10 ¹⁷ cm ⁻³ [FIG. 3 (c) and 4 (c)].

Next, the pad oxide film 131 and the sacrificial oxide film 133 are removed by wet etching.
At this stage, the upper surface of the field insulating film 107aa is, for example, at a position about 80 nm lower than the surface of the P-type silicon substrate 101, and the upper surface of the field insulating film 107ab is at a position about 60 nm higher than the surface of the P-type silicon substrate 101. A gate oxide film 1 having a thickness of about 7 nm is formed by thermal oxidation.
09, the exposed portion of the surface of the P-type silicon substrate 101 forming the element formation region 103aa and the side surface of the groove 105 surrounding the element formation region 103aa;
It is formed on the surface of the P-type silicon substrate 101 forming the ab.

When the semiconductor device according to the first embodiment is manufactured, the processes from the field insulating film 107a in FIG. 4A to the formation of the field insulating films 107aa and 107ab in FIG. The process is
It is not limited to the above. For example, if immediately after the field insulating film 107a is formed, the groove 105
Is not formed, the silicon nitride film 132 can be removed without forming the sacrificial oxide film 133. For example, if the field insulating film 107a is thinned by, for example, about 50 nm by wet etching after the field insulating film 107a is formed, FIG.
The thickness of the field insulating film 107a for forming the field insulating film 107aa in FIG. 4B is reduced to some extent, and the height of the upper surface of the field insulating film 107ab in FIG. A value close to that of the surface 101 can also be used.

Subsequently, 100% of N ⁺ type is formed on the entire surface at the film forming stage.
An N ⁺ type polycrystalline silicon film (not shown in the figure) having a thickness of about nm is formed, and a tungsten silicide film (not shown in the figure) having a thickness of about 150 nm is formed on the entire surface. Using a third photoresist film pattern (not shown) as a mask, a tungsten silicide film, N ⁺
P-type polycrystalline silicon film is sequentially patterned to form an element forming region 103aa via a gate oxide film 109.
Line 111aa (which is the first gate electrode) crossing over the surface of the silicon substrate 101 and the gate oxide film 1
A (second) gate electrode 111ab crossing over the surface of the P-type silicon substrate 101 forming the element formation region 103ab through the gate electrode 09 is formed. Word line 111aa is N ⁺
A tungsten silicide film pattern 139aa is laminated on the polycrystalline silicon film pattern 137aa, and a gate electrode 111ab is formed on the N ⁺ polycrystalline silicon film pattern 137ab by the tungsten silicide film pattern 13.
9ab are laminated.

Next, using the word line 111aa and the gate electrode 111ab as a mask, ion implantation of an N-type impurity of about 1 × 10 ¹³ cm ⁻² is performed, and the element formation region 10 is formed.
An N-type source / drain region 113aa is formed on the surface of the P-type silicon substrate 101 forming the 3aa, and an N ^- type diffusion layer (not explicitly shown) is formed on the surface of the P-type silicon substrate 101 forming the element forming region 103ab. Is formed. After an insulating film spacer (not shown) is formed on the side surface of the gate electrode 111ab, ion implantation of an N-type impurity on the order of 10 ¹⁵ cm ⁻² is performed on the surface of the P-type silicon substrate 101 forming the element forming region 103ab. These element forming regions 103a
An N-type source is formed on the surface of the P-type silicon
Drain region 113ab is formed.

After the interlayer insulating film 115 is formed on the entire surface,
N-type source / drain regions 113 are formed in the interlayer insulating film 115.
A bit contact hole 117 reaching one side of aa is formed. After a bit line (not shown) and the like are formed on the surface of interlayer insulating film 115, a second interlayer insulating film (not shown) is formed on the entire surface. N-type source / drain region 113a penetrating through second interlayer insulating film and interlayer insulating film 115
a of the node contact hole 118 reaching the other of the
And a contact hole 119 penetrating through the interlayer insulating film and the interlayer insulating film 115 to reach the N-type source / drain regions 113ab and the like. On the surface of the second interlayer insulating film, a capacitance element, wiring for peripheral circuits, and the like are formed, and a DRAM employing the first embodiment is formed (FIG. 1).

FIG. 5A is a schematic plan view of a semiconductor device.
5 (b), FIG. 5 (c) and FIG. 5 (d), which are schematic cross-sectional views taken along line AA, BB and CC of FIG. 5 (a). In the semiconductor device according to the second example of the embodiment, the N-channel MOS transistors constituting the memory cell and the peripheral circuit are respectively composed of edge operation type and non-edge operation type N-channel MOS transistors. The difference between the second embodiment and the first embodiment lies in the configuration of the gate electrode of the N-channel MOS transistor constituting the memo cell. Also in the second embodiment, for easy understanding, in FIG. 5A, the (first) field insulating film portion in the cell array region is hatched by a dotted line on the lower left.

In the cell array region on the surface of the P-type silicon substrate 101, T-shaped element forming regions 1 which are regularly arranged are arranged.
In the peripheral circuit region on the surface of the P-type silicon substrate 101, an element forming region 103bb and the like are provided. A groove 105 having a depth of about 250 nm is provided on the surface of the P-type silicon substrate 101 surrounding the element formation regions 103ba and 103bb.
The trench 105 around 103bb is filled with field insulating films 107ba and 107bb made of a silicon oxide film. The upper surface of the field insulating film 107ba is also lower than the surface of the P-type silicon substrate 101 by, for example, about 80 nm (however, this height may be in the range of 25 nm to 100 nm). The upper surface of the field insulating film 107bb is also higher than, for example, the surface of the P-type silicon substrate 101 (but 25 nm higher than the surface of the P-type silicon substrate 101).
It is only necessary to set a higher position than a lower position).
Groove 1 in a portion exposed on field insulating film 107ba
A gate oxide film 109 having a thickness of about 7 nm is provided on the side surface of the substrate 05 and the surface of the P-type silicon substrate 101 forming the element forming regions 103ba and 103bb.

In the memory cell region, the gate oxide film 109
And the word line 111ba also serving as a gate electrode is connected to the P-type silicon substrate 1
01) on the surface. In the peripheral circuit region, the gate electrode 111bb is connected to the P-type silicon substrate 10
It crosses on the surface of 1). Gate electrode 111bb extends on the upper surface of field insulating film 107. The word line 111ba is a P ⁺ type polysilicon film pattern 13
8, a tungsten silicide film pattern 139ba is stacked, and a gate electrode 111bb is formed by stacking a tungsten silicide film pattern 139bb on an N ⁺ type polycrystalline silicon film pattern 137b. Each of the N ⁺ type polysilicon film pattern 137b and the P ⁺ type polysilicon film pattern 138 has a thickness of about 100 nm, and the tungsten silicide film pattern 139ba,
The thickness of 139bb is about 150 nm. The impurity concentration of the N ⁺ type polycrystalline silicon film pattern 137b is 1 × 10
²⁰ cm is about ^-2, the impurity concentration of the P + -type polycrystalline silicon film pattern 138 is 2 × 10 ²⁰ cm ^-2, for example, about.

On the surface of the P-type silicon substrate 101 forming the element formation region 103ba, N-type source / drain regions 113ba are provided in a self-aligned manner with the word lines 111ba.
P-type silicon substrate 101 forming element formation region 103bb
Are provided with N-type source / drain regions 113bb in self alignment with the gate electrode 111bb. N-type source / drain region 113ba is composed of only an N ⁻ -type diffusion layer, and N-type source / drain region 113bb is L-type.
It is composed of a diffusion layer having a DD structure. The first part of the memory cell
N channel MOS transistor has a gate oxide film 10
9, a second N-channel MOS transistor comprising a word line 111ba and an N-type source / drain region 113ba and constituting a peripheral circuit comprises a gate oxide film 109,
It comprises a gate electrode 111bb and N-type source / drain regions 113bb. First N-channel MO
The channel length and channel width of the S transistor are 0.2 μm
The second N-channel MOS
The channel length and channel width of the transistor are, for example, 0.3
It is about 10 μm.

The surface of the P-type silicon substrate 101 including the first and second N-channel MOS transistors and the field insulating films 107ba and 107bb is an interlayer insulating film 11
5. (1st interlayer insulating film 115)
Bit contact hole 117 reaching one of N-type source / drain regions 113ba, node contact hole 118 reaching the other of N-type source / drain regions 113ba, and (second N
A contact hole 119 reaching the N-type source / drain region 113bb (of the channel MOS transistor) is provided. Although not shown, a bit line, a capacitor, and the like are provided on the surface or on the surface of the interlayer insulating film 115.

The semiconductor device according to the second embodiment of the first embodiment has the same effects as those of the semiconductor device according to the first embodiment of the first embodiment. Book first
The first MOS transistor forming the memory cell according to the second embodiment of the present embodiment also has an element formation region 103.
electric field concentration occurs in the channel edge portion immediately under the word line 111ba of ba to become current also flows in this portion, it is possible to set a low S value can be set lower V _t. Therefore, this first MOS
The use of the transistor increases the access speed to the memory cell. Second N-channel MO constituting peripheral circuit
The S transistor is a non-edge operation type. No increase in leak current occurs in the sub-threshold region due to the edge operation. Therefore, it is difficult to reduce the on-current, and the operation speed of the N-channel MOS transistor is prevented from being reduced.

Further, the second embodiment has the following effects as compared with the first embodiment. Although the word line 111aa in the first embodiment includes the N ⁺ -type polycrystalline silicon film pattern 137aa, the gate electrode of the first N-channel MOS transistor constituting the memory cell according to the second embodiment is changed. The word line 111ba is (N ⁺
P ⁺ type polycrystalline silicon film pattern 138 having a larger work function than that of the type polycrystalline silicon film, so that Vt of the first N-channel MOS transistor in the first embodiment and the second embodiment is increased. When set to the same value (compared to the impurity concentration of the element formation region 103aa)
The impurity concentration of the element formation region 103ba can be set low. As a result, the S value of the first N-channel MOS transistor can be made lower in the second embodiment than in the first embodiment, and the access speed to the memory cell can be reduced in the second embodiment. The example is even faster.

The method of manufacturing the semiconductor device according to the second embodiment of the first embodiment is basically the same as that of the first embodiment except for the manufacturing steps related to the word line 111ba and the gate electrode 111bb. Is the same as the method of manufacturing a semiconductor device according to the first embodiment. The outline of the method of manufacturing the semiconductor device according to the second embodiment is as follows.

First, a pad oxide film and a silicon nitride film covering the surface of the P-type silicon substrate 101 are formed in the same manner as in the manufacturing method of the first embodiment. Using the first photoresist film pattern as a mask, the silicon nitride film, the pad oxide film, and the P-type silicon substrate are sequentially etched to form the (first) element formation region 103ba and the (second)
A groove 105 surrounding the element formation region 103bb is formed. A silicon oxide film is formed on the entire surface, and the silicon oxide film is subjected to chemical mechanical polishing to form a field insulating film filling the trench 105. The field insulating film is etched using the second photoresist film pattern having an opening in the cell array region as a mask to cover the peripheral circuit region and fill the groove 105 in the cell array region (first). A film 107ba is formed, and a (second) field insulating film 107bb filling the groove 105 in the cell array region is formed. After the formation of the sacrificial oxide film and the removal of the silicon nitride film on the exposed portion on the side surface of the groove 105, the device formation region 103b is finally formed.
At least the element forming region 103ba is channel-doped with boron or the like so that the impurity concentration in the vicinity of the surfaces of a and 103bb becomes a required value. After the pad oxide film and the sacrificial oxide film are removed, the gate oxide film 10 is removed.
9 is formed.

Subsequently, an N ⁺ -type polycrystalline silicon film having a thickness of about 100 nm and an impurity concentration of about 1 × 10 ²⁰ cm ⁻² is formed at the film formation stage on the entire surface. An opening is formed over the element formation region 103ba, and the element formation region 103b
b using the third photoresist film covering
5 × 10 ¹⁶ cm ^-2 of boron (or BF ₂ )
The ions are implanted at about eV (or about 30 keV). The N ⁺ -type polycrystalline silicon film covering the element formation region 103ba is converted into a P ⁺ -type polycrystalline silicon film as a result. Tungsten with a thickness of about 150 nm
A silicide film is formed. Thereafter, using the fourth photo-resist film pattern as a mask, the tungsten silicide film, the P ⁺ -type polycrystalline silicon film and the N ⁺ -type polycrystalline silicon film are sequentially patterned to form a gate oxide film 1.
09, a word line 111ba (which is a first gate electrode) traversing the surface of the P-type silicon substrate 101 forming the element forming region 103ba, and a P-type forming the element forming region 103bb via the gate oxide film 109. Silicon substrate 1
01 (second) gate electrode 111b crossing the surface of
b is formed. The word line 111ba is formed by stacking a tungsten silicide film pattern 139ba on a P ⁺ type polysilicon film pattern 138,
1bb is formed by stacking a tungsten silicide film pattern 139bb on an N ⁺ type polycrystalline silicon film pattern 137b.

Thereafter, the N-type source / drain regions 113ba, 113ba, 1ba are formed by the same manufacturing method as in the first embodiment.
13bb is formed, an interlayer insulating film 115 is formed, and further, a bit contact hole 117, a bit line, a second interlayer insulating film, a node contact hole 118, a contact hole 119, a capacitor, a wiring, and the like are formed. .

FIG. 6A which is a schematic plan view of a semiconductor device.
6 (b), FIG. 6 (c) and FIG. 6 (d), which are schematic cross-sectional views taken along lines AA, BB and CC in FIG. 6 (a). In the semiconductor device according to the third embodiment of the present invention, the N-channel MOS transistors constituting the memory cell and the peripheral circuit are respectively composed of edge operation type and non-edge operation type N-channel MOS transistors. The difference between the third embodiment and the first embodiment is that the thickness of the gate oxide film of the first N-channel MOS transistor (which constitutes the memo cell) is the second (which constitutes the peripheral circuit). The point is that it is thicker than the thickness of the gate oxide film of the N-channel MOS transistor. In the third embodiment as well, for easy understanding, the portion of the (first) field insulating film in the cell array region in FIG.

In the cell array region on the surface of the P-type silicon substrate 101, T-shaped element forming regions 1 which are regularly arranged are arranged.
In the peripheral circuit region on the surface of the P-type silicon substrate 101, an element formation region 103cb and the like are provided. A groove 105 having a depth of about 250 nm is provided on the surface of the P-type silicon substrate 101 surrounding the element forming regions 103ca and 103cb.
The trench 105 around 103 cb is filled with field insulating films 107 ca and 107 cb made of a silicon oxide film. The upper surface of the field insulating film 107ca is also lower than the surface of the P-type silicon substrate 101 by, for example, about 80 nm (however, this height may be in the range of 25 nm to 100 nm). The upper surface of the field insulating film 107cb is also higher than, for example, the surface of the P-type silicon substrate 101 (but 25 nm higher than the surface of the P-type silicon substrate 101).
It is only necessary to set a higher position than a lower position).

A gate oxide film 110 having a thickness of about 11 nm is provided on the surface of the P-type silicon substrate 101 forming the element forming region 103ca and the side surface of the groove 105 exposed on the field insulating film 107ca. A gate oxide film 109 having a thickness of about 6 nm is provided on the surface of the P-type silicon substrate 101 forming the element forming region 103cb.

In the memory cell region, the gate oxide film 110
The word line 111ca also serving as a gate electrode is connected to the P-type silicon substrate 1
01) on the surface. In the peripheral circuit region, the gate electrode 111cb is connected via the gate oxide film 109 to the element formation region 103cb (the P-type silicon substrate 10c).
It crosses on the surface of 1). The gate electrode 111cb extends on the upper surface of the field insulating film 107. The word line 111ca is an N ⁺ type polycrystalline silicon film pattern 13
Tungsten silicide film pattern 139c on 7ca
The gate electrode 111cb is formed by stacking a tungsten silicide film pattern 139cb on an N ⁺ type polycrystalline silicon film pattern 137cb. The film thickness of the N ⁺ type polycrystalline silicon film patterns 137ca and 137cb is about 100 nm, and the film thickness of the tungsten silicide film patterns 139ca and 139cb is about 150 nm.

On the surface of the P-type silicon substrate 101 forming the element forming region 103ca, N-type source / drain regions 113ca are provided in self-alignment with the word lines 111ca.
P-type silicon substrate 101 forming element formation region 103cb
Are provided with N-type source / drain regions 113cb in a self-aligned manner with the gate electrode 111cb. N-type source / drain region 113ca is composed of only an N ⁻ -type diffusion layer, and N-type source / drain region 113cb is
It is composed of a diffusion layer having a DD structure. The first part of the memory cell
N channel MOS transistor has a gate oxide film 10
9, a second N-channel MOS transistor comprising a word line 111ca and an N-type source / drain region 113ca, and constituting a peripheral circuit.
It comprises a gate electrode 111cb and N-type source / drain regions 113cb. First N-channel MO
The channel length and channel width of the S transistor are 0.2 μm
The second N-channel MOS
The channel length and channel width of the transistor are, for example, 0.3
It is about 10 μm.

The surface of the P-type silicon substrate 101, including the first and second N-channel MOS transistors and the field insulating films 107ca and 107cb, is
5. (1st interlayer insulating film 115)
A bit contact hole 117 reaching one of the N-type source / drain regions 113ca, a node contact hole 118 reaching the other of the N-type source / drain regions 113ca, and a second N-type MOS transistor.
A contact hole 119 and the like reaching the N-type source / drain region 113cb (of the channel MOS transistor) are provided. On the surface of the interlayer insulating film 115, although not shown, a bit line, a capacitor, and the like are provided.

The semiconductor device according to the third example of the first embodiment has the same effects as those of the semiconductor device according to the first example of the first embodiment. Book 3
In the first MOS transistor constituting the memory cell according to the third embodiment, unlike the first embodiment, the thickness of the gate oxide film 110 is increased, but the element formation region 103ca is formed.
By lowering the impurity concentration of the first MOS transistor, the S value can be made substantially the same as that of the first MOS transistor of the first embodiment. On the other hand, in the third embodiment, the gate oxide film 110 is formed.
Is provided, the third embodiment has a higher electrostatic breakdown resistance of the first MOS transistor than the first embodiment.

The method of manufacturing the semiconductor device according to the third embodiment of the first embodiment is different from that of the first embodiment in that the gate oxide films 109, 1
Except for the manufacturing process related to 10, the method is basically the same as the method of manufacturing the semiconductor device according to the first embodiment. The outline of the method of manufacturing the semiconductor device according to the third embodiment is as follows.

First, a pad oxide film and a silicon nitride film covering the surface of the P-type silicon substrate 101 are formed in the same manner as in the manufacturing method of the first embodiment. Using the first photoresist film pattern as a mask, the silicon nitride film, the pad oxide film and the P-type silicon substrate are sequentially etched to form the (first) element formation region 103ca and the (second)
A groove 105 surrounding the element formation region 103cb is formed. A silicon oxide film is formed on the entire surface, and the silicon oxide film is subjected to chemical mechanical polishing to form a field insulating film filling the trench 105. The field insulating film is etched using the second photoresist film pattern having an opening in the cell array region as a mask to cover the peripheral circuit region and fill the groove 105 in the cell array region (first). A film 107ca is formed, and a (second) field insulating film 107cb filling the trench 105 in the cell array region is formed. After the formation of the sacrificial oxide film and the removal of the silicon nitride film on the exposed portions on the side surfaces of the trench 105, the device formation region 103c is finally formed.
At least the element forming region 103ba is channel-doped with boron or the like so that the impurity concentration in the vicinity of the surface of each of a and 103cb becomes a required value.

Next, the pad oxide film and the sacrificial oxide film are removed. An exposed portion of the surface of the P-type silicon substrate 101 forming the element formation region 103ca and the side surface of the groove 105 surrounding the element formation region 103ca;
A silicon oxide film having a thickness of about 5 nm is formed by thermal oxidation on the surface of the P-type silicon substrate 101 forming b. The silicon oxide film is removed by etching using a third photoresist film having an opening above the element formation region 103cb and covering the element formation region 103ca as a mask. Further, thermal oxidation is performed, and the surface of P-type silicon substrate 101 forming element formation region 103ca and element formation region 10ca are formed.
A (first) gate oxide film 110 having a thickness of about 11 nm is formed on the exposed portion on the side surface of the groove 105 surrounding 3ca, and the P-type silicon substrate 1 forming an element formation region 103cb is formed.
A gate oxide film 109 having a thickness of about 6 nm is formed on the surface of the substrate 01.

Subsequently, an N ⁺ -type N ⁺ -type polycrystalline silicon film having a thickness of about 100 nm is formed on the entire surface at the film forming stage, and a tungsten film of a thickness of about 150 nm is formed on the entire surface. -A silicide film is formed. Then the fourth
The tungsten silicide film and the N ⁺ -type polycrystalline silicon film are sequentially patterned by using the photo resist film pattern as a mask, and on the surface of the P-type silicon substrate 101 forming the element formation region 103ca via the gate oxide film 110. Line 1 (which is the first gate electrode)
11ca and a (second) gate electrode 111cb crossing over the surface of the P-type silicon substrate 101 forming the element forming region 103cb via the gate oxide film 109 are formed. The word line 111ca is formed by stacking a tungsten silicide film pattern 139ca on an N ⁺ type polycrystalline silicon film pattern 137ca, and the gate electrode 111cb is
^A tungsten silicide film pattern 139cb is laminated on the ⁺ type polycrystalline silicon film pattern 137cb.
Thereafter, by the same manufacturing method as in the first embodiment,
N-type source / drain regions 113ba and 113bb are formed, an interlayer insulating film 115 is formed, and a bit contact hole 117, a bit line, a second interlayer insulating film,
A node contact hole 118, a contact hole 119, a capacitor, a wiring, and the like are formed.

In the first embodiment, the first MOS transistor of the edge operation type and the second MOS transistor of the non-edge operation type are formed in different element formation regions. The present invention is not limited to the first embodiment, and in the second embodiment of the present invention,
The first and second MOS transistors coexist in one element formation region.

FIG. 7 is a circuit diagram of an SRAM memory cell.
9A and FIG. 9B which are schematic cross-sectional views of the semiconductor device, FIG. 8 which is a schematic plan view of the semiconductor device, and FIG. ) And FIG. 9C, the semiconductor device according to the first example of the second embodiment of the present invention, as described below, has a transfer transistor of an SRAM memory cell, Each of the driver transistors includes a first N-channel MOS transistor of an edge operation type and a second N-channel MOS transistor of a non-edge operation type. In FIG. 8, for easy understanding, the portion of the first field insulating film is hatched by a dotted line on the lower left.

The S according to the first embodiment of the second embodiment
The memory cell of the RAM includes a pair of transfer transistors (Tr3, Tr4) each composed of a first N-channel MOS transistor of an edge operation type and a pair of cascade-coupled second N-channel MOS transistors of a non-edge operation type. Driver transistors (Tr1, T
r2), a pair of resistance load elements (R1, R2), a word line (WL) and a pair of bit lines (BL1, BL2). Connections other than the cascade connection are as follows. Word lines (WL) are Tr3, Tr4
One of the N-type source / drain regions of Tr3 and Tr4 is connected to BL1 and BL2, and one end of each of R1 and R2 is connected to a power supply line ( _Vcc ). The N-type source region is connected to a ground line. The N-type drain region of Tr1 is Tr3
And the other of the N-type source / drain regions is connected to the other end of R1. The N-type drain region of Tr2 is Tr4
And the other of the N-type source / drain regions is connected to the other end of R2.

The structure of the memory cell of the SRAM according to the first embodiment is as follows.

In the cell array region on the surface of the P-type silicon substrate 201, there are provided generally square-shaped device forming regions 203 which are regularly arranged. 2 in one memory cell
One element formation region 203 is included, and one element formation region 203 is shared by four memory cells. One element forming region 203 forming one memory cell has one first N-channel MOS transistor (Tr3) and one
Second N-channel MOS transistors (Tr1)
The other element forming region 203 is provided with one first N-channel MOS transistor (Tr4) and one second N-channel MOS transistor (Tr2). Tr3 in the element formation region 203
The impurity concentration near the surface serving as the channel region of (and Tr4) is, for example, about 4 × 10 ¹⁷ cm ⁻³ , and the impurity concentration near the surface serving as the channel region of Tr1 (and Tr2) in the element forming region 203 is, for example, 3 × 10 ¹⁷ c
m ⁻³ .

A groove 20 having a depth of about 250 nm is formed on the surface of the P-type silicon substrate 201 surrounding the element forming region 203.
5 are provided. Tr in the element forming region 203
The trench 205 around the channel region 3 (and Tr4) is made of a (first) field insulating film 2 made of a silicon oxide film.
07aa. The trench 205 around the channel region of Tr1 (and Tr2) in the element forming region 203 is filled with a (second) field insulating film 207ab made of a silicon oxide film. The upper surface of the field insulating film 207aa is lower than the surface of the P-type silicon substrate 201 by, for example, about 80 nm, but this lower level may be in the range of 25 nm to 100 nm. Outside this range, the effect of the edge operation type in Tr3 (and Tr4) is weakened. The upper surface of the field insulating film 207ab is, for example, a P-type silicon substrate 201
Of the P-type silicon substrate 201
It may be set at a position higher than a position lower by about 25 nm from the surface of. A gate oxide film 209 having a thickness of about 7 nm is provided on the side surface of the groove 205 exposed on the field insulating film 207aa and on the surface of the P-type silicon substrate 201 forming the element forming region 203.

A word line 211aa serving also as a gate electrode of Tr3 (or Tr4) is formed, via a gate oxide film 209, on a P-type silicon substrate forming a plurality of element forming regions 103aa (portion interposed between field insulating films 207aa). 2
01) on the surface. The gate electrode 211ab of Tr1 (Tr2) is connected to the gate electrode 211ab through the gate oxide film 209.
Crossing a portion of one (the other) element formation region 203 of one of the memory cells sandwiched between the field insulating films 207ab;
The field insulating film 20 traverses over the surface of the field insulating film 207ab and in the other (one) element formation region 203.
The portion extending between the portions 7ab extends over the element forming region 203 via the gate oxide film 209. Word line 2
11aa is an N ⁺ type polycrystalline silicon film pattern 237aa
The gate electrode 211ab is formed by laminating a tungsten silicide film pattern 239ab on an N ⁺ type polycrystalline silicon film pattern 237ab. The film thickness of the N ⁺ type polycrystalline silicon film patterns 237aa and 237ab is 10
The thickness of the tungsten silicide film patterns 239aa and 239ab is about 150 nm.

On the surface of the P-type silicon substrate 201 forming the element formation region 203, an N-type diffusion layer 213aa having an LDD structure is provided in a self-aligned manner only with the word line 211aa.
An N-type diffusion layer 213ab is provided in a self-aligned manner with the word line 211aa and the gate electrode 211ab.
An n-type diffusion layer 213ac is provided in a self-alignment only in 11ab. N-type diffusion layer 213aa and N-type diffusion layer 21
3 cc each is shared by two memorcells and N
The type diffusion layer 213ab is composed of Tr1 and Tr3 (or
Tr2 and Tr4). Tr3 (and Tr4) includes a gate oxide film 209, a word line 211aa (which is a first gate electrode), an N-type diffusion layer 213aa (which becomes a first N-type source / drain region), and an N-type diffusion layer. 213ab. Tr1
(And Tr2) are composed of the gate oxide film 209 and the (second
), And an N-type diffusion layer 213ab (which becomes the second N-type source / drain region) and an N-type diffusion layer 213ac. The channel length and channel width of Tr3 (and Tr4) are set to about 0.2 μm and about 0.2 μm, respectively.
2) The channel length and channel width are about 0.2 μm and 8 μm.
m.

Tr1 to Tr4 and field insulating film 2
07aa, 207ab, and the P-type silicon substrate 20
1 is covered with an interlayer insulating film 215. The interlayer insulating film 215 includes a bit contact hole 217 reaching the N-type diffusion layer 213aa, a node contact hole 218 reaching the N-type diffusion layer 213ab, and an N-type diffusion layer 213.
A ground contact hole 219 reaching ab is provided. The node contact hole 218 is a contact hole related to the cascade connection, and has a structure called a common contact hole. For example, Tr3 and T
The n-type diffusion layer 213ab shared by r1 and the gate electrode 211ab of Tr2 are
Connected through. Although not shown in FIGS. 8 and 9, the bit line (BL1, BL2) and the resistance load element (R) are formed on the surface of the interlayer insulating film 215 or on the surface.
1, R2), power supply wiring (V _cc ), ground wiring, and the like.

According to the first example of the second embodiment, the first MOS transistors (Tr3, Tr4) constituting the transfer transistor of the memory cell are located immediately below the word line 211aa in the element forming region 203aa. electric field concentration becomes a current in this part flows occur in the channel edge portion, setting a low V _t S value becomes smaller. As a result, even with a lower further V _t Lower the power supply voltage, by using this first MOS transistor, the access speed to the memory cell becomes faster, easier suppression of erroneous writing of information into the memory cell Become. Also, the second N which constitutes the driver transistor of the memory cell
Since channel MOS transistor (Tr1, Tr2) is a non-edge-operation, servants set the V _t corresponding to the reduction of the power source voltage to be lower, it will not occur an increase in leakage current in the sub-threshold region. For this reason, it is difficult to reduce the on-current in Tr1 and Tr2. Further, the synergistic effect of such advantages of Tr1 and Tr2 and the above advantages of Tr3 and Tr4 facilitates suppression of a decrease in stability of holding write information in a memory cell.

FIG. 1 is a schematic cross-sectional view of a manufacturing process of a semiconductor device, and is a schematic cross-sectional view of a manufacturing process along line AA in FIG.
FIG. 8 is a schematic cross-sectional view of a semiconductor device manufacturing process,
FIG. 11 is a schematic cross-sectional view of a manufacturing process along the line BB of FIG. 11, and FIG. 12 is a schematic cross-sectional view of a manufacturing process along the line CC of FIG. An example of the manufacturing method of the first example of the second embodiment will be described with reference to FIGS.

First, a pad oxide film 231 having a thickness of about 10 nm and a thickness of 100
A silicon nitride film 232 of about nm is formed. Using the first photoresist pattern (not shown) as a mask, the silicon nitride film 232, the pad oxide film 231 and the P-type silicon substrate 201 are sequentially etched to form a groove 205 surrounding the element formation region 203aa. You.
The depth of the groove 205 is about 250 nm. A silicon oxide film is formed on the entire surface, and the silicon oxide film is subjected to chemical mechanical polishing until the upper surface of the silicon nitride film 232 is exposed, thereby forming a field insulating film 207a filling the trench 205 [FIG. ), FIG. 11 (a), FIG.
(A)].

Next, at least a second N-channel MOS transistor (which becomes a driver transistor) (Tr
1, Tr2), and at least a first N-channel MO (to be a transfer transistor)
The field insulating film 207a is etched by using the (second) photoresist film pattern 235 having an opening in a region where the S transistor (Tr3, Tr4) is to be formed and having a belt-like shape as a mask, and the trench 205 is formed. (First) field insulating film 207aa is formed, and (second) field insulating film 207a filling trench 205 is formed.
b is formed remaining. The upper surface of the field insulating film 207aa is, for example, 30n from the surface of the P-type silicon substrate 201.
m lower. Also, an exposed portion is formed on the side surface of the groove 205 at a portion filled with the field insulating film 207aa [FIGS. 10B, 11B, and 12].
(B)].

Next, a sacrificial oxide film 233 having a thickness of about 20 nm is formed on the exposed portion on the side surface of the groove 205 by thermal oxidation. The silicon nitride film 232 is removed by wet etching. The purpose of forming the sacrificial oxide film 233 is to form the silicon nitride film 2 with no exposed portion of the groove 205.
This is to remove 32. For example, if the upper surface of the field insulating film 207aa is at a position higher than the surface of the P-type silicon substrate 201, the formation of the sacrificial oxide film 233 becomes unnecessary. Finally, the impurity concentration in the vicinity of the surface of the element forming region 203 at the portion where Tr3 (and Tr4) is formed becomes, for example, about 4 × 10 ¹⁷ cm ⁻³ , and Tr1
Element formation region 2 at the portion where (and Tr2) are formed
03 has an impurity concentration in the vicinity of the surface of, for example, 3 × 10 ¹⁷ cm ^−3.
At least Tr1 (and Tr2)
Boron ion implantation (channel doping) is performed, for example, in the portion of the element forming region 203 which is to be a region where the silicon is to be formed.
Implantation energy of about 0 keV is performed [FIG.
(C), FIG. 11 (c), FIG. 12 (c)].

Next, pad oxide film 231 and sacrificial oxide film 233 are removed by wet etching.
At this stage, the upper surface of the field insulating film 207aa is, for example, at a position about 80 nm lower than the surface of the P-type silicon substrate 201, and the upper surface of the field insulating film 207ab is at a position about 60 nm higher than the surface of the P-type silicon substrate 201. A gate oxide film 2 having a thickness of about 7 nm is formed by thermal oxidation.
09 is a P-type silicon substrate 2 forming an element forming region 203
01 and the exposed portions on the side surfaces of the groove 205.

In manufacturing the semiconductor device according to the first embodiment of the second embodiment, FIGS.
FIG. 11 is a diagram showing the field insulating film 207a in FIG.
Field insulating films 207aa and 207 in (c) and the like.
Manufacturing steps up to the formation of ab are not limited to the above. For example, immediately after the field insulating film 207a is formed, the silicon nitride film 232 can be removed without forming the sacrificial oxide film 233 because the exposed portion of the groove 205 is not formed. For example, after the field insulating film 207a is formed, the field insulating film 20
If the thickness of the field insulating film 7a is reduced by, for example, about 50 nm by wet etching, the field insulating film 207 for forming the field insulating film 207aa in FIG.
FIG.
The height of the upper surface of the field insulating film 207ab in (c) and the like can be set to a value close to the surface of the P-type silicon substrate 201.

Subsequently, 100% of N ⁺ type is formed on the entire surface at the film forming stage.
An N ⁺ type polycrystalline silicon film (not shown in the figure) having a thickness of about nm is formed, and a tungsten silicide film (not shown in the figure) having a thickness of about 150 nm is formed on the entire surface. Using a third photoresist film pattern (not shown) as a mask, a tungsten silicide film, N ⁺
The polycrystalline silicon film is sequentially patterned, and a word line 211aa (which is a first gate electrode) crossing over the surface of a P-type silicon substrate 201 forming an element forming region 203 via a gate oxide film 209, and a gate. Oxide film 109
P-type silicon substrate 2 forming element forming region 203 through
01 (second) gate electrode 211a crossing the surface of
b is formed. The word line 211aa is formed by stacking a tungsten silicide film pattern 239aa on an N ⁺ type polysilicon film pattern 237aa, and the gate electrode 211ab is formed by an N ⁺ type polysilicon film pattern 237a.
B is formed by stacking a tungsten silicide film pattern 239ab.

Next, using the word line 211aa and the gate electrode 211ab as a mask, ion implantation of a low dose N-type impurity is performed. An insulating film spacer (not shown) that covers the side surfaces of the word line 211aa and the gate electrode 211ab is formed. Further, ion implantation of a high dose of N-type impurities is performed, and N-type diffusion layers 213aa, 213ab, and 213ac having an LDD structure are formed on the surface of the P-type silicon substrate 201 forming the element forming region 203. .

After the interlayer insulating film 215 is formed on the entire surface,
A bit contact hole 217 reaching the N-type diffusion layer 213aa and an N-type diffusion layer 213ab are formed in the interlayer insulating film 215.
Is formed. After a bit line, a resistance load element (not shown) and the like are formed on the surface of the interlayer insulating film 215, a second interlayer insulating film (not shown) is formed on the entire surface. A ground contact hole 219 that penetrates the second interlayer insulating film and the interlayer insulating film 215 and reaches the N-type diffusion layer 213ac, and a contact that penetrates the second interlayer insulating film and reaches the above-described resistance load element and the like is formed. You. A power supply wiring, a ground wiring, and the like are formed on the surface of the second interlayer insulating film, and the SRA adopting the first embodiment is used.
M is formed [FIGS. 8 and 9].

FIG. 7 is a circuit diagram of an SRAM memory cell.
FIG. 13 is a schematic plan view of the semiconductor device, and FIG. 13 is a schematic cross-sectional view of the semiconductor device.
FIGS. 14A and 14B are schematic cross-sectional views taken along line C.
14 (c), in the semiconductor device according to the second example of the second embodiment of the present invention, the thickness of the gate oxide film of the transfer transistor is smaller than that of the driver transistor. The second embodiment is different from the first embodiment in that the thickness is larger than the thickness of the film. In FIG. 13 as well, the portion of the first field insulating film is hatched by a dotted line to the left in order to facilitate understanding.

The S according to the second embodiment of the present second embodiment
The connection of the memory cells of the RAM is the same as that of the first example of the second embodiment. S according to the second embodiment
The structure of the memory cell of the RAM is as follows.

In the cell array area on the surface of the P-type silicon substrate 201, there are provided generally square-shaped element forming areas 203 which are regularly arranged. 2 in one memory cell
One element formation region 203 is included, and one element formation region 203 is shared by four memory cells. One element forming region 203 forming one memory cell has one first N-channel MOS transistor (Tr3) and one
Second N-channel MOS transistors (Tr1)
The other element forming region 203 is provided with one first N-channel MOS transistor (Tr4) and one second N-channel MOS transistor (Tr2). Tr3 in the element formation region 203
(And Tr4) and the impurity concentration near the surface serving as the channel region and Tr1 (and T4) in the element forming region 203.
The impurity concentration near the surface serving as the channel region of r2) is Tr3 (and Tr3) in the first embodiment, respectively.
4), it is set to barrel the same as the V _t of Tr1 (and Tr2).

The groove 20 having a depth of about 250 nm is formed on the surface of the P-type silicon substrate 201 surrounding the element forming region 203.
5 are provided. Tr in the element forming region 203
The trench 205 around the channel region 3 (and Tr4) is made of a (first) field insulating film 2 made of a silicon oxide film.
07ba. The trench 205 around the channel region of Tr1 (and Tr2) in the element forming region 203 is filled with a (second) field insulating film 207bb made of a silicon oxide film. The upper surface of the field insulating film 207ba is, for example, about 80 nm lower than the surface of the P-type silicon substrate 201, but this lower level may be in the range of 25 nm to 100 nm. The upper surface of the field insulating film 207bb is higher than the surface of the P-type silicon substrate 201, for example, but may be set at a position higher than a position lower by about 25 nm than the surface of the P-type silicon substrate 201.

The side surface of the groove 205 exposed on the field insulating film 207ba and the field insulating film 207b
A gate oxide film 210 having a thickness of about 11 nm is provided on the surface of the P-type silicon substrate 201 which forms the element forming region 203 between the portions a. Field insulating film 2
P which forms the element forming region 203 at the portion sandwiched between
A gate oxide film 209 having a thickness of about 6 nm is provided on the surface of the mold silicon substrate 201.

The word line 211ba also serving as the gate electrode of Tr3 (or Tr4) is connected via the gate oxide film 210 to the P-type silicon substrate forming the plurality of element forming regions 103ba (partially sandwiched by the field insulating film 207ba). 2
01) on the surface. The gate electrode 211bb of Tr1 (Tr2) is connected to the gate electrode 211bb through the gate oxide film 209.
Traverses a portion of the one (the other) element formation region 203 of the two memory cells sandwiched between the field insulating films 207bb,
The field insulating film 20 crosses over the surface of the field insulating film 207bb and is in the other (one) element formation region 203.
7bb extends over the element formation region 203 via the gate oxide film 209. Word line 2
11ba is an N ⁺ type polycrystalline silicon film pattern 237ba
And a tungsten silicide film pattern 239bb is laminated on the gate electrode 211bb, and a tungsten silicide film pattern 239bb is laminated on the N ⁺ type polycrystalline silicon film pattern 237bb. The film thickness of the N ⁺ type polycrystalline silicon film patterns 237ba and 237bb is 10
The thickness of the tungsten / silicide film patterns 239ba and 239bb is about 150 nm.

On the surface of the P-type silicon substrate 201 forming the element formation region 203, an N-type diffusion layer 213ba having an LDD structure is provided in a self-aligned manner only with the word line 211ba.
An N-type diffusion layer 213bb is provided in a self-aligned manner with the word line 211ba and the gate electrode 211bb.
The N-type diffusion layer 213bc is provided in a self-alignment only for 11bb. N-type diffusion layer 213ba and N-type diffusion layer 21
3bc are shared by two memolcells, respectively,
Type diffusion layer 213bb is formed of Tr1 and Tr3 (or
Tr2 and Tr4). Tr3 (and Tr4) includes a gate oxide film 210, a word line 211ba (which is a first gate electrode), an N-type diffusion layer 213ba (which becomes a first N-type source / drain region), and an N-type diffusion layer. 213bb. Tr1
(And Tr2) are composed of the gate oxide film 209 and the (second
), And an N-type diffusion layer 213bb (which becomes the second N-type source / drain region) and an N-type diffusion layer 213bc. The channel length and channel width of Tr3 (and Tr4) are set to about 0.2 μm and about 0.2 μm, respectively.
2) The channel length and channel width are about 0.2 μm and 8 μm.
m.

Tr1 to Tr4 and field insulating film 2
07ba, 207bb and the P-type silicon substrate 20
1 is covered with an interlayer insulating film 215. The interlayer insulating film 215 includes a bit contact hole 217 reaching the N-type diffusion layer 213ba, a node contact hole 218 reaching the N-type diffusion layer 213bb, and an N-type diffusion layer 213.
A ground contact hole 219 reaching bb is provided. Although not shown in FIGS. 13 and 14 on the surface of the interlayer insulating film 215, the bit lines (BL1, BL2), the resistance load elements (R1, R2),
A power supply wiring (V _CC ), a ground wiring, and the like are provided.

The semiconductor device according to the second example of the second embodiment has the same effects as the semiconductor device according to the first example of the second embodiment. Book second
In the Tr3 and Tr4 according to this embodiment, unlike the first embodiment, the thickness of the gate oxide film 210 is increased, but the impurity concentration of the element forming region 203 at the portion sandwiched between the field insulating films 207ba is reduced. By lowering the first
The S value can be made approximately the same as that of the first MOS transistor of the embodiment. On the other hand, in the second embodiment, the provision of the gate oxide film 210 makes the third embodiment higher in electrostatic breakdown resistance than the Tr3 and Tr4 of the first embodiment.

The method of manufacturing the semiconductor device according to the second embodiment of the second embodiment is similar to the method of manufacturing the gate oxide films 209 and 2 of FIG.
Except for the manufacturing process related to 10, the method is basically the same as the method of manufacturing the semiconductor device according to the first embodiment. The outline of the method of manufacturing the semiconductor device according to the second embodiment is as follows.

First, a pad oxide film and a silicon nitride film covering the surface of the P-type silicon substrate 201 are formed in the same manner as in the manufacturing method of the first embodiment. Using the first photo-resist film pattern as a mask, the silicon nitride film, the pad oxide film, and the P-type silicon substrate are sequentially etched to form a groove 205 surrounding the element formation region 203ca. A silicon oxide film is formed on the entire surface, and the silicon oxide film is chemically and mechanically polished to form a field insulating film filling trench 205. At least Tr1, Tr
The field insulating film is etched using the (second) photoresist film pattern having a strip-like form as a mask, covering the formation planned region 2 and having at least openings in the formation regions of Tr3 and Tr4. , A (first) field insulating film 207ba filling the groove 205 is formed, and the (second) field insulating film 207b filling the groove 205 is formed.
b is formed remaining. After the formation of the sacrificial oxide film and the removal of the silicon nitride film on the exposed portions on the side surfaces of the trench 205, finally, the impurities near the surface of the element formation region 203 in the regions where Tr3 and Tr4 are to be formed are finally formed. Concentration and Tr
Element formation region 203 in the region where Tr1 and Tr2 are to be formed
Channel doping of boron or the like is performed so that the impurity concentration in the vicinity of the surface becomes a required value.

Next, the pad oxide film and the sacrificial oxide film are removed. A silicon oxide film having a thickness of about 5 nm is formed by thermal oxidation on the surface of the P-type silicon substrate 201 forming the element forming region 203 and on the exposed portions on the side surfaces of the groove 205.
An opening is provided at least in a region where Tr3 and Tr4 are to be formed, and at least in a region where Tr1 and Tr2 are to be formed;
The silicon oxide film is etched away using the (third) photo resist film pattern having a band-like appearance as a mask. Further, thermal oxidation is performed, and Tr3, Tr4
A (first) gate oxide film 210 having a thickness of about 11 nm is formed on the surface of the P-type silicon substrate 201 and the exposed portion on the side surface of the groove 205 which form the element forming region 203 in the region where the device is to be formed. , Tr2, the P-type silicon substrate 101 forming the element formation region 203 in the portion where the formation is to be formed
A gate oxide film 209 having a thickness of about 6 nm is formed on the surface of the substrate.

Subsequently, an N ⁺ -type N ⁺ -type polycrystalline silicon film having a thickness of about 100 nm is formed on the entire surface at the film forming stage, and a tungsten film having a thickness of about 150 nm is formed on the entire surface. -A silicide film is formed. Then the fourth
The tungsten silicide film and the N ⁺ -type polycrystalline silicon film are sequentially patterned using the photo resist film pattern as a mask to form word lines 211ba and gate electrodes 211bb. Then, the N-type diffusion layers 213ba and 213ba,
13bb and 213bc are formed, an interlayer insulating film 215 is formed, and a bit contact hole 217, a node contact hole 218, a bit line, a resistive load element, a second interlayer insulating film, a ground contact hole 219, a power supply are provided. Wiring and ground wiring are formed.

[0092]

As described above, according to the present invention, only the MOS transistor functioning as a transfer transistor is constituted by the edge operation type, and the MOS transistor whose current driving function is important is constituted by the non-edge operation type. Therefore, M as a transfer transistor
At the same time as increasing the access speed of the OS transistor, it becomes easy to suppress a decrease in the operating speed of the MOS transistor in which the current drive function is important.

[Brief description of the drawings]

FIG. 1 is a schematic plan view and a schematic sectional view of a semiconductor device according to a first example of the first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a manufacturing process of the semiconductor device according to the first embodiment of the first embodiment, which is a cross-sectional schematic view along the line AA in FIG.

FIG. 3 is a schematic cross-sectional view of a manufacturing process of the semiconductor device of the first example of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line BB in FIG.

FIG. 4 is a schematic cross-sectional view of a manufacturing process of the semiconductor device according to the first embodiment of the first embodiment, and is a schematic cross-sectional view of the manufacturing process along line CC in FIG. 1A.

FIG. 5 is a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a second example of the first embodiment of the present invention.

FIG. 6 is a schematic plan view and a schematic cross-sectional view of a semiconductor device according to a third example of the first embodiment of the present invention.

FIG. 7 is a diagram for explaining a second embodiment of the present invention;
FIG. 3 is a circuit diagram of a memory cell of a RAM.

FIG. 8 is a schematic plan view of a semiconductor device according to a first example of the second embodiment of the present invention.

9 is a schematic cross-sectional view of the semiconductor device according to the first example of the second embodiment, taken along line AA, BB, and CC in FIG. 7;

FIG. 10 is a schematic cross-sectional view of a manufacturing step of the semiconductor device of the first example of the second embodiment, and is an AA of FIG. 9;
It is a cross-sectional schematic diagram of the manufacturing process in a line.

FIG. 11 is a schematic cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the second embodiment, which is taken along the line BB in FIG. 9;
It is a cross-sectional schematic diagram of the manufacturing process in a line.

FIG. 12 is a schematic cross-sectional view of a manufacturing process of the semiconductor device of the first example of the second embodiment, and is a sectional view of FIG.
It is a cross-sectional schematic diagram of the manufacturing process in a line.

FIG. 13 is a schematic plan view of a semiconductor device according to a second example of the second embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view of the semiconductor device of the second example of the second embodiment, taken along line AA, BB and CC in FIG. 7;

FIG. 15 is a schematic plan view and a schematic cross-sectional view of a conventional semiconductor device.

[Figure 16] is a diagram for explaining the problems of the conventional semiconductor device, a graph showing the I _D -V _G characteristics.

[Explanation of symbols]

101, 201, 301 P-type silicon substrate 103aa, 103ab, 103ba, 103bb, 1
03ca, 103cb, 203, 303 Element formation region 105, 205, 305 Groove 107a, 107aa, 107ab, 107ba, 10
7bb, 107ca, 107cb, 207a, 207a
a, 207ab, 207ba, 207bb, 307
Field insulating films 109, 110, 209, 210, 309 Gate oxide films 111aa, 111ba, 111ca, 211aa, 2
11ba, 311a word lines 111ab, 111bb, 111cb, 211ba, 2
11bb, 311b Gate electrode 113aa, 113ab, 113ba, 113bb, 1
13ca, 113cb, 313a, 313b N-type source / drain regions 115, 215, 315 Interlayer insulating film 117, 217, 317 Bit contact hole 118, 218, 318 Node contact hole 119, 319 Contact hole 131, 231 Pad oxide film 132,232 Silicon nitride film 133,233 Sacrificial oxide film 135,235 Photoresist film pattern 137aa, 137ab, 137b, 137ca, 13
7cb, 237aa, 237ab, 237ba, 237
bb, 337a, 337b N ⁺ type polycrystalline silicon film pattern 138 P ⁺ type polycrystalline silicon film pattern 139aa, 139ab, 139ba, 139bb, 1
39ca, 139cb, 239aa, 239ab, 23
9ba, 239bb, 339a, 339b Tungsten silicide film pattern 213aa, 213ab, 213ac, 213ba, 2
13bb, 213bc N type diffusion layer 219 Ground contact hole Tr1, Tr2, Tr3, Tr4 N channel MOS
Transistor R1, R2 Resistance load element

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁶ identification code FI H01L 27/11 (58) Investigation field (Int.Cl. ⁶ , DB name) H01L 21/8244 H01L 21/8242 H01L 27/10 481 H01L 27/108 H01L 27/11 H01L 21/76

Claims (14)

(57) [Claims] An element forming region provided on a surface of a P-type silicon substrate is surrounded by a groove formed on a surface of the P-type silicon substrate, and the groove is formed between a first field insulating film and a second field insulating film. And a top surface of the first field insulating film is provided at a position lower than a surface of the P-type silicon substrate by a required height, and a top surface of the second field insulating film is provided by the first field insulating film. A first gate electrode, a first gate oxide film, and a first N-type source / drain are provided at a position higher than the upper surface of the insulating film, and in the element formation region sandwiched between the first field insulating films. A first N having a region
A channel MOS transistor is provided, and the element formation region sandwiched between the second field insulating films has a second gate electrode, a second gate oxide film, and a second N-type source / drain region. The second N
A semiconductor device comprising a channel MOS transistor. 2. The method according to claim 1, wherein the first and second gate electrodes are formed on the first and second N ⁺ -type polycrystalline silicon film patterns having the same thickness, respectively, by the first and second refractory metals having the same thickness. The first and second gate oxide films have the same thickness, and the first and second gate oxide films have the same thickness.
2. The semiconductor device according to claim 1, wherein the junction depths of the second N-type source / drain regions are equal to each other. 3. The first and second refractory metal silicides having the same thickness as the P ⁺ -type polycrystalline silicon film pattern and the N ⁺ -type polycrystalline silicon film pattern, respectively. 2. The semiconductor according to claim 1, wherein a film pattern is laminated, said first and second gate oxide films have the same thickness, and said first and second N-type source / drain regions have the same junction depth. apparatus. 4. The first and second gate electrodes are formed on the first and second N ⁺ -type polycrystalline silicon film patterns having the same film thickness, respectively, by the first and second refractory metals having the same film thickness. A first gate oxide film having a thickness greater than a thickness of the second gate oxide film and a junction depth between the first and second N-type source / drain regions; The semiconductor device according to claim 1, wherein: 5. A regularly arranged first element formation region is provided in a cell array region on a surface of a P-type silicon substrate, and a second element formation region is provided in a peripheral circuit region on a surface of the P-type silicon substrate.
The first and second element formation regions are respectively surrounded by grooves provided on the surface of the P-type silicon substrate, and the portions respectively surround the first and second element formation regions. Are filled with first and second field insulating films, respectively, and the upper surface of the first field insulating film is provided at a position lower than the surface of the P-type silicon substrate by a required height. The upper surface of the field insulating film is provided at a position higher than the upper surface of the first field insulating film, and the first element forming region sandwiched between the first field insulating films has a first element forming region also serving as a word line. A first N-channel MOS transistor having a gate electrode, a first gate oxide film, and a first N-type source / drain region is provided, and one of the first N-type source / drain regions is provided with a bit. And the other of the first N-type source / drain regions is connected to a capacitor, and the first N-channel MOS
A memory cell of a DRAM is constituted by the transistor and the capacitor, and a second gate electrode, a second gate oxide film, and a second N-type are formed in the element formation region sandwiched by the second field insulating film. A semiconductor device, comprising: a second N-channel MOS transistor having a source / drain region; and a peripheral circuit including the second N-channel MOS transistor. 6. The first and second refractory metal layers having the same film thickness respectively formed on the first and second N ⁺ -type polycrystalline silicon film patterns having the same film thickness. The first and second gate oxide films have the same thickness, and the first and second gate oxide films have the same thickness.
6. The semiconductor device according to claim 5, wherein the junction depths of the second N-type source / drain regions are equal to each other. 7. The first and second refractory metal silicides having the same thickness as the P ⁺ -type polysilicon film pattern and the N ⁺ -type polysilicon film pattern, respectively. 6. The semiconductor according to claim 5, wherein a film pattern is laminated, said first and second gate oxide films have the same thickness, and said first and second N-type source / drain regions have the same junction depth. apparatus. 8. The first and second N.sup. ⁺ -Type polycrystalline silicon film patterns having the same film thickness are respectively formed on the first and second gate electrodes by the first and second refractory metals having the same film thickness. A first gate oxide film having a thickness greater than a thickness of the second gate oxide film and a junction depth between the first and second N-type source / drain regions; 6. The semiconductor device according to claim 5, wherein: 9. A pair of element forming regions are provided in regions where SRAM memory cells are formed on the surface of the P-type silicon substrate, and the element forming regions are formed on the surface of the P-type silicon substrate. The trench is filled with a first field insulating film and a second field insulating film, and the upper surface of the first field insulating film is lower than the surface of the P-type silicon substrate by a required height. And the upper surface of the second field insulating film is provided at a position higher than the upper surface of the first field insulating film.
The first N-channel MOS transistor is provided in a part of the element formation region sandwiched between the first field insulating films, and the first N-channel MOS transistor is a word line. A first gate electrode, a first gate oxide film, and a first N-type source / drain region, one of which is connected to a bit line. The other of the first N-type source / drain regions is connected to a resistive load element, and the second N-channel MOS transistor is provided in a part of the element forming region sandwiched between the second field insulating films. The second N-channel MOS transistor includes a second gate electrode, a second gate oxide film, and a second N-type source / drain region.
One of the drain regions is composed of the other of the first N-type source / drain regions, the other of the second N-type source / drain regions is connected to a ground line, Is connected to the second gate electrode of the second N-channel MOS transistor provided in the other of the paired element forming regions. A semiconductor device. 10. The first and second gate electrodes,
The first and second refractory metal silicide film patterns having the same thickness are respectively laminated on the first and second N ⁺ -type polycrystalline silicon film patterns having the same thickness. 10. The semiconductor device according to claim 9, wherein the gate oxide films have the same thickness, and the first and second N-type source / drain regions have the same junction depth. 11. The first and second gate electrodes,
The first and second refractory metal silicide film patterns having the same thickness are respectively laminated on the first and second N ⁺ -type polycrystalline silicon film patterns having the same thickness, and the first gate oxide film is formed. 10. The semiconductor device according to claim 9, wherein a thickness of said first gate oxide film is larger than a thickness of said second gate oxide film, and a junction depth of said first and second N-type source / drain regions is equal. 12. A pad oxide film and a silicon nitride film are formed on a surface of a P-type silicon substrate, and a first photoresist film pattern covering an element formation region is used as a mask.
Etching the silicon nitride film and the pad oxide film,
Forming a groove in the surface of the P-type silicon substrate by etching the P-type silicon substrate; forming an insulating film made of a silicon oxide film on the entire surface; Forming a field insulating film that fills the groove by chemical mechanical polishing (CMP) the insulating film; and etching the field insulating film to a desired thickness using the second photoresist pattern as a mask. Forming a first field insulating film in a portion not covered by the second photo resist film pattern, and forming a second field insulating film in a portion covered by the second photo resist film pattern; Forming a residue, etching and removing the silicon nitride film, etching and removing the pad oxide film, and keeping the upper surface of the first field insulating film in front. A step of lowering the surface by a required height from the surface of the P-type silicon substrate, a step of forming a gate oxide film in the element formation region by thermal oxidation, a step of forming an N ⁺ -type polycrystalline silicon film on the entire surface, Forming a refractory metal silicide film, patterning the refractory metal silicide film and the N ⁺ -type polycrystalline silicon film using the third photoresist pattern as a mask, and sandwiching the first field insulating film. Forming a first gate electrode in the device forming region, and forming a second gate electrode in the device forming region sandwiched between the first field insulating films; Forming an N-type source / drain region on the surface of the element formation region using an electrode as a mask. 13. A pad oxide film and a silicon nitride film are formed on a surface of a P-type silicon substrate, and a first photoresist film pattern covering an element formation region is used as a mask.
Etching the silicon nitride film and the pad oxide film,
Forming a groove in the surface of the P-type silicon substrate by etching the P-type silicon substrate; forming an insulating film made of a silicon oxide film on the entire surface; Forming a field insulating film to fill the groove by chemical mechanical polishing the insulating film; etching the field insulating film to a desired thickness using the second photoresist film pattern as a mask; Forming a first field insulating film on a portion not covered by the second photoresist film pattern, and forming a second field insulating film on the portion covered by the second photoresist film pattern; Etching the silicon nitride film; removing the pad oxide film by etching; and etching the upper surface of the first field insulating film with the P-type silicon film. A step of lowering the surface by a required height from the surface of the capacitor substrate; a step of forming a gate oxide film in the element formation region by thermal oxidation; and a step of forming an N ⁺ type N ⁺ -type polycrystalline silicon film over the entire surface. Forming the first field by ion-implantation of a P-type impurity using a third photo-resist film pattern covering the element forming region sandwiched between the second field insulating films as a mask. The N on the element formation region sandwiched between insulating films
Converting the ⁺ -type polycrystalline silicon film to a P ⁺ -type polycrystalline silicon film; forming a high-melting-point metal silicide film over the entire surface; and using the fourth photo-resist film pattern as a mask, The N ⁺ -type polycrystalline silicon film and the P ⁺ -type polycrystalline silicon film are sequentially patterned to form the P ^{+ in the} element forming region sandwiched between the first field insulating films.
Forming a first gate electrode made of a refractory metal polycide film including a polycrystalline silicon film, and forming the N ⁺ -type polycrystalline silicon film in the element forming region sandwiched by the second field insulating film; Forming a second gate electrode made of a high-melting-point metal polycide film containing: and forming an N-type source / drain region on the surface of the element formation region using the first and second gate electrodes as a mask. Forming a semiconductor device. 14. A pad oxide film and a silicon nitride film are formed on a surface of a P-type silicon substrate, and a first photoresist film pattern covering an element formation region is used as a mask.
Etching the silicon nitride film and the pad oxide film,
Forming a groove in the surface of the P-type silicon substrate by etching the P-type silicon substrate; forming an insulating film made of a silicon oxide film on the entire surface; Forming a field insulating film to fill the groove by chemical mechanical polishing the insulating film; etching the field insulating film to a desired thickness using the second photoresist film pattern as a mask; Forming a first field insulating film on a portion not covered by the second photoresist film pattern, and forming a second field insulating film on the portion covered by the second photoresist film pattern; Etching the silicon nitride film; removing the pad oxide film by etching; and etching the upper surface of the first field insulating film with the P-type silicon film. Forming a silicon oxide film in the element formation region by thermal oxidation to cover the element formation region sandwiched by the first field insulating film; Removing the silicon oxide film using the photo-resist film pattern as a mask, and leaving the silicon oxide film in the element formation region sandwiched between the first field insulating films; Forming a first gate oxide film in the element formation region sandwiched by the first field insulating film, and forming a first gate oxide film in the element formation region sandwiched by the second field insulation film; Forming a thin second gate oxide film, forming an N ⁺ type polycrystalline silicon film over the entire surface, further forming a refractory metal silicide film, and using the fourth photoresist film pattern as a mask. The high Wherein the said element forming region sandwiched between the first field insulating film to form a first gate electrode by patterning the point metal silicide film and the N ⁺ -type polycrystalline silicon film, said first field insulating film Forming a second gate electrode in the element formation region sandwiched therebetween, and forming N-type source / drain regions on the surface of the element formation region using the first and second gate electrodes as a mask; A method for manufacturing a semiconductor device, comprising: