KR0161196B1 - Fabricating method of capacitor storage node - Google Patents

Fabricating method of capacitor storage node Download PDF

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Publication number
KR0161196B1
KR0161196B1 KR1019950019357A KR19950019357A KR0161196B1 KR 0161196 B1 KR0161196 B1 KR 0161196B1 KR 1019950019357 A KR1019950019357 A KR 1019950019357A KR 19950019357 A KR19950019357 A KR 19950019357A KR 0161196 B1 KR0161196 B1 KR 0161196B1
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forming
charge storage
storage electrode
polysilicon
layer
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KR1019950019357A
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KR970003963A (en
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여태정
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

1. 청구 범위에 기재된 발명이 속한 기술 분야1. The technical field to which the invention described in the claims belongs

반도체 소자 제조방법Semiconductor device manufacturing method

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

종래의 방법으로는 고집적화된 반도체 소자에서 소자를 동작시키기에 충분한 전하용량을 가진 캐패시터를 형성하기에는 공간이 부족하다는 문제점을 해결하고자 함.The conventional method solves the problem of insufficient space to form a capacitor having a sufficient charge capacity to operate the device in a highly integrated semiconductor device.

3. 발명의 해결 방법의 요지.3. Summary of the solution of the invention.

전하저장 전극의 모양 형성을 용이하게 하기 위한 희생막을 형성하고 습식 식각과 건식 식각 공정을 차례로 실시 하므로써 폴리실리콘 스페이서를 형성하여 한정된 공간에서 전극의 표면적을 극대화하고자 함.By forming a sacrificial film to facilitate the formation of the shape of the charge storage electrode and performing wet etching and dry etching processes in order, polysilicon spacers are formed to maximize the surface area of the electrode in a limited space.

4. 발명의 중요한 용도.4. Important uses of the invention.

캐패시터의 전하저장 전극을 형성하는데 주로 이용됨.It is mainly used to form charge storage electrodes of capacitors.

Description

캐패시터의 전하저장 전극 형성 방법Method for forming charge storage electrode of capacitor

제1a도 내지 제1e도는 본 발명의 캐패시터 전하저장 전극 형성 방법에 따른 공정도.1a to 1e is a process chart according to the capacitor charge storage electrode forming method of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 접합부 2 : 반도체 기판1 junction 2 semiconductor substrate

3 : 층간절연막 4 : 식각 장벽층3: interlayer insulating film 4: etching barrier layer

5 : 측벽산화막 6,9 : 폴리실리콘5: sidewall oxide film 6,9: polysilicon

7 : PSG(Phosphorous Silicate Glass)막7: PSG (Phosphorous Silicate Glass) film

8 : 포토레지스트8: photoresist

본 발명은 반도체 소자 제조 방법에 관한 것으로서 특히 한정된 셀(cell)영역 내에서 유효 표면적을 극대화하여 정전용량을 높인 캐패시터(Capacitor)의 전하저장 전극(Storage Electrode)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a storage electrode of a capacitor having a high capacitance by maximizing an effective surface area within a limited cell region.

반도체 소자가 고집적화됨에 따라 캐패시터가 차지할 수 있는 면적은 줄어들고 있지면 캐패시터는 소자를 동작시키기에 충분한 전하용량을 수용할 수 있어야 한다. 그런데 종래의 방법으로는 좁은 공간에서 충분한 전하용량을 가지면서 소자를 고집적화 하는데는 한계가 있었다.If the area occupied by a capacitor is decreasing as semiconductor devices become more integrated, the capacitor must be able to accommodate sufficient charge capacity to operate the device. However, the conventional method has a limitation in integrating devices with sufficient charge capacity in a narrow space.

따라서, 전술한 바와 같은 문제점을 해결하기 위해 안출된 본 발명은 전하저장 전극(storage electrode)의 모양 형성을 용이하게 하기 위한 희생막을 형성하고 전하저장 전극의 표면이 될 부분에 습식 식각과 건식 식각 공정을 차례로 실시하므로써 전극의 표면적을 극대화하여 정전용량이 증가된 캐패시터 전하저장 전극을 형성하는 방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention devised to solve the above-mentioned problems is to form a sacrificial film for facilitating the formation of the shape of the storage electrode (wet) and the wet etching and dry etching process on the portion to be the surface of the charge storage electrode It is an object of the present invention to provide a method for forming a capacitor charge storage electrode having an increased capacitance by maximizing the surface area of the electrode.

본 발명의 캐패시터의 전하저장 전극 형성 방법은, 접합부가 형성된 반도체 기판에 층간 절연막과 식각 장벽층이 증착되고 상기 접합부 상에 콘택홀이 형성되고 상기 콘택홀 측벽에 측벽 산화막이 형성된 구조 상에 제1 폴리실리콘층을 증착하는 단계와, 전하저장 전극의 모양 형성을 용이하게 하기 위한 희생막을 증착하는 단계와, 상기 접합부 상부가 오픈된 전하저장 전극을 형성하기 위한 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 배리어로 이용하여 상기 희생막의 일부를 습식식각 한 후 잔류 희생막과 상기 제1폴리 실리콘층을 건식식각하는 단계와, 잔류 포토레지스트를 제거하고 제2폴리실리콘을 증착하는 단계와, 상기 제2폴리실리콘층을 블랭킷 식각하여 측벽 폴리실리콘 스페이서를 형성하는 단계 및 습식식각을 실시하여 잔류 희생막을 제거하는 단계를 포함하는 것을 특징으로 한다.In the method of forming a charge storage electrode of a capacitor of the present invention, an interlayer insulating film and an etch barrier layer are deposited on a semiconductor substrate on which a junction is formed, a contact hole is formed on the junction, and a sidewall oxide film is formed on the sidewall of the contact hole. Depositing a polysilicon layer, depositing a sacrificial film for facilitating the formation of the shape of the charge storage electrode, forming a photoresist pattern for forming the charge storage electrode with the junction open; Wet etching a portion of the sacrificial layer using a photoresist pattern as an etching barrier and then dry etching the remaining sacrificial layer and the first polysilicon layer, removing the remaining photoresist and depositing a second polysilicon; And blanket etching the second polysilicon layer to form sidewall polysilicon spacers and wet etching. And removing the remaining sacrificial film.

이제 본 발명의 캐패시터의 전하저장 전극 형성 방법의 한 실시예에 대하여 첨부도면을 참조하여 상세하게 살펴보게 된다. 먼저 제1a도에 도시된 바와 같이 접합부(1)가 형성된 반도체 기판(2)에 층간 절연막(3)과 식각 장벽층(4)이 증착되고 상기 접합부(1)상에 콘택홀이 형성되고 상기 콘택홀 측벽에 측벽 산화막(5)이 형성된 구조 상에 폴리실리콘(6)층을 증착한다. 그리고 전하저장 전극의 모양 형성을 용이하게 하기 위한 희생막으로 PSG(Phosphorous silicate Glass)막(7)을 증착한다. 이 때 상기 PSG막(7)은 후속 공정인 습식식각 공정에서 시간을 줄이기 위해 인이온을 약 6 내지 9 중량퍼센트로 다량 포함하게 한다. 다음으로 제1b도에 도시된 바와 같이 상기 접합부 영역이 오픈되고 전하저장 전극을 형성하기 위한 포토레지스트 패턴(8)을 형성한다. 그리고 상기 포토레지스트 패턴(8)을 식각 배리어로 이용하여 상기 PSG막(7)의 일부를 습식식각하여 상기 포토레지스트 패턴 하부에 언터컷(undercut)이 형성된 후 잔류 PSG막(7)과 상기 폴리실리콘층(6)을 건식식각 한다. 다음으로 제1c도에 도시된 바와 같이 잔류 포토레지스트를 제거하고 전체 구조 상에 폴리실리콘(9)을 증착한다. 다음으로 제1D도에 도시된 바와 같이 상기 폴리실리콘층(9)을 블랭킷 식각하여 상기 PSG막(7)과 폴리실리콘층(6)의 측벽에 폴리실리콘 스페이서가 형성되고 트렌치 부분 및 전하저장 전극 형성 외영역은 상기 폴리실리콘(9)이 제거된다. 상기 폴리실리콘 스페이서는 전하저장 전극의 표면적을 넓히는 역할을 한다. 마지막으로 제1e도에 도시된 바와 같이 습식식각을 실시하여 잔류 PSG막을 제거한다.An embodiment of the charge storage electrode forming method of the capacitor of the present invention will now be described in detail with reference to the accompanying drawings. First, as shown in FIG. 1A, an interlayer insulating film 3 and an etch barrier layer 4 are deposited on a semiconductor substrate 2 on which a junction 1 is formed, and a contact hole is formed on the junction 1. A layer of polysilicon 6 is deposited on the structure in which the sidewall oxide film 5 is formed on the hole sidewall. And a PSG (Phosphorous silicate Glass) film 7 is deposited as a sacrificial film to facilitate the formation of the shape of the charge storage electrode. At this time, the PSG film 7 contains a large amount of phosphorus ions in about 6 to 9% by weight in order to reduce time in a subsequent wet etching process. Next, as shown in FIG. 1B, the junction region is opened to form a photoresist pattern 8 for forming a charge storage electrode. A portion of the PSG film 7 is wet-etched using the photoresist pattern 8 as an etching barrier to form an undercut under the photoresist pattern, and then the residual PSG film 7 and the polysilicon are formed. Dry etch layer (6). Next, as shown in FIG. 1C, residual photoresist is removed and polysilicon 9 is deposited on the entire structure. Next, as shown in FIG. 1D, the polysilicon layer 9 is blanket-etched to form polysilicon spacers on sidewalls of the PSG layer 7 and the polysilicon layer 6 to form trench portions and charge storage electrodes. In the outer region, the polysilicon 9 is removed. The polysilicon spacer serves to widen the surface area of the charge storage electrode. Finally, as shown in FIG. 1e, wet etching is performed to remove the residual PSG film.

반도체 소자의 캐패시터 제조시, 전술한 바와 같은 본 발명에 따라 폴리실리콘 스페이서를 형성하므로써 캐패시터의 전하저장 전극의 표면적을 넓히고 정전용량을 증대시킬 수 있어 반도체 소자가 고집적화됨에 따라 사용할 수 있는 방법이다.When manufacturing a capacitor of a semiconductor device, by forming a polysilicon spacer according to the present invention as described above, the surface area of the charge storage electrode of the capacitor can be increased and the capacitance can be increased, so that the semiconductor device can be used as a high integration.

Claims (3)

반도체 소자의 캐패시터의 전하저장 전극 형성 방법에 있어서, 접합부가 형성된 반도체 기판에 층간 절연막과 식각 장벽층이 증착되고 상기 접합부 상에 콘택홀이 형성되고 상기 콘택홀 측벽에 측벽 산화막이 형성된 구조 상에 제1폴리 실리콘층을 증착하는 단계와, 전하저장 전극의 모양 형성을 용이하게 하기 위한 희생막을 증착하는 단계와, 상기 접합부 상부가 오픈된 전하저장 전극을 형성하기 위한 포토레지스트 패턴을 형성하는 단계와, 상기 포토레지스트 패턴을 식각 배리어로 이용하여 상기 희생막의 일부를 습식식각한 후 잔류 희생막과 상기 제1 폴리실리콘층을 건식식각하는 단계와, 잔류 포토레지스트를 제거하고 제2폴리실리콘을 증착하는 단계와, 상기 제2폴리실리콘층을 블랭킷 식각 하여 측벽 폴리실리콘 스페이서를 형성하는 단계 및 습식식각을 실시하여 잔류 희생막을 제거하는 단계를 포함하여 이루어진 캐패시터의 전하저장 전극 형성 방법.A method for forming a charge storage electrode of a capacitor of a semiconductor device, comprising: depositing an interlayer insulating film and an etch barrier layer on a semiconductor substrate on which a junction is formed, forming a contact hole on the junction, and forming a sidewall oxide film on the sidewall of the contact hole. Depositing a polysilicon layer, depositing a sacrificial film for facilitating the formation of the shape of the charge storage electrode, forming a photoresist pattern for forming the charge storage electrode with the junction open; Wet etching a portion of the sacrificial layer using the photoresist pattern as an etch barrier and then dry etching the remaining sacrificial layer and the first polysilicon layer; removing the remaining photoresist and depositing a second polysilicon; Blanket etching the second polysilicon layer to form sidewall polysilicon spacers; and A method of forming a charge storage electrode of a capacitor comprising wet etching to remove a residual sacrificial layer. 제1항에 있어서, 상기 희생막은 포스포러스-실리케이트-글래스인 것을 특징으로 하는 캐패시터 전하저장 전극 형성 방법.The method of claim 1, wherein the sacrificial layer is phosphorus-silicate-glass. 제2항에 있어서, 상기 포스포러스-실리케이트-글래스의 포스포러스 험유율은 약 6 내지 9 중량퍼센트인 것을 특징으로 하는 캐패시터 전하저장 전극 형성 방법.3. The method of claim 2, wherein the phosphorus hum flow rate of the phosphorus-silicate-glass is about 6 to 9 weight percent.
KR1019950019357A 1995-06-30 1995-06-30 Fabricating method of capacitor storage node KR0161196B1 (en)

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