KR100235895B1

KR100235895B1 - Manufacturing method of capacitor charge storage electrode

Info

Publication number: KR100235895B1
Application number: KR1019930029763A
Authority: KR
Inventors: 김대영; 이찬용
Original assignee: 김영환; 현대전자산업주식회사
Priority date: 1993-12-27
Filing date: 1993-12-27
Publication date: 1999-12-15
Also published as: KR950021469A

Abstract

본 발명은 캐패시터의 전하저장전극을 형성하는 방법에 관한 것으로, 측벽이 스페이서 구조를 갖는 실린더형(Cylinder type) 전하저장전극을 반구형 폴리실리콘을 이용하여 유효표면적을 증대시키고자 할 때, 형성되는 반구형 폴리실리콘을 최대한으로 이용하여 전하저장전극의 유효표면적을 증대시킬 수 있는 캐패시터의 전하저장전극을 형성하는 방법에 관해 기술된다.The present invention relates to a method of forming a charge storage electrode of a capacitor, and is formed when a cylinder type charge storage electrode having a spacer structure having a side wall is formed using a hemispherical polysilicon to increase the effective surface area. A method of forming a charge storage electrode of a capacitor capable of increasing the effective surface area of the charge storage electrode using polysilicon to the maximum is described.

Description

Method of forming charge storage electrode of capacitor

제1a도 내지 제1f도는 본 발명에 의한 캐패시터의 전하저장전극을 형성하는 단계를 도시한 단면도.1A to 1F are cross-sectional views showing steps of forming a charge storage electrode of a capacitor according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 필드산화막1: silicon substrate 2: field oxide film

3 : 게이트전극 3A : 게이트 전극선3: gate electrode 3A: gate electrode line

4 : 불순물영역(소오스 및 드레인) 5 : 제1층간 절연막4 impurity region (source and drain) 5 first interlayer insulating film

6 : 비트라인 7 : 제2층간 절연막6 bit line 7 second interlayer insulating film

8 : 질화막 9 : 콘택홀8: nitride film 9: contact hole

10 : 제1폴리실리콘 11 : 제1희생 산화막10: first polysilicon 11: first sacrificial oxide film

12 : 제2희생 산화막 13 : 제3희생 산화막12: second sacrificial oxide film 13: third sacrificial oxide film

14 : 제2폴리실리콘 15 : 반구형 폴리실리콘14 second polysilicon 15 hemispherical polysilicon

본 발명은 캐패시터의 전하저장전극을 형성하는 방법에 관한 것으로, 특히 측벽이 스페이서 구조를 갖는 실린더형(Cylinder Type) 전하저장전극을 반구형 폴리실리콘을 이용하여 유효표면적을 증대시키고자 할 때, 형성되는 반구형 폴리실리콘을 최대한으로 이용하여 전하저장전극의 유효표면적을 증대시킬 수 있는 캐패시터의 전하저장전극을 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a charge storage electrode of a capacitor, in particular, when a cylindrical type charge storage electrode having a spacer structure having a sidewall is formed using hemispherical polysilicon to increase the effective surface area. The present invention relates to a method of forming a charge storage electrode of a capacitor capable of increasing the effective surface area of a charge storage electrode by using hemispherical polysilicon to the maximum.

일반적으로, 반도체 소자가 고집적화 되어감에 따라 셀 면적은 급격하게 축소되고 셀 면적의 축소에도 불구하고 소자의 동작에 필요한 셀당 일정용량이상의 캐패시터 용량을 확보해야 한다.In general, as semiconductor devices are highly integrated, the cell area is drastically reduced, and despite the reduction in cell area, a capacitor capacity of more than a predetermined capacity per cell required for the operation of the device must be secured.

이를 해결하기 위하여 여러 가지 3차원의 전하저장전극을 제시되고 있으며 보다 유용한 구조로 제조하기 위해 계속 연구되고 있다.In order to solve this problem, various three-dimensional charge storage electrodes have been proposed and continuously studied to manufacture more useful structures.

따라서 본 발명은 반도체소자의 고집적화에 적합하도록 제한된 면적하에서 유효표면적을 극대화할 수 있는 캐패시터의 전하저장전극 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a charge storage electrode of a capacitor capable of maximizing an effective surface area under a limited area to be suitable for high integration of semiconductor devices.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제1a도 내지 제1f도는 본 발명에 의한 캐패시터의 전하저장전극을 형성하는 단계를 도시한 단면도로서, 제1a도는 실리콘 기판(1)상에 필드 산화막(2)을 형성하고, 게이트 전극(3)과 게이트 전극선(3A)을 형성하고, 상기 게이트 전극(3) 양측에 소오스 및 드레인 전극으로 사용될 불순물 영역(4)을 형성한 후, 전체적으로 제1층간 절연막(5)을 형성한 다음, 상기 불순물 영역(4)중 어느 한 영역에 접속되는 비트라인(6)을 형성하고, 전체적으로 제2층간 절연막(7)을 증착 평탄화 한다음, 상기 제2층간 절연막(7)상에 식각장벽층으로 질화막(8)을 형성하고 전하저장전극 콘택마스크를 이용한 식각공정으로 다른측 불순물 영역(4)과 연통되는 콘택홀(9)을 형성하고, 상기 콘택홀(9)을 포함한 질화막(8)상부에 전하저장전극용 제1폴리실리콘(10)을 증착한 후, 그 상부에 제1, 2 및 3 희생 산화막(11,12 및 13)을 차례로 증착한 상태를 도시한 것이다.1A to 1F are cross-sectional views showing a step of forming a charge storage electrode of a capacitor according to the present invention. FIG. 1A shows a field oxide film 2 formed on a silicon substrate 1, and a gate electrode 3. And the gate electrode line 3A, and the impurity regions 4 to be used as source and drain electrodes on both sides of the gate electrode 3 are formed, and then the first interlayer insulating film 5 is formed as a whole. The bit line 6 connected to any one of the regions (4) is formed, and the second interlayer insulating film 7 is deposited and planarized as a whole, and the nitride film 8 is formed as an etch barrier layer on the second interlayer insulating film 7. ) And an contact hole 9 communicating with the other impurity region 4 by an etching process using a charge storage electrode contact mask, and a charge storage electrode on the nitride film 8 including the contact hole 9. After depositing the first polysilicon 10 for the first, second on the top And the three sacrificial oxide films 11, 12, and 13 are sequentially deposited.

상기 제1희생 산화막(11)은 그 두께를 두껍게 형성한다.The first sacrificial oxide film 11 has a thick thickness.

제1b도는 전하저장전극 마스크를 사용한 식각공정으로 제3, 2 및 1 희생 산화막(13,12 및 11)과 제1폴리실리콘(10)을 차례로 식각하여 패턴화한 상태를 도시한 것이다.FIG. 1B illustrates a patterned state in which the third, second and first sacrificial oxide films 13, 12 and 11 and the first polysilicon 10 are sequentially etched by an etching process using a charge storage electrode mask.

상기 식각공정시 하부층인 질화막(8)은 식각장벽층 역할을 한다.The nitride layer 8, which is a lower layer in the etching process, serves as an etching barrier layer.

제1c도는 상기 상태하에서 습식식각방법으로 제2희생 산화막(12)을 일정부분 식각하여 홈을 형성한 상태를 도시한 것이다.FIG. 1C illustrates a state in which a groove is formed by etching a portion of the second sacrificial oxide film 12 by a wet etching method under the above state.

상기 제2희생 산화막(12)은 습식식각시 식각선택비가 큰 예를 들어 불순물이 도핑된 산화막을 사용하고, 상기 제1 및 3희생 산화막(11 및 13)은 식각선택비가 낮은 예를 들어 불순물이 도핑되지 않은 산화막을 사용한다.The second sacrificial oxide film 12 may be formed using, for example, an oxide doped with an impurity having a large etch selectivity during wet etching, and the first and third sacrificial oxide films 11 and 13 may have a low etch selectivity. An undoped oxide film is used.

상기 습식식각 공정시에도 질화막(8)이 식각장벽층 역할을 한다.In the wet etching process, the nitride layer 8 also serves as an etching barrier layer.

제1d도는 전체구조 상부에 전하저장전극용 제2폴리실리콘(14)을 증착하고 전면적으로 식각하여 제2희생 산화막(12)이 식각되어 들어간 부분을 포함한 패턴화된 제1폴리실리콘(10), 제1희생 산화막(11) 및 제3희생 산화막(13)측벽에 스페이서를 형성한 상태를 도시한 것이다.FIG. 1D illustrates the patterned first polysilicon 10 including a portion in which the second sacrificial oxide film 12 is etched by depositing the second polysilicon 14 for the charge storage electrode on the entire structure and etching the entire surface. A state where spacers are formed on the side walls of the first sacrificial oxide film 11 and the third sacrificial oxide film 13 is shown.

제1e도는 습식 또는 건식식각방법으로 스페이서를 이루는 제2폴리실리콘(14)내부의 제3, 2 및 1희생 산화막(13,12 및 11)을 차례로 완전히 제거한 상태를 도시한 것이다.FIG. 1E illustrates a state in which the third, second and first sacrificial oxide films 13, 12, and 11 inside the second polysilicon 14 forming the spacer are completely removed in sequence by a wet or dry etching method.

이때에도 질화막(8)은 식각장벽층 역할을 한다.In this case, the nitride film 8 also serves as an etching barrier layer.

제1f도는 반구형 폴리실리콘(15)을 전면적으로 증착하고, 다시 전면적으로 식각을 한 상태를 도시한 것으로, 이때 전하저장전극의 안쪽면은 제2희생 산화막(12)을 처음 식각으로 턱이 형성되어 있기 때문에 그 턱의 밑부분의 반구형 폴리실리콘은 식각공정 후에도 손상을 입지않고 그대로 남아 있으며, 전하저장전극 바깥부분은 약간 손상을 입어 뭉그러진 상태가 되며, 질화막(8)상의 반구형 폴리실리콘(15)은 완전히 제거되어 인접의 전하저장전극과 분리시킨 상태가 된다.FIG. 1f illustrates a state in which the hemispherical polysilicon 15 is deposited on the entire surface and then etched on the entire surface. In this case, the inner surface of the charge storage electrode is formed by first etching the second sacrificial oxide film 12. Since the hemispherical polysilicon at the bottom of the jaw remains undamaged after the etching process, the outer portion of the charge storage electrode is slightly damaged and clumped, and the hemispherical polysilicon (15) on the nitride film (8) Is completely removed and separated from the adjacent charge storage electrode.

이후, 유전체막 및 플레이트전극을 형성하여 캐패시터를 완성한다.After that, a dielectric film and a plate electrode are formed to complete the capacitor.

상술한 바에 의거한 본 발명은 전하저장전극 측벽의 상단부에 턱을 형성하므로써 그 밑부분의 반구형 폴리실리콘을 남겨 보다 증대된 축적용량을 얻을 수 있다.According to the present invention based on the above, by forming the jaw at the upper end of the side wall of the charge storage electrode, the hemispherical polysilicon at the bottom can be left to obtain an increased storage capacity.

Claims

In the method of forming a charge storage electrode of a capacitor for increasing the effective surface area,

The impurity region 4 is formed on the silicon substrate 1 to form the field oxide film 2, the gate electrode 3 and the gate electrode line 3A, and are used as source and drain electrodes on both sides of the gate electrode 3. After the formation, the first interlayer insulating film 5 is formed as a whole, the bit lines 6 connected to any one of the impurity regions are formed, and the entire second interlayer insulating film 7 is deposited and planarized. And forming a nitride film as an etch barrier layer on the second interlayer insulating film 7, and forming a contact hole 9 in communication with the other impurity region 4 by an etching process using a charge storage electrode contact mask. After depositing the first polysilicon 10 for the charge storage electrode on the nitride film 8 including the hole 9, the first, second and third sacrificial oxide films 11, 12 and 13 are sequentially deposited thereon. And an etching process using the charge storage electrode mask from the step. Etching the third, second, and first sacrificial oxide films 13, 12, and 11 and the first polysilicon 10 in turn to pattern the second sacrificial oxide film 12 by a wet etching method. Etching to form a groove, and patterning the second polysilicon 14 for charge storage electrode 14 deposited on the entire structure from the above step and etching the entire surface to etch the second sacrificial oxide film 12 Forming a spacer on the sidewalls of the first polysilicon 10, the first sacrificial oxide film 11, and the third sacrificial oxide film 13, and forming the spacer from the step by a wet or dry etching method. 14) completely removing the internal third, second and one sacrificial oxide films 13, 12 and 11, sequentially depositing the hemispherical polysilicon 15 from the above step, and etching the entire surface again to etch adjacent charges. Side separated from storage electrode Hemispherical polysilicon 15 form a charge storage electrode of the capacitor according to the particular comprising a step of completing the charge storage electrode is formed of a spacer forming a.

The first and third sacrificial oxide films 11 and 13 are oxide films not doped with impurities having a low etching selectivity, and the second sacrificial oxide films 12 are oxide films doped with impurities having a large etching selectivity. A method of forming a charge storage electrode of a capacitor, characterized in that.

The method of claim 1, wherein the process is performed without forming the nitride film (8) as the etch barrier layer.