JPH07176628A - Semiconductor memory and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory having NAND cell structure in which sufficient storage capacity can be obtained without increasing the level difference from underlying layer when a bit line is formed. CONSTITUTION:In a dynamic semiconductor memory comprising a memory cell group (NAND cell) wherein a plurality of MOS transistors are formed, while connected in series, in the memory cell region of a semiconductor substrate and a capacitor is connected with the source side of each transistor, the capacitor of the memory cell comprises a trench 5 made in the memory cell region and a diffusion layer 2, i.e., a charge storage layer, formed on the inner wall of the trench 5. A capacitor electrode 6 is formed by filling the trench 5 through a capacitor insulating film 3 except the region on the surface of substrate where the MOS transistor is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory cell structure of a dynamic semiconductor memory device (DRAM).

[0002]

2. Description of the Related Art In recent years, a NAND-type memory cell structure has been proposed in which a plurality of MOS transistors are connected in series and an information storage capacitor is connected to each source (or drain) of these MOS transistors. This memory cell structure is shown in FIG. In the figure, 101 is a substrate, 103 is a field oxide film, 106 is a capacitor electrode, 107 is a gate oxide film, 108 is a gate electrode (word line), 109 is a source / drain region, 111 is a bit line contact, 112 is interlayer insulation. A film, 113 is a bit line, 121 is a capacitor insulating film, and 122 is a plate electrode.

In this array method, since one bit line contact is required for each memory cell group connected in series, the number of bit line contacts 111 is smaller than in the case where a plurality of MOS transistors are not connected in series. ,
There is an advantage that the cell area becomes small.

However, this type of memory cell structure has the following problems. That is, since the cell used is a stack type cell and the cell area is small, the capacitor must be formed extremely high in order to obtain the required storage capacity. Therefore, when forming the upper layer wiring such as the bit line, the step difference in the underlying layer is as large as 1 μm or more, which makes it extremely difficult to process the upper layer wiring.

Further, FIG. 24 shows a conventional example of a NAND type memory cell structure using a trench type capacitor. In the figure, 133 is ap ⁺ type silicon substrate, 134 is a p type epitaxial layer, 135 is a storage electrode, 136 and 137 are n type diffusion layers, and 138 is a sidewall contact. Since this memory cell structure uses a trench type capacitor, it has an advantage that a sufficient storage capacity can be easily obtained by forming a deep trench.

However, this type of memory cell structure has the following problems. That is, since the transistor used is a vertical MOS transistor, RIE (Reac
The side surface of the trench formed by tiveIon etching is used as the channel region. Therefore, the insulation characteristics or the transistor characteristics of the gate insulating film may be affected by the damaged layer formed on the side surface of the trench during RIE.

[0007]

As described above, the conventional MO
In a NAND-type memory cell structure in which S transistors are connected in series, it is difficult to obtain a sufficient storage capacity at the time of high integration, and the step difference in the underlying layer when forming an upper layer wiring such as a bit line is extremely large. There was a problem that it was difficult.

Further, in the NAND type memory cell structure using the trench type cell, there is a problem that the gate insulating film characteristic and the transistor characteristic may be influenced by the damage layer on the side surface of the trench.

The present invention has been made to solve the above problems, and an object of the present invention is to increase the underlying step when forming an upper layer wiring such as a bit line.
It is an object of the present invention to provide a semiconductor memory device having a NAND cell structure which can obtain a sufficient storage capacity and whose gate insulating film characteristics and transistor characteristics are not affected by the damage layer on the side surface of the trench.

[0010]

In order to obtain a large storage capacity, the essence of the present invention is to use a MOS capacitor having a capacitor electrode embedded in a trench via a capacitor insulating film as an information storage capacitor, and further to form a MOS transistor. Is formed on the upper surface of the silicon substrate, not on the side surface of the trench.

That is, the present invention (claim 1) is a semiconductor memory having a memory cell group in which a plurality of MOS transistors are connected in series in a memory cell region of a semiconductor substrate and a capacitor is connected to each transistor. In the device, the capacitor is formed by forming a trench formed in the memory cell region, a charge storage layer formed on the inner wall of the trench and formed of a diffusion layer connected to the MOS transistor, and embedded in the trench via a capacitor insulating film. And a capacitor electrode formed on the surface of the substrate except at least the MOS transistor formation region.

Further, the present invention (claim 2) is a semiconductor memory having a memory cell group in which a plurality of MOS transistors are connected in series in a memory cell region of a semiconductor substrate and a capacitor is connected to each transistor. In the device, the capacitor includes a trench formed in a memory cell region, a charge storage layer formed of a diffusion layer formed on the inner wall of the trench, a trench embedded in the trench through a capacitor insulating film, and at least a substrate surface. MOS
The MOS transistor includes a capacitor electrode formed excluding the transistor formation region, and a MOS transistor is characterized in that a gate electrode is formed between trenches and a diffusion layer formed on the inner wall of the trench is used as a source / drain. .

The preferred embodiments of the present invention are as follows. (1) Capacitor electrodes function as field plates to separate elements between adjacent memory cell groups. (2) An insulating film thicker than the gate insulating film of the MOS transistor is formed on the upper and side portions of the capacitor electrode. (3) The contact to the gate electrode of the MOS transistor is formed on the capacitor electrode other than the memory cell region.

According to the present invention, in the method of manufacturing a semiconductor memory device having the above structure, a step of forming a trench in a memory cell region of a semiconductor substrate, a step of forming a diffusion layer and a capacitor insulating film on a wall surface of the trench, and a substrate A step of forming a capacitor electrode so as to fill the trench above, a step of forming an upper insulating film on the capacitor electrode,
A step of processing the capacitor electrode and the upper insulating film into a mesh shape so as to expose a space between trenches adjacent to each other in the series connection direction of the MOS transistor; a step of forming a side insulating film on a side surface of the capacitor electrode; and an exposed substrate And a step of forming a gate electrode on the surface via a gate insulating film.

[0015]

According to the present invention, a MOS having a capacitor electrode embedded in a trench via a capacitor insulating film.
With the capacitor, a sufficient storage capacitance can be obtained with a small cell area. In addition to this, by forming the capacitor electrode also on the substrate surface to form a field plate, a field insulating film for separating the memory cell groups becomes unnecessary, and the manufacturing process can be simplified.

Further, by forming the capacitor electrode in the trench and on the surface of the substrate, it is possible to realize a sufficient storage capacity without increasing the step difference of the underlying layer when forming the upper layer wiring such as the bit line. Furthermore, since the MOS transistor is formed on the surface of the silicon substrate, a highly reliable memory cell that is not affected by the RIE damage layer can be realized.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows a DR according to a first embodiment of the present invention.
2 is a plan view showing the AM cell array configuration, FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1, and FIGS. 3A and 3B are views taken along the line B- of FIG.
It is a B ', CC' sectional drawing.

The memory cell region on the silicon substrate 1 is divided into stripe-shaped element regions by the field oxide film 14. In the element region surrounded by the field oxide film 14, a memory cell group (NA) in which a plurality of memory cells (four in this embodiment) each including a MOS transistor and a trench capacitor are connected in series to the bit line 10 (NA)
ND type cell) is formed.

In the trench capacitor, four trenches 5 are formed in one NAND type cell in the element region, and n-type diffusion layers 2 (charge storage layers) are formed on the inner walls of these trenches 5, respectively. Capacitor electrode 6 is embedded in capacitor 5 via capacitor insulating film 3. The capacitor electrode 6 is connected between adjacent trenches of adjacent memory cell groups.

The MOS transistor has a trench 5
Is provided adjacent to. Specifically, the gate electrode 8 is formed on the surface of the substrate via the gate insulating film 7, and the source / drain regions are connected to the charge storage layers 2 on both sides of the gate electrode 8, respectively. Gate electrode 8
Is patterned so as to be continuous in one direction of the cell array, and this becomes a word line.

A part of the n-type diffusion layer 2 of the MOS transistor at one end of the NAND-type cell is connected to the bit line 10 via the bit line contact 9. The bit line 10 is patterned in a direction orthogonal to the gate electrode 8. Further, the capacitor electrode 6 is patterned in a direction parallel to the gate electrode 8 to become a so-called plate electrode. Incidentally, reference numeral 4 in the figure is an interlayer insulating film.

According to the present embodiment thus constructed,
Since the capacitor electrode 6 is embedded in the trench 5 to form the capacitor, it is possible to secure a sufficient storage capacitance and reduce the step difference of the base. Therefore, the upper wiring can be easily processed when forming the bit line. (Embodiment 2) FIG. 4 shows a DR according to a second embodiment of the present invention.
FIG. 5 is a plan view showing an AM cell array structure, FIG. 5 is a sectional view taken along the line AA ′ in FIG. 4, and FIGS.
It is a B ', CC' sectional drawing. The same parts as those in FIGS. 1 to 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

This embodiment is different from the first embodiment described above in that field plate isolation is used for element isolation between memory cell groups. That is, in this embodiment, the capacitor electrode 6 is also provided on the surface of the silicon substrate 1 via the oxide film 11 having a thickness larger than that of the insulating films 3 and 7. The capacitor electrode 6 is processed into a mesh shape in which only the MOS transistor portion is removed. Further, in this embodiment, the field oxide film 14 as shown in FIG.
Are not formed in the cell region, and are so-called field plate separation by the capacitor electrode 6.

With such a structure, the same effects as those of the first embodiment can be obtained, and the following effects can be obtained. That is, since the step of forming the field oxide film 14 is unnecessary, the manufacturing cost can be reduced. Further, since the capacitor electrodes 6 are processed in a mesh shape, the capacitor electrodes 6 are connected without being separated in a stripe shape, so that they are less affected by the potential change of the word line and the noise margin is widened.

Although the oxide film 11 exists under the capacitor electrode 6 in this embodiment, the capacitor insulating film 3 may be formed without forming the oxide film 11. Further, the oxide film 11 is made of another material such as silicon nitride film or Ta ₂ O.
₅ , Al ₂ O ₃ may be used. Further, these materials may be laminated.

Further, the patterning of the capacitor electrode 6 in the direction of the gate electrode 8 of this embodiment is the same as the pattern of the trench 5, but it is not always necessary to do so. That is, the capacitor electrode 6 may be mounted on the silicon substrate 1, or conversely, the capacitor electrode 6 may be patterned in the trench 5. (Third Embodiment) FIG. 7 shows a DR according to a third embodiment of the present invention.
8 is a plan view showing the AM cell array structure, FIG. 8 is a sectional view taken along the line AA ′ of FIG. 7, and FIGS. 9A and 9B are views taken along the line B- of FIG.
It is a B ', CC' sectional drawing. The same parts as those in FIGS. 1 to 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the capacitor electrode 6 is in contact with the surface of the silicon substrate 1 through the oxide film 11 and is processed into a mesh shape in which only the MOS transistor portion is removed. As a result, similar to the second embodiment, the field plates are separated by the capacitor electrodes 6.

A relatively thick oxide film 12 is formed on the capacitor electrode 6, and a relatively thick oxide film 13 is also formed on the side surface. The capacitor electrode 6 and the gate electrode 8 are separated by the oxide film 12 and the oxide film 13.

With such a structure, the same effect as in the second embodiment can be obtained, and the capacitor electrode 6 and the gate electrode 8 are separated by the oxide film 12 and the oxide film 13. Therefore, it has excellent insulation characteristics and high reliability. Further, since the gate capacitance is small, high speed operation can be expected.

Although the oxide film 13 is formed on the side surface of the capacitor electrode 6 in this embodiment, the gate insulating film 7 may be separated from the gate electrode 8 without forming the oxide film 13. Further, the oxide film 12 and the oxide film 13 may be made of other materials such as silicon nitride film, Ta ₂ O ₅ , and Al ₂ O ₃ .
Further, these materials may be laminated. The oxide film 12 and the oxide film 13 may be formed simultaneously or separately. (Embodiment 4) FIG. 10 shows D according to a fourth embodiment of the present invention.
FIG. 11 is a plan view showing the gate electrode lead-out portion at the end of the RAM memory cell array, and FIG. 11 is a sectional view taken along the line CC ′ of FIG. The same parts as those in FIGS. 1 to 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The structure of the cell array portion is similar to that of the third embodiment described above. Aluminum wiring 1 for gate electrode 8
The contact 15 with the capacitor 6 is formed on the capacitor electrode 6 which is drawn outside the memory cell region. Of course, the oxide films 12 and 13 are formed on the upper and side portions of the capacitor electrode 6.

In the structure in which the gate electrode 8 is arranged on the capacitor electrode 6, when the capacitor electrode 6 is vertically processed by RIE (reactive ion etching) or the like, the gate electrode 8 formed on the upper part thereof is subjected to RIE. The gate electrode 8 may remain along the edge of the capacitor electrode 6 during processing. This causes a short circuit between the adjacent gate electrodes 8.

On the other hand, in the present embodiment, since the contact 15 is formed on the capacitor electrode 6 which is drawn out to the outside of the memory cell region, the gate electrode 8 is formed on the edge of the capacitor electrode 6 in the portion other than the cell array. Never crosses. Therefore, the gate electrode 8 does not short-circuit with the adjacent gate electrode 8 or another wiring. In the cell array portion, the gate electrode 8 is formed at the window of the capacitor electrode 6.
Intersects with the edge of the capacitor electrode 6, but since only one gate electrode 8 exists in one window, there is no problem even if the gate electrode 8 remains at the edge of the capacitor electrode 6. Therefore, the manufacturing yield can be increased.

In this embodiment, the capacitor electrode 6 is in contact with the silicon substrate 1 through the oxide film 11, but the oxide film 11 may not be present and may be separated by the capacitor insulating film 3. Further, instead of the oxide film 12 and the oxide film 13, the gate insulating film 7 is used to form the gate electrode 8 and the capacitor electrode 6.
May be separated. Further, the aluminum wiring 16 is made of another material such as poly-Si, Cu, W, WSi ₂ , MoSi.
₂ , TiSi ₂ , Ag, etc. may be used. (Embodiment 5) FIG. 12 shows D according to the fifth embodiment of the present invention.
FIG. 12 is a plan view showing a RAM cell array configuration.
14 is a sectional view taken along the line AA 'in FIG. 14, and FIGS. 14A and 14B are sectional views taken along the line BB' and CC 'in FIG. The same parts as those in FIGS. 1 to 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the capacitor electrode 6 is in contact with the surface of the silicon substrate 1 through the oxide film 11, and is processed into a mesh shape in which only the MOS transistor portion is removed. As a result, similar to the second embodiment, the field plates are separated by the capacitor electrodes 6.

The pattern edge of the gate electrode 8 is
It exists on the capacitor electrode 6 rather than in the window of the capacitor electrode 6. That is, the entire substrate surface between the trenches 5 becomes the channel region of the MOS transistor. The n-type diffusion layer 2 as the charge storage layer serves as the source / drain of the MOS transistor.

With such a structure, the same effect as that of the third embodiment can be obtained, and the distance between the trenches 5 in the bit line 10 direction can be shortened, and the memory cell area can be reduced. Can be reduced. (Embodiment 6) FIG. 15 shows D according to a sixth embodiment of the present invention.
FIG. 16 is a plan view showing a RAM cell array configuration, and FIG.
FIG. 9 is a sectional view taken along line AA ′ of FIG. The same parts as those in FIGS. 1 to 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The memory cell region on the silicon substrate 1 is divided into stripe-shaped element regions in the direction parallel to the bit lines 10 by the field oxide film. In this element region, a memory cell group (NAND type cell) is formed in which a plurality (four in this embodiment) of memory cells each consisting of a MOS transistor and a trench capacitor are connected in series to the bit line 10. . The MOS transistor at the right end is for separating from the adjacent memory cell, which is so-called field shield separation.

In the trench capacitor, four trenches 5 are formed in one NAND type cell in the element region, the n-type diffusion layers 2 (charge storage layers) are formed on the inner walls of these trenches 5, respectively, and the trenches are formed. Capacitor electrode 6 is embedded in capacitor 5 via capacitor insulating film 3. The capacitor electrode 6 is connected between adjacent trenches of adjacent memory cell groups.

The MOS transistor has each trench 5
Is provided adjacent to. Specifically, the gate electrodes 8 and 28 are formed on the surface of the substrate with the gate insulating film 7 interposed therebetween, and the source / drain regions are formed of the n-type diffusion layer 2 on the inner wall of the trench 5. The gate electrode has two layers, and the lower layer gate electrode 8 has an inverted pattern of the capacitor electrode 6, and is arranged in an island shape only in the MOS transistor region. The upper gate electrode 28 is patterned to be continuous in one direction of the cell array,
This becomes the word line.

The n-type diffusion layer 26 of the MOS transistor at one end of the NAND cell is connected to the bit line 10 via the bit line contact 9. Bit line 10
It is patterned in a direction orthogonal to the gate electrode 28. The capacitor electrode 6 is processed into a mesh shape in which only the MOS transistor region is removed. The insulating films 12 and 13 on the upper and side portions of the capacitor electrode 6 separate the capacitor electrode 6 from the gate electrodes 8 and 28.

According to the present embodiment configured as described above,
Since the capacitor electrode 6 is embedded in the trench 5 to form the capacitor, it is possible to secure a sufficient storage capacitance and reduce the step difference of the base. Therefore, the upper wiring can be easily processed when forming the bit line. Further, since the MOS transistor is formed on the surface of the silicon substrate, a highly reliable memory cell which is not affected by the RIE damage layer can be realized.

Further, since the source / drain regions of the MOS transistor are formed by the n-type diffusion layer 2 formed on the inner wall of the trench 5, the source / drain forming step is not required, and the memory cell manufacturing step can be shortened. Is possible. Furthermore, effective gate length (effective channel length)
Since it is determined by the distance between the n-type diffusion layers 2, the effective channel length does not change due to misalignment between the gate electrode 8 and the trench 5, and the effective channel length can be easily controlled.

Further, since the gate electrode 8 and the capacitor electrode 6 are in contact with each other with the insulating film 13 interposed therebetween, the gate electrode can be processed by etching back in which RIE is performed on the entire surface, and a lithography process is not necessary. Therefore, misalignment between the capacitor electrode 6 and the gate electrode 8 does not pose a problem and the processing becomes easy. In addition, the gate electrode 28 and the capacitor electrode 6
The insulating film 12 is used to isolate Therefore, it is possible to realize a high withstand voltage of, for example, 20 V or more between the gate electrode 28 and the capacitor electrode 6, and to ensure high reliability.

The patterning of the upper layer gate electrode 28 is performed by lithography and RIE. However, since the lower layer gate electrode 8 already exists, there is a large margin for misalignment. Further, since the inside of the memory cell is flattened by the gate electrode 28, processing by lithography and RIE is easy. Furthermore, since the gate electrode is divided into two layers, a polycide gate electrode (for example, poly Si / WSi) is formed.
₂ ) or poly metal gate electrode (eg poly Si / W)
Is easy to adapt.

Next, regarding the manufacturing process of the device of this embodiment,
This will be described with reference to FIGS. 17 and 18. First, FIG.
As shown in (a), for example, an oxide film 24 is formed in the memory cell region of the silicon substrate 1, and a mask material for trench formation is prepared. Next, the oxide film 24 is processed by lithography and RIE, and the silicon substrate 1 is further etched to form the trench 5.

Next, as shown in FIG. 17B, an n-type diffusion layer 2 is formed in the trench 5, and subsequently a capacitor insulating film 3 (for example, a two-layer film of silicon nitride film / oxide film) is formed. . After that, a plate electrode 6 (for example, polysilicon) is formed so as to fill the trench 5, and an insulating film 12 (for example, a CVD oxide film) is formed thereon. continue,
The insulating film 12 and the plate electrode 6 are formed by lithography and RIE.
Processed into a mesh.

Next, as shown in FIG. 17C, after depositing an insulating film 13 (for example, a CVD oxide film) on the entire surface, R
By performing IE, it is left on the side surface of the capacitor electrode 6. Then, the gate insulating film 7 (for example, oxide film), the gate electrode 8 (for example, polysilicon), and the planarization resist 25 are formed.

Next, as shown in FIG. 18A, the flattening resist 25 and the gate electrode 8 deposited on the plate electrode 6 are removed by RIE. By this step, the gate electrode 8 is arranged in an island shape only in the MOS transistor region. Next, as shown in FIG. 18B, an upper layer gate electrode 28 (for example, tungsten silicide) is deposited on the entire surface, and then patterned by lithography and RIE so as to be continuous in one direction of the cell array. This becomes the word line.

Next, as shown in FIG. 18C, the gate electrode 8 in the portion forming the bit line contact is removed, and the n-type diffusion layer 26 is formed. Then, the bit line 10
After depositing (for example, polysilicon and tungsten silicide) on the entire surface, patterning is performed in a direction orthogonal to the gate electrode 28.

In this embodiment, the oxide film 24 is used as the mask material for forming the trench, but other materials (for example, silicon nitride film, Mo silicide, C, resist or a composite film thereof) may be used. Further, the capacitor insulating film 13 may be a thermal oxide film, a CVD oxide film, a CVD nitride film, a thermal nitride film, a tantalum oxide, a halfnium oxide, a ferroelectric film, a paraelectric film single layer film or a composite film thereof. .

Further, the lower electrode of the capacitor is the n-type diffusion layer 2, but W, Mo, Pt, Ti, Ni, Ta, A
It may be a metal such as l, Co or C, or a silicide, oxide or nitride thereof. In addition, polysilicon,
Amorphous silicon may be made n-type. Further, although polysilicon is used for the capacitor electrode 6, W, Pt,
A metal such as Ti, Ni, Ta, Al, Co or C, or a silicide, oxide or nitride thereof may be used.

Although the silicon oxide films are used for the insulating films 12 and 13, other materials such as a silicon nitride film may be used. Further, although polysilicon is used for the gate electrode 8,
A metal such as W, Mo, Ti, Ni, Pt, Ta or Co or a silicide thereof may be used. Although tungsten silicide is used for the gate electrode 11, W, Mo, T
A metal such as i, Ni, Pt, Ta, Co, or a silicide thereof may be used. Further, polysilicon and amorphous silicon may be used. (Embodiment 7) FIG. 19 is a plan view showing a cell array structure of a DRAM according to a seventh embodiment of the present invention, and FIG.
9 is a cross-sectional view taken along the line 9-9 of FIG. The same parts as those in FIGS. 15 and 16 are designated by the same reference numerals, and detailed description thereof will be omitted.

The point of difference of this embodiment from the sixth embodiment described above is the structure of the gate electrode portion. That is, in this embodiment, the gate electrode 28 is formed of a single layer film,
The edge in the bit line direction exists above the capacitor electrode 6 and does not exist on the silicon substrate.

With such a structure, it is of course possible to obtain the effect of the sixth embodiment other than the effect of forming the gate electrode into two layers, and the gate electrode 28 is processed into the capacitor electrode 6. Lithography and RIE to perform on top
Can be done easily.

21 and 22 show the manufacturing method of this embodiment. The steps up to the steps shown in FIGS. 21A and 21B are the same as those in the sixth embodiment. After that, as shown in FIG.
The insulating film 13 is left on the side surface of the capacitor electrode 6. Then, the gate insulating film 7 and the gate electrode 28 are formed.

Next, as shown in FIG. 22A, the gate electrode 28 is processed by lithography and RIE. Next, as shown in FIG. 22B, after depositing the interlayer insulating film 4, the bit line contact 9 is formed. Then, after depositing the bit line 10 on the entire surface, the bit line 10 is processed in a direction orthogonal to the gate electrode 28.

In the present embodiment, the edge of the gate electrode 28 is located above the capacitor electrode 6, but any structure may be used as long as the effective channel length is determined by the distance between the n-type diffusion layers 2 on the sidewalls of the trench. Therefore, the capacitor electrode 6 is not always
Need not be above the n-type diffusion layer 2 and the gate electrode 2
The gate length may be short within a range where offset with 8 cannot be performed. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0059]

As described above, according to the present invention, a MOS capacitor having a capacitor electrode embedded in a trench via a capacitor insulating film is used as an information storage capacitor, thereby having a sufficient storage capacity. NA capable of achieving sufficient storage capacity without increasing the underlying step when forming an upper layer wiring such as a bit line.
It is possible to realize a semiconductor memory device having an ND cell structure.

[Brief description of drawings]

FIG. 1 is a plan view showing a cell array configuration of a DRAM according to a first embodiment.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

3 is a sectional view taken along the line BB ′ and CC ′ of FIG.

FIG. 4 is a plan view showing a cell array configuration of a DRAM according to a second embodiment.

5 is a sectional view taken along the line AA ′ in FIG.

6 is a sectional view taken along the line BB ′ and CC ′ of FIG.

FIG. 7 is a plan view showing a cell array configuration of a DRAM according to a third embodiment.

8 is a cross-sectional view taken along the line AA ′ of FIG.

9 is a sectional view taken along line BB ′ and CC ′ of FIG. 7.

FIG. 10 is a plan view showing a gate electrode lead-out portion at a cell array terminal of a DRAM according to a fourth embodiment.

11 is a sectional view taken along the line CC ′ of FIG.

FIG. 12 is a plan view showing a cell array configuration of a DRAM according to a fifth embodiment.

13 is a cross-sectional view taken along the line AA ′ of FIG.

14 is a sectional view taken along the line BB ′ and CC ′ of FIG.

FIG. 15 is a plan view showing a cell array configuration of a DRAM according to a sixth embodiment.

16 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 17 is a cross-sectional view showing the first half of the manufacturing process of the sixth embodiment.

FIG. 18 is a cross-sectional view showing the latter half of the manufacturing process of the sixth embodiment.

FIG. 19 is a plan view showing a cell array configuration of a DRAM according to a seventh embodiment.

20 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 21 is a cross-sectional view showing the first half of the manufacturing process of the seventh embodiment.

FIG. 22 is a cross-sectional view showing the latter half of the manufacturing process of the seventh example.

FIG. 23 is a plan view and a cross-sectional view showing a cell array configuration of a conventional DRAM.

FIG. 24 is a cross-sectional view showing a cell array configuration of a conventional DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2, 26 ... N-type diffusion layer 3 ... Capacitor insulating film 4 ... Interlayer insulating film 5 ... Trench 6 ... Capacitor electrode 7 ... Gate insulating film 8, 28 ... Gate electrode 9 ... Bit line contact 10 ... Bit line 11 , 12, 13, 24 ... Oxide film 14 ... Field oxide film 15 ... Contact 16 ... Aluminum wiring 25 ... Planarization resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 7210-4M H01L 27/10 325 D

Claims (5)

[Claims] 1. A plurality of Ms in a memory cell region of a semiconductor substrate.
In a semiconductor memory device having a memory cell group formed by connecting OS transistors in series and connecting a capacitor to each transistor, the capacitor is formed in a trench formed in the memory cell region and an inner wall of the trench. From a charge storage layer formed of a diffusion layer connected to the MOS transistor, and a capacitor electrode formed in the trench via a capacitor insulating film and formed on the substrate surface except at least the MOS transistor formation region. A semiconductor memory device characterized by the following. 2. A plurality of Ms in a memory cell region of a semiconductor substrate.
In a semiconductor memory device having a memory cell group formed by connecting OS transistors in series and connecting a capacitor to each transistor, the capacitor is formed in a trench formed in the memory cell region and an inner wall of the trench. And a capacitor electrode formed by being buried in the trench via a capacitor insulating film and formed on the surface of the substrate except at least a MOS transistor forming region. A semiconductor memory device, wherein a gate electrode is formed between adjacent trenches, and a diffusion layer formed on the inner wall of the trench is used as a source / drain. 3. The semiconductor memory according to claim 1, wherein an insulating film having a thickness larger than that of the gate insulating film of the MOS transistor is formed on the upper and side portions of the capacitor electrode. apparatus. 4. The semiconductor according to claim 1, wherein a contact to the gate electrode of the MOS transistor is formed on the capacitor electrode extended outside the memory cell region. Storage device. 5. A plurality of Ms in a memory cell region of a semiconductor substrate.
In a method of manufacturing a semiconductor memory device having a memory cell group in which OS transistors are connected in series and a capacitor is connected to each transistor, a step of forming a trench in a memory cell region of a semiconductor substrate, and a diffusion layer on a wall surface of the trench A step of forming a capacitor insulating film, a step of forming a capacitor electrode on the substrate so as to fill the trench, a step of forming an upper insulating film on the capacitor electrode, and a step of forming the capacitor electrode and the upper insulating film. A step of forming a mesh so as to expose the trenches adjacent to each other in the series connection direction of the MOS transistors; a step of forming a side insulating film on the side surface of the capacitor electrode; and a step of forming a gate insulating film on the exposed substrate surface. And a step of forming a gate electrode therethrough. .