KR930012121B1

KR930012121B1 - Method of fabricating a stacked capacitor

Info

Publication number: KR930012121B1
Application number: KR1019910011936A
Authority: KR
Inventors: 최봉균
Original assignee: 금성일렉트론 주식회사; 문정환
Priority date: 1991-07-13
Filing date: 1991-07-13
Publication date: 1993-12-24
Also published as: KR930003388A

Abstract

The stacked capacitor of a high integrated MOS memory element is mfd. by (a) forming a field oxide film (2) on the silicon substrate, and patterning a gate (3), (b) depositing an oxide film (6), a nitride film (7) and a SOG (8) on the whole surface, and depositing a polycrystalline silicon film (9) for a first plate on the etched portion of the SOG (8), (c) etching back the film (9), and selectively etching the SOG (8), (d) depositing a first ONO (10) and a polycrystalline silicon film (11) for a first node, and etching the SOG (8) to form a buried contact, (e) depositing a polycrystalline silicon film (12) for a second node on the contact, and forming a second ONO (13) and a polycrystalline silicon film (14) for a second plate, and (f) etching the SOG (8), and depositing a polycrystalline silicon film (15) for a third plate.

Description

Manufacturing method of multilayer capacitor

제1도는 종래의 커패시터 제조 공정단면도.1 is a cross-sectional view of a conventional capacitor manufacturing process.

제2도는 본발명의 적층형 커패시터의 제조 공정단면도.2 is a cross-sectional view of the manufacturing process of the multilayer capacitor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 기판 2, 3, 4, 6 : 산화막1: silicon substrate 2, 3, 4, 6: oxide film

5 : 게이트 7 : 질화막5 gate 7 nitride film

8 : SOG 10, 13 : ONO층8: SOG 10, 13: ONO layer

9, 11, 12, 14, 15 : 다결정 규소막9, 11, 12, 14, 15: polycrystalline silicon film

본발명은 고집적 모스(MOS) 기억소자의 적층형 커패시터 제조방법에 관한 것으로 특히 정전용량의 증대로 인한 소자의 신뢰성 개선 및 집적도 향상을 얻을 수 있도록 한 것이다.The present invention relates to a method of manufacturing a stacked capacitor of a highly integrated MOS memory device, and in particular, to improve the reliability and integration of the device due to the increase in capacitance.

종래의 적층형 커패시터 제조방법을 제1도를 이용하여 설명하면 다음과 같다. 즉, 제1도(a)와 같이 국부산화막 증착법으로 필드산화막(2)을 형성하여 필드영역과 액티브영역을 구분하고 트랜지스터 형성을 위한 게이트 절연막으로서 고열 확산로에서 게이트 산화막을 성장시키고, 그 위에 도핑된 다결정 규소막이나 폴리사이드막을 성장시켜 마스크공정과 식각을 통해 게이트(5)를 형성한 뒤 LDD구조를 위한 n-이온주입하고 측벽(4)을 형성하여 소오스/드레인 n+이온주입을 한다.The conventional multilayer capacitor manufacturing method will be described with reference to FIG. 1 as follows. That is, as shown in FIG. 1A, the field oxide film 2 is formed by the local oxide film deposition method to distinguish the field region from the active region, and the gate oxide film is grown in a high thermal diffusion path as a gate insulating film for transistor formation, and doped thereon. The grown polycrystalline silicon film or polyside film is grown to form a gate 5 through a mask process and etching, and then n-ion implantation for LDD structures and sidewalls 4 are formed to perform source / drain n + ion implantation.

그리고 제1도(b)와 같이 게이트(5)의 다결정 규소막과 커패시터 노드용 다결정 규소막을 절연시키기 위해 산화막(6)을 증착하고 산화막사이 접합부위를 커패시터의 노드와 연결될 수 있도록 마스크 공정과 식각을 통해 베리드 콘택을 형성하여 노드룔 다결정 규소막(11)을 증착한 후 감광막(16)을 사용한 사진/식각 공정으로 노드를 정의하고 감광막(16)을 제거한다. 그 다음 제1도(c)와 같이 유전체(예를 들어 O-N-O나 N-O)(7)를 도포하고 그 위에 커패시터의 플레이트용 다결정 규소막(9)을 증착시키고 도핑한 다음 마스크공정과 건식식각으로 불필요한 부위를 제거하고 감광체를 깨끗이 제거하여 적층형 커패시터를 제조한다.Then, as shown in FIG. 1 (b), an oxide layer 6 is deposited to insulate the polycrystalline silicon layer of the gate 5 from the polysilicon layer for the capacitor node, and a mask process and an etching process are performed so that the junction between the oxide layers can be connected to the node of the capacitor. After the buried contact is formed through the deposition of the node N polycrystalline silicon film 11, the node is defined by a photo / etch process using the photosensitive film 16, and the photosensitive film 16 is removed. Then, as shown in Fig. 1 (c), a dielectric (for example, ONO or NO) 7 is applied and the polycrystalline silicon film 9 for the plate of the capacitor is deposited and doped thereon, which is then unnecessary by a mask process and dry etching. The multilayer capacitor is manufactured by removing the portion and removing the photoconductor.

그러나 이와같이 제조한 종래의 적층형 커패시터는 정전용량이 적어 디램(DRAM)의 충전 특성과 소자의 신뢰성도 저하되고 집적도가 낮다.However, the conventional multilayer capacitor manufactured as described above has a low capacitance, thereby lowering the charging characteristics of the DRAM, the reliability of the device, and having a low degree of integration.

본발명은 이와같은 문제점들을 해결하기 위한 것으로 본발명의 목적은 커패시터 노드로 사용되는 다결정 규소막 아래에 커패시터 면적 확장용막과 커패시터의 플레이트용 다결정 규소막을 형성하여 정전 용량의 증대에 의한 소자의 신뢰성 개선 및 집적도 향상에 있다. 이러한 목적을 달성하기 위한 본발명의 실시예를 제2도를 이용하여 보다 상세히 설명하면 다음과 같다. 먼저 제2도(a)와 같이, 실리콘기판(1)에 필드산화막(2)을 성장시켜 액티브영역과 필드영역을 구분하고 다결정규소막과 산화막(3)을 증착하여 마스크공정과 식각을 통해 게이트(5)을 형성한 뒤 LDD 구조를 위한 n-이온주입하고 측벽(4)을 형성하여 n+소오스/드레인 이온주입한다.The present invention solves these problems, and an object of the present invention is to improve the reliability of the device by increasing the capacitance by forming a capacitor area expansion film and a capacitor plate polycrystalline silicon film under the polycrystalline silicon film used as the capacitor node. And degree of integration. An embodiment of the present invention for achieving this purpose will be described in more detail with reference to FIG. 2. First, as shown in FIG. 2A, the field oxide film 2 is grown on the silicon substrate 1 to separate the active region and the field region, and the polysilicon film and the oxide film 3 are deposited to form a gate through a mask process and etching. After forming (5), n-ion implantation for the LDD structure is formed, and sidewalls 4 are formed, and n + source / drain ion implantation is performed.

그리고 제2도(b)와 같이 산화막(6)을 증착하고 산화막 보호용 질화막(7)을 500Å~1,000Å두께로 증착한 뒤 그위에 단차가 가장 높은 부위가 1,000Å~2,000Å두께가 되도록 SOG(Spin on glass)(8)을 증착시킨후 마스크 공정을 거쳐 SOG(8)의 소정의 부위를 수직식각하고 감광막을 제거한 뒤 1차 플레이트용 다결정 규소막(9)을 3,000??~5,000??두께로 SOG(8)사이에 완전히 채워지도록 증착하여 도핑한다.Then, as shown in FIG. 2 (b), the oxide film 6 is deposited, and the oxide film protective nitride film 7 is deposited at a thickness of 500 kV to 1,000 kPa, and the SOG (1000 kPa to 2,000 kPa) thickness is formed at the highest step thereon. After depositing the spin on glass (8), through a mask process, a predetermined portion of the SOG (8) is vertically etched, the photoresist film is removed, and the polysilicon film 9 for the primary plate is 3,000 ?? to 5,000 ?? And doped so as to be completely filled between the SOGs (8).

또한 제2도(c)와 같이 SOG(8)가 들어날때까지 1차 플레이트용 다결정 규소막(9)을 에치백하고 다시 마스크공정을 거쳐 1차 플레이트용 다결정 규소막(9)과 베리드 콘택사이의 SOG(8)를 식각한 뒤 감광막을 제거한 후 제2도(d)와 같이 1차 ONO(산화막, 질화막, 산화막)(10)을 형성하고 1차 노드용 다결정 규소막(11)을 베리드 콘택부위와 1차 플레이트용 다결정 규소막(9) 사이에 완전히 채워지도록 2,000Å~3,000Å두께로 증착한 뒤 마스크공정을 통해 SOG(8)와 1차 ONO막(10)을 동시에 식각하여 베리드 콘택을 형성하고, 감광막을 제거한다. 제2도(e)와 같이 노드용 다결정 규소막(12)을 1,000Å~2,000Å증착시켜 도핑하고 마스크 공정을 거쳐 노드를 정의하여 건식식각을 한후 감광막을 제거한다. 이때 1,2차 노드용 다결정 규소막(11,12)과 1차 ONO막(10)을 같이 식각한다.In addition, as shown in FIG. 2C, the polycrystalline silicon film 9 for the primary plate is etched back until the SOG 8 enters, followed by a mask process, and the buried contact with the polycrystalline silicon film 9 for the primary plate. After etching the SOG (8) therebetween, the photoresist film is removed, and then a primary ONO (oxide film, nitride film, oxide film) 10 is formed as shown in FIG. 2 (d), and the polysilicon film 11 for the primary node is obtained. After depositing at 2,000Å ~ 3,000Å thickness so as to be completely filled between the contact region and the polycrystalline silicon film 9 for the primary plate 9, the SOG 8 and the primary ONO film 10 were simultaneously etched through the mask process to obtain a berry. De-contact is formed and the photoresist film is removed. As shown in FIG. 2E, the polycrystalline silicon film 12 for the node is deposited and doped by 1,000 mV to 2,000 mV, and the node is defined through dry etching to remove the photoresist. At this time, the polycrystalline silicon films 11 and 12 for the primary and secondary nodes and the primary ONO film 10 are etched together.

그리고 2차 ONO(13)을 형성하고 2차 플레이트용 다결정 규소막(14)을 1,000Å~2,000Å으로 증착하여 도핑한 뒤 제2도(f)와 같이 마스크 공정을 거쳐 2차 플레이트용 다결정 규소막(14)과 2차 ONO막(13)을 건식식각하고 아래의 SOG(8)를 습식식각한 뒤 감광막을 제거하고 3차 플레이트용 다결정 규소막(15)을 1,500Å~3,000Å으로 증착하여 1,2차 플레이트용 다결정 규소막(9,14)과 연결되도록 한 후 도핑한다. 그리고 제2도(g)와 같이 마스크공정을 거쳐 건식식각을 통해 불필요한 부위를 제거하고 감광막을 깨끗이 제거함으로써 적층형 커패시터가 완성된다.Then, the secondary ONO 13 is formed, and the polycrystalline silicon film 14 for the secondary plate 14 is deposited and doped at 1,000 to 2,000 microseconds, and then subjected to a mask process as shown in FIG. Dry etching the film 14 and the secondary ONO film 13, wet etching the SOG 8 below, removing the photoresist film, and depositing the polycrystalline silicon film 15 for the tertiary plate at 1,500 Å to 3,000 Å Doping is performed after connecting to the polycrystalline silicon films 9 and 14 for the primary and secondary plates. Then, as shown in FIG. 2 (g), the multilayer capacitor is completed by removing unnecessary parts through dry etching and removing the photoresist film.

이상에서 설명한 바와같은 본발명은 커패시터 노드로 사용되는 다결정 규소막아래에 커패시터 면적 확장용 막과 커패시터의 플레이트용 다결정 규소막을 형성하여 정전용량을 확대시킬 수 있어 소자의 신뢰성을 개선시킴과 아울러 집적도를 향상시킬 수 있는 효과가 있다.As described above, the present invention forms a capacitor area expansion film and a capacitor plate polycrystalline silicon film under the polycrystalline silicon film used as a capacitor node, which can increase capacitance, thereby improving device reliability and integration. There is an effect that can be improved.

Claims

The process of growing the field oxide film 2 on the silicon substrate 1 and patterning it on the gate 3, depositing the oxide film 6 and the nitride film 7 on the entire surface, and depositing and patterning the SOG 8 Depositing and doping the primary plate polycrystalline silicon film 9 on the etched portion of the SOG 8 in the state, and the primary plate polycrystalline silicon film 9 until the SOG 8 is exposed. Selectively etching the SOG 8 between the polycrystalline silicon film 9 for primary plate and the primary plate, depositing a primary ONO 10 and a polysilicon film 11 for the primary node, and depositing the primary node Etching the SOG (8) between the polycrystalline silicon film (11) to form a buried contact, and depositing and doping a polysilicon film (12) for the secondary node on the contact to the secondary ONO (13) and 2 Forming a polycrystalline silicon film 14 for a secondary plate to remove unnecessary portions; and etching the SOG 8 above to form a polycrystalline tertiary plate Method of manufacturing a stack-type capacitor by depositing a doped somak 15 and removing unnecessary portions.

The thickness of the oxide film 6 is 1,000 kPa to 3,500 kPa, the thickness of the nitride film 7 is 500 kPa to 1,000 kPa, and the thickness of the SOG 8 is 1,000 kPa to 2.000 kPa. Method of manufacturing a multilayer capacitor, characterized in that

2. The polycrystalline silicon film 9 for primary plates according to claim 1, wherein the thickness of the polycrystalline silicon film 9 for primary plates is 3,000 kPa to 5,000 kPa, the polycrystalline silicon film 11 for primary nodes is 2,000 kPa to 3,000 kPa, and the polycrystalline silicon for secondary nodes Multilayer capacitors having a film thickness of 1,000 kPa to 2,000 kPa, the thickness of the polycrystalline silicon film 14 for secondary plates 14 to 2000 kPa and the thickness of the polycrystalline silicon film 15 for tertiary plates 1,500 kPa to 3,000 kPa Manufacturing method.