KR940016804A

KR940016804A - Capacitor Formation Method of Semiconductor Device

Info

Publication number: KR940016804A
Application number: KR1019920027309A
Authority: KR
Inventors: 박상훈
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-12-31
Filing date: 1992-12-31
Publication date: 1994-07-25
Also published as: KR960005575B1

Abstract

본 발명은 반도체 기판(21)에 필드산화막(22), 게이트 산화막(23), 게이트 전극(24), 상기 게이트 전극(24)의 측벽에 형성되는 스페이서 산화막(26), 이온 주입에 의한 소오스/드레인 영역(25)을 형성하고 절연 산화막(27)을 증착하는 제1단계, 상기 제1단계 후에 이중성 레지스트(dual-tone resist)(28)를 도포하여 광대역의 자외선을 노광시켜 현상한 다음 소오스/드레인 영역(25) 상부의 절연 산화막(27)을 식각에 의해 오픈(open)하는 제2단계, 상기 제2단계 후에 현상된 상기 이중성 레지스트(28)를 마스크로 하여 오픈된 상기 절연 산화막(27)을 식각하는 제3단계, 상기 제3단계 후에 상기 상기 이중성 레지스트(28)를 재 노광시켜 산화막의 요철 형성부위를 제외한 상기 이중성 레지스트(28)를 제거하여 절연 산화막(27)을 노출시키는 제4단계, 상기 제4단계 후에 상기 노출된 절연 산화막(27)을 식각하여 소오스/드레인 영역(25)이 드러나도록한 다음에 잔류된 상기 이중성 레지스트(28) 제거하고 전하보존용 전도물질(29)을 증착하여 패턴하는 제5단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 캐패시터 형성 방법에 관한 것이다.According to the present invention, the field oxide film 22, the gate oxide film 23, the gate electrode 24, the spacer oxide film 26 formed on the sidewalls of the gate electrode 24, and the source / implantation in the semiconductor substrate 21 are provided. After the first step of forming the drain region 25 and depositing the insulating oxide layer 27, a dual-tone resist 28 is applied after the first step to expose and develop broadband ultraviolet light, and then the source / A second step of opening the insulating oxide film 27 on the drain region 25 by etching, and the insulating oxide film 27 opened by using the dual resist 28 developed after the second step as a mask. A third step of etching and a fourth step of exposing the insulating resistive layer 27 by exposing the dual resist 28 to remove the dual resist 28 except the uneven portions of the oxide layer. The exposed section after the fourth step. A fifth step of etching the soft oxide layer 27 to expose the source / drain regions 25, and then removing the remaining dual resist 28 and depositing and patterning the charge preservation conductive material 29. The present invention relates to a method for forming a capacitor of a semiconductor device.

Description

Capacitor Formation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 반도체 소자 캐패시터 제조 공정.2 is a semiconductor device capacitor manufacturing process according to the present invention.

Claims

In the method of forming a capacitor of a semiconductor device, the field oxide film 22, the gate oxide film 23, the gate electrode 24, the spacer oxide film 26 formed on the sidewalls of the gate electrode 24, and the semiconductor substrate 21, A first step of forming the source / drain regions 25 by ion implantation and depositing the insulating oxide film 7, and after the first step, a dual-tone-resist 28 is applied to apply broadband ultraviolet rays. After exposure and development, the second step of opening the insulating oxide film 27 over the source / drain region 25 by etching, and using the dual resist 28 developed after the second step as a mask, is opened. A third step of etching the insulating oxide film 27, and after the third step, the dual resist 28 is re-exposed to remove the dual resist 28 except for an uneven portion of the oxide film, thereby removing the insulating oxide 27. Exposing the fourth step, the After the fourth step, the exposed insulating oxide layer 27 is etched to expose the source / drain regions 25, and then, the residual duality resist 28 is removed and a charge preservation conductive material 29 is deposited. And a fifth step of forming a capacitor of the semiconductor device.

The method of claim 1, wherein the etching thickness of the insulating oxide layer (27) in the second step is 1/2 of the thickness of the insulating oxide layer (27).

※ Note: The disclosure is based on the initial application.