KR970013385A - Fully self-aligned thin film transistor and its manufacturing method - Google Patents

Fully self-aligned thin film transistor and its manufacturing method Download PDF

Info

Publication number
KR970013385A
KR970013385A KR1019950023862A KR19950023862A KR970013385A KR 970013385 A KR970013385 A KR 970013385A KR 1019950023862 A KR1019950023862 A KR 1019950023862A KR 19950023862 A KR19950023862 A KR 19950023862A KR 970013385 A KR970013385 A KR 970013385A
Authority
KR
South Korea
Prior art keywords
forming
gate electrode
source
mask
semiconductor
Prior art date
Application number
KR1019950023862A
Other languages
Korean (ko)
Other versions
KR0156215B1 (en
Inventor
이주홍
Original Assignee
구자홍
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 구자홍, 엘지전자 주식회사 filed Critical 구자홍
Priority to KR1019950023862A priority Critical patent/KR0156215B1/en
Publication of KR970013385A publication Critical patent/KR970013385A/en
Application granted granted Critical
Publication of KR0156215B1 publication Critical patent/KR0156215B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 완전 자기정렬형 박막트랜지스터 및 그 제조방법에 관한 것으로, 소오스 및 드레인과 채널간의 저항을 감소시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fully self-aligning thin film transistor and a method for manufacturing the same, and to reduce the resistance between the source and the drain and the channel.

본 발명은 절연기판 상부에 게이트전극을 형성하는 공정과, 상기 게이트전극이 형성된 기판 전면에 게이트절연막, 반도체층, 상부절연막을 연속으로 형성하는 공정, 상기 게이트전극을 마스크로 이용한 배면노광 기술에 의해 상기 상부절연막을 패터닝하여 에치스토퍼를 형성하는 공정, 상기 에치스토퍼를 마스크로 하여 상기 반도체층에 불순물을 선택적으로 주입하여 불순물을 함유한 반도체 영역을 형성하는 공정, 상기 반도체층을 소정의 활성영역 패턴으로 패터닝하는 공정, 기판 전면에 ITO를 증착하는 공정, 상기 ITO층상에 네가티브형 포토레지스트를 도포하는 공정, 상기 게이트전극을 마스크로 이용한 배면노광 기술에 의해 상기 네가티브형 포토레지트스를 노광 및 현상하여 소정의 포토레지스트 패턴을 형성하는 공정, 상기 포토레지스트패턴을 마스크로 하여 상기 ITO층을 식각하여 소오스 및 드레인 리드부를 형성하는 공정, 상기 포토레지스트패턴을 제거하는 공정, 상기 소오스 및 드레인 리드부상에 소오스 및 드레인 전극을 각각 형성하는 공정으로 이루어지는 완전 자기정렬형 박막트랜지스터 제조방법을 제공한다.The present invention provides a method of forming a gate electrode on an insulating substrate, a process of continuously forming a gate insulating film, a semiconductor layer, and an upper insulating film on an entire surface of the substrate on which the gate electrode is formed, and a back exposure technique using the gate electrode as a mask. Patterning the upper insulating layer to form an etch stopper; selectively implanting impurities into the semiconductor layer using the etch stopper as a mask; forming a semiconductor region containing impurities; forming the semiconductor layer as a predetermined active region pattern Exposing and developing the negative photoresist by a patterning process, a process of depositing ITO on the entire surface of the substrate, a process of applying a negative photoresist on the ITO layer, and a back exposure technique using the gate electrode as a mask. Forming a predetermined photoresist pattern; Forming the source and drain lead portions by etching the ITO layer using a mask as a mask, removing the photoresist pattern, and forming source and drain electrodes on the source and drain lead portions, respectively. Provided is a thin film transistor manufacturing method.

Description

완전 자기정렬형 박막트랜지스터 및 그 제조방법Fully self-aligned thin film transistor and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 완전 자기정렬형 박막트랜지스터 단면구조도.2 is a cross-sectional view of a fully self-aligned thin film transistor according to the present invention.

Claims (2)

절연기판과, 상기 절연기판상에 형성된 게이트전극, 상기 게이트전극과 절연기판상에 형성된 게이트절연막, 상기 게이트절연막 상부에 형성된 반도체 활성층, 상기 반도체 활성층상의 상기 게이트전극 상부에 형성된 에치스토퍼, 상기 에치스토퍼 양단의 상기 반도체 활성층 영역에 형성된 불순물이 함유된 반도체영역, 상기 에치스토퍼 양측의 상기 반도체 활성층 영역상에 각각 형성된 ITO로 이루어진 소오스 및 드레인 리드부 및 상기 소오스 및 드레인 리드부상에 각각 형성된 소오스 및 드레인전극으로 구성된 것을 특징으로 하는 완전 자기정렬형 박막트랜지스터.An insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the gate electrode and the insulating substrate, a semiconductor active layer formed on the gate insulating film, an etch stopper formed on the gate electrode on the semiconductor active layer, and an etch stopper A source and drain lead formed of a semiconductor region containing impurities formed in the semiconductor active layer regions at both ends, and an ITO formed on the semiconductor active layer regions on both sides of the etch stopper, and a source and drain electrode formed on the source and drain lead portions, respectively. Fully self-aligned thin film transistor, characterized in that consisting of. 절연기판에 게이트전극을 형성하는 공정과, 상기 게이트전극이 형성된 기판 전면에 게이트절연막, 반도체층, 상부절연막을 연속으로 형성하는 공정, 상기 게이트전극을 마스크로 이용한 배면 노광으로 상기 상부절연막을 패터닝하여 에치스토퍼를 형성하는 공정, 상기 에치스토퍼를 마스크로 하여 상기 반도체층에 불순물을 선택적으로 주입하여 불순물을 함유한 반도체영역을 형성하는 공정, 상기 반도체층을 소정의 활성영역패턴으로 패터닝하는 공정, 기판 전면에 ITO를 증착하는 공정, 상기 ITO층상에 네가티브형 포토레지스트를 도포하는 공정, 상기 게이트전극을 마스크로 이용한 배면노광으로 상기 네가티브형 포토레지트스를 노광 및 현상하여 선택적으로 포토레지스트 패턴을 형성하는 공정, 상기 포토레지스트패턴을 마스크로 하여 상기 절연층상의 ITO층을 식각하여 소오스 및 드레인 리드부를 형성하는 공정, 상기 포토레지스트패턴을 제거하는 공정, 상기 소오스 및 드레인 리드부상에 소오스 및 드레인 전극을 각각 형성하는 공정으로 이루어지는 것을 특징으로 하는 완전 자기정렬형 박막트랜지스터 제조방법.Patterning the upper insulating film by forming a gate electrode on an insulating substrate, forming a gate insulating film, a semiconductor layer, and an upper insulating film on the entire surface of the substrate on which the gate electrode is formed, and by back exposure using the gate electrode as a mask. Forming an etch stopper; selectively implanting impurities into the semiconductor layer using the etch stopper as a mask; forming a semiconductor region containing impurities; patterning the semiconductor layer into a predetermined active region pattern; substrate A process of depositing ITO on the entire surface, a process of applying a negative photoresist on the ITO layer, and exposing and developing the negative photoresist by back exposure using the gate electrode as a mask to selectively form a photoresist pattern. Step, the section using the photoresist pattern as a mask Forming a source and drain lead by etching the layered ITO layer, removing the photoresist pattern, and forming a source and a drain electrode on the source and drain lead, respectively. Type thin film transistor manufacturing method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950023862A 1995-08-02 1995-08-02 Fully self-aligned thin film transistor KR0156215B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950023862A KR0156215B1 (en) 1995-08-02 1995-08-02 Fully self-aligned thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950023862A KR0156215B1 (en) 1995-08-02 1995-08-02 Fully self-aligned thin film transistor

Publications (2)

Publication Number Publication Date
KR970013385A true KR970013385A (en) 1997-03-29
KR0156215B1 KR0156215B1 (en) 1998-10-15

Family

ID=19422687

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950023862A KR0156215B1 (en) 1995-08-02 1995-08-02 Fully self-aligned thin film transistor

Country Status (1)

Country Link
KR (1) KR0156215B1 (en)

Also Published As

Publication number Publication date
KR0156215B1 (en) 1998-10-15

Similar Documents

Publication Publication Date Title
KR960012564A (en) Thin film transistor and method of forming the same
KR960024604A (en) Dual channel thin film transistor and its manufacturing method
KR940022874A (en) Method of manufacturing thin film transistor
KR970013385A (en) Fully self-aligned thin film transistor and its manufacturing method
KR970030892A (en) Structure and manufacturing method of thin film transistor
KR960026570A (en) Highly Integrated Semiconductor Device Manufacturing Method
KR960009073A (en) Manufacturing Method of Field Effect Transistor
KR970054379A (en) Manufacturing method of LDD MOS device
KR970003685A (en) Manufacturing method of MOS field effect transistor
KR940010271A (en) Semiconductor device manufacturing method
KR970054506A (en) Method of manufacturing a fully self-matching thin film transistor using a laser
KR950021761A (en) Method of manufacturing thin film transistor
KR960026973A (en) Method of manufacturing thin film transistor
KR950021744A (en) Semiconductor Thin Film Transistor Manufacturing Method
KR970054481A (en) Thin film transistor manufacturing method
KR970054258A (en) Method of manufacturing thin film transistor
KR940016920A (en) Manufacturing method of bottom gate thin film transistor
KR970054510A (en) Method of manufacturing thin film transistor
KR950034828A (en) Manufacturing method and gate structure of MOS transistor using copper electrode
KR950024331A (en) Semiconductor device manufacturing method
KR970004085A (en) Thin film transistor and method of manufacturing same
KR940016804A (en) Capacitor Formation Method of Semiconductor Device
KR970023880A (en) Method of manufacturing thin film transistor
KR940016911A (en) Method of manufacturing thin film transistor
KR940027199A (en) Method of manufacturing thin film transistor

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070629

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee